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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07002/**
3 * (C) Copyright 2014, Cavium Inc.
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07004**/
5
6#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07007#include <cpu_func.h>
Simon Glass9d922452017-05-17 17:18:03 -06008#include <dm.h>
Simon Glass2cf431c2019-11-14 12:57:47 -07009#include <init.h>
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070010#include <malloc.h>
11#include <errno.h>
Simon Glass90526e92020-05-10 11:39:56 -060012#include <net.h>
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070013#include <linux/compiler.h>
14
Sergey Temerkhanov3ed2ece2015-10-14 09:55:52 -070015#include <cavium/atf.h>
Alexander Grafd473f0c2016-03-04 01:09:48 +010016#include <asm/armv8/mmu.h>
Sergey Temerkhanov3ed2ece2015-10-14 09:55:52 -070017
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070018#if !CONFIG_IS_ENABLED(OF_CONTROL)
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070019#include <dm/platform_data/serial_pl01x.h>
20
21static const struct pl01x_serial_platdata serial0 = {
22 .base = CONFIG_SYS_SERIAL0,
23 .type = TYPE_PL011,
24 .clock = 0,
25 .skip_init = true,
26};
27
28U_BOOT_DEVICE(thunderx_serial0) = {
29 .name = "serial_pl01x",
30 .platdata = &serial0,
31};
32
33static const struct pl01x_serial_platdata serial1 = {
34 .base = CONFIG_SYS_SERIAL1,
35 .type = TYPE_PL011,
36 .clock = 0,
37 .skip_init = true,
38};
39
40U_BOOT_DEVICE(thunderx_serial1) = {
41 .name = "serial_pl01x",
42 .platdata = &serial1,
43};
44#endif
45
46DECLARE_GLOBAL_DATA_PTR;
47
Alexander Grafd473f0c2016-03-04 01:09:48 +010048static struct mm_region thunderx_mem_map[] = {
49 {
York Suncd4b0c52016-06-24 16:46:22 -070050 .virt = 0x000000000000UL,
51 .phys = 0x000000000000UL,
Alexander Grafd473f0c2016-03-04 01:09:48 +010052 .size = 0x40000000000UL,
53 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
54 }, {
York Suncd4b0c52016-06-24 16:46:22 -070055 .virt = 0x800000000000UL,
56 .phys = 0x800000000000UL,
Alexander Grafd473f0c2016-03-04 01:09:48 +010057 .size = 0x40000000000UL,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
59 PTE_BLOCK_NON_SHARE,
60 }, {
York Suncd4b0c52016-06-24 16:46:22 -070061 .virt = 0x840000000000UL,
62 .phys = 0x840000000000UL,
Alexander Grafd473f0c2016-03-04 01:09:48 +010063 .size = 0x40000000000UL,
64 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65 PTE_BLOCK_NON_SHARE,
66 }, {
67 /* List terminator */
68 0,
69 }
70};
71
72struct mm_region *mem_map = thunderx_mem_map;
73
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070074int board_init(void)
75{
76 return 0;
77}
78
79int timer_init(void)
80{
81 return 0;
82}
83
Sergey Temerkhanov3ed2ece2015-10-14 09:55:52 -070084int dram_init(void)
85{
86 ssize_t node_count = atf_node_count();
87 ssize_t dram_size;
88 int node;
89
90 printf("Initializing\nNodes in system: %zd\n", node_count);
91
92 gd->ram_size = 0;
93
94 for (node = 0; node < node_count; node++) {
95 dram_size = atf_dram_size(node);
96 printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
97 gd->ram_size += dram_size;
98 }
99
100 gd->ram_size -= MEM_BASE;
101
102 *(unsigned long *)CPU_RELEASE_ADDR = 0;
103
104 puts("DRAM size:");
105
106 return 0;
107}
108
Sergey Temerkhanov746f9852015-10-14 09:55:50 -0700109/*
110 * Board specific reset that is system reset.
111 */
112void reset_cpu(ulong addr)
113{
114}
115
116/*
117 * Board specific ethernet initialization routine.
118 */
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900119int board_eth_init(struct bd_info *bis)
Sergey Temerkhanov746f9852015-10-14 09:55:50 -0700120{
121 int rc = 0;
122
123 return rc;
124}
125
126#ifdef CONFIG_PCI
127void pci_init_board(void)
128{
129 printf("DEBUG: PCI Init TODO *****\n");
130}
131#endif