blob: aec1d80c46d9b200a87907ff0b9067976ea33e76 [file] [log] [blame]
Jagan Teki6901aab2019-01-11 15:41:46 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun9i-a80-ccu.h>
13#include <dt-bindings/reset/sun9i-a80-ccu.h>
14
15static const struct ccu_clk_gate a80_gates[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +000016 [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
17
Jagan Teki6901aab2019-01-11 15:41:46 +053018 [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
19 [CLK_BUS_UART1] = GATE(0x594, BIT(17)),
20 [CLK_BUS_UART2] = GATE(0x594, BIT(18)),
21 [CLK_BUS_UART3] = GATE(0x594, BIT(19)),
22 [CLK_BUS_UART4] = GATE(0x594, BIT(20)),
23 [CLK_BUS_UART5] = GATE(0x594, BIT(21)),
24};
25
26static const struct ccu_reset a80_resets[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +000027 [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
28
Jagan Teki6901aab2019-01-11 15:41:46 +053029 [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
30 [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
31 [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
32 [RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
33 [RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
34 [RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
35};
36
Andre Przywarae0c7ce72019-01-29 15:54:10 +000037static const struct ccu_clk_gate a80_mmc_gates[] = {
38 [0] = GATE(0x0, BIT(16)),
39 [1] = GATE(0x4, BIT(16)),
40 [2] = GATE(0x8, BIT(16)),
41 [3] = GATE(0xc, BIT(16)),
42};
43
44static const struct ccu_reset a80_mmc_resets[] = {
45 [0] = GATE(0x0, BIT(18)),
46 [1] = GATE(0x4, BIT(18)),
47 [2] = GATE(0x8, BIT(18)),
48 [3] = GATE(0xc, BIT(18)),
49};
50
Jagan Teki6901aab2019-01-11 15:41:46 +053051static const struct ccu_desc a80_ccu_desc = {
52 .gates = a80_gates,
53 .resets = a80_resets,
54};
55
Andre Przywarae0c7ce72019-01-29 15:54:10 +000056static const struct ccu_desc a80_mmc_clk_desc = {
57 .gates = a80_mmc_gates,
58 .resets = a80_mmc_resets,
59};
60
Jagan Teki6901aab2019-01-11 15:41:46 +053061static int a80_clk_bind(struct udevice *dev)
62{
Andre Przywarae0c7ce72019-01-29 15:54:10 +000063 ulong count = ARRAY_SIZE(a80_resets);
64
65 if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk"))
66 count = ARRAY_SIZE(a80_mmc_resets);
67
68 return sunxi_reset_bind(dev, count);
Jagan Teki6901aab2019-01-11 15:41:46 +053069}
70
71static const struct udevice_id a80_ccu_ids[] = {
72 { .compatible = "allwinner,sun9i-a80-ccu",
73 .data = (ulong)&a80_ccu_desc },
Andre Przywarae0c7ce72019-01-29 15:54:10 +000074 { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
75 .data = (ulong)&a80_mmc_clk_desc },
Jagan Teki6901aab2019-01-11 15:41:46 +053076 { }
77};
78
79U_BOOT_DRIVER(clk_sun9i_a80) = {
80 .name = "sun9i_a80_ccu",
81 .id = UCLASS_CLK,
82 .of_match = a80_ccu_ids,
83 .priv_auto_alloc_size = sizeof(struct ccu_priv),
84 .ops = &sunxi_clk_ops,
85 .probe = sunxi_clk_probe,
86 .bind = a80_clk_bind,
87};