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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002/*
York Sunc0c32af2018-01-29 09:44:35 -08003 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
Kumar Gala58e5e9a2008-08-26 15:01:29 -05005 */
6
7#ifndef FSL_DDR_MEMCTL_H
8#define FSL_DDR_MEMCTL_H
9
10/*
11 * Pick a basic DDR Technology.
12 */
13#include <ddr_spd.h>
York Sun34e026f2014-03-27 17:54:47 -070014#include <fsl_ddrc_version.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050015
York Sun34e026f2014-03-27 17:54:47 -070016#define SDRAM_TYPE_DDR1 2
17#define SDRAM_TYPE_DDR2 3
18#define SDRAM_TYPE_LPDDR1 6
19#define SDRAM_TYPE_DDR3 7
20#define SDRAM_TYPE_DDR4 5
Kumar Gala58e5e9a2008-08-26 15:01:29 -050021
Dave Liuc360cea2009-03-14 12:48:30 +080022#define DDR_BL4 4 /* burst length 4 */
23#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
24#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
25#define DDR_BL8 8 /* burst length 8 */
26
York Sune1fd16b2011-01-10 12:03:00 +000027#define DDR3_RTT_OFF 0
Dave Liuf8d05e52010-03-05 12:23:00 +080028#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
29#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
30#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
31#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
32#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
33
York Sun19601dd2015-11-04 10:03:17 -080034#define DDR4_RTT_OFF 0
35#define DDR4_RTT_60_OHM 1 /* RZQ/4 */
36#define DDR4_RTT_120_OHM 2 /* RZQ/2 */
37#define DDR4_RTT_40_OHM 3 /* RZQ/6 */
38#define DDR4_RTT_240_OHM 4 /* RZQ/1 */
39#define DDR4_RTT_48_OHM 5 /* RZQ/5 */
40#define DDR4_RTT_80_OHM 6 /* RZQ/3 */
41#define DDR4_RTT_34_OHM 7 /* RZQ/7 */
42
York Sun4e573822011-08-26 11:32:43 -070043#define DDR2_RTT_OFF 0
44#define DDR2_RTT_75_OHM 1
45#define DDR2_RTT_150_OHM 2
46#define DDR2_RTT_50_OHM 3
47
York Sun5614e712013-09-30 09:22:09 -070048#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050049#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
50typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
51#ifndef CONFIG_FSL_SDRAM_TYPE
52#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
53#endif
York Sun5614e712013-09-30 09:22:09 -070054#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050055#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
56typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
57#ifndef CONFIG_FSL_SDRAM_TYPE
58#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
59#endif
York Sun5614e712013-09-30 09:22:09 -070060#elif defined(CONFIG_SYS_FSL_DDR3)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050061typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
Dave Liu22ff3d02008-11-21 16:31:29 +080062#ifndef CONFIG_FSL_SDRAM_TYPE
63#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
Kumar Gala58e5e9a2008-08-26 15:01:29 -050064#endif
York Sun34e026f2014-03-27 17:54:47 -070065#elif defined(CONFIG_SYS_FSL_DDR4)
66#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
67typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
68#ifndef CONFIG_FSL_SDRAM_TYPE
69#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
70#endif
York Sun5614e712013-09-30 09:22:09 -070071#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
Kumar Gala58e5e9a2008-08-26 15:01:29 -050072
York Sune1fd16b2011-01-10 12:03:00 +000073#define FSL_DDR_ODT_NEVER 0x0
74#define FSL_DDR_ODT_CS 0x1
75#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
76#define FSL_DDR_ODT_OTHER_DIMM 0x3
77#define FSL_DDR_ODT_ALL 0x4
78#define FSL_DDR_ODT_SAME_DIMM 0x5
79#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
80#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
81
Haiying Wangdbbbb3a2008-10-03 12:36:39 -040082/* define bank(chip select) interleaving mode */
83#define FSL_DDR_CS0_CS1 0x40
84#define FSL_DDR_CS2_CS3 0x20
85#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
86#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
87
88/* define memory controller interleaving mode */
89#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
90#define FSL_DDR_PAGE_INTERLEAVING 0x1
91#define FSL_DDR_BANK_INTERLEAVING 0x2
92#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
York Sun6b1e1252014-02-10 13:59:44 -080093#define FSL_DDR_256B_INTERLEAVING 0x8
York Suna4c66502012-08-17 08:22:39 +000094#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
95#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
96#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
97/* placeholder for 4-way interleaving */
98#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
99#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
100#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
Haiying Wangdbbbb3a2008-10-03 12:36:39 -0400101
York Sun123922b2012-10-08 07:44:23 +0000102#define SDRAM_CS_CONFIG_EN 0x80000000
103
Poonam_Aggrwal-b10812e1be0d22009-01-04 08:46:38 +0530104/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
105 */
106#define SDRAM_CFG_MEM_EN 0x80000000
107#define SDRAM_CFG_SREN 0x40000000
108#define SDRAM_CFG_ECC_EN 0x20000000
109#define SDRAM_CFG_RD_EN 0x10000000
110#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
111#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
112#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
113#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
114#define SDRAM_CFG_DYN_PWR 0x00200000
Matthew McClintock9c6b47d2012-08-13 08:10:37 +0000115#define SDRAM_CFG_DBW_MASK 0x00180000
York Sunf31cfd12012-10-08 07:44:24 +0000116#define SDRAM_CFG_DBW_SHIFT 19
Poonam_Aggrwal-b10812e1be0d22009-01-04 08:46:38 +0530117#define SDRAM_CFG_32_BE 0x00080000
Poonam Aggrwal0b3b1762011-02-07 15:09:51 +0530118#define SDRAM_CFG_16_BE 0x00100000
Poonam_Aggrwal-b10812e1be0d22009-01-04 08:46:38 +0530119#define SDRAM_CFG_8_BE 0x00040000
120#define SDRAM_CFG_NCAP 0x00020000
121#define SDRAM_CFG_2T_EN 0x00008000
122#define SDRAM_CFG_BI 0x00000001
123
Tang Yuantiana7787b72014-11-21 11:17:15 +0800124#define SDRAM_CFG2_FRC_SR 0x80000000
York Sun91671912011-01-25 22:05:49 -0800125#define SDRAM_CFG2_D_INIT 0x00000010
Shengzhou Liueb118802016-03-10 17:36:56 +0800126#define SDRAM_CFG2_AP_EN 0x00000020
York Sun91671912011-01-25 22:05:49 -0800127#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
York Suncae7c1b2011-08-26 11:32:40 -0700128#define SDRAM_CFG2_ODT_NEVER 0
129#define SDRAM_CFG2_ODT_ONLY_WRITE 1
130#define SDRAM_CFG2_ODT_ONLY_READ 2
131#define SDRAM_CFG2_ODT_ALWAYS 3
York Sun91671912011-01-25 22:05:49 -0800132
Shengzhou Liua994b3d2015-12-16 16:45:41 +0800133#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
York Sun91671912011-01-25 22:05:49 -0800134#define TIMING_CFG_2_CPO_MASK 0x0F800000
135
York Sun34e026f2014-03-27 17:54:47 -0700136#if defined(CONFIG_SYS_FSL_DDR_VER) && \
137 (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
Dave Liuc360cea2009-03-14 12:48:30 +0800138#define RD_TO_PRE_MASK 0xf
139#define RD_TO_PRE_SHIFT 13
140#define WR_DATA_DELAY_MASK 0xf
141#define WR_DATA_DELAY_SHIFT 9
142#else
143#define RD_TO_PRE_MASK 0x7
144#define RD_TO_PRE_SHIFT 13
145#define WR_DATA_DELAY_MASK 0x7
146#define WR_DATA_DELAY_SHIFT 10
147#endif
148
Shengzhou Liu074596c2016-04-07 16:22:21 +0800149/* DDR_EOR register */
150#define DDR_EOR_RD_REOD_DIS 0x07000000
151#define DDR_EOR_WD_REOD_DIS 0x00100000
152
York Sunfa8d23c2011-01-10 12:03:01 +0000153/* DDR_MD_CNTL */
154#define MD_CNTL_MD_EN 0x80000000
155#define MD_CNTL_CS_SEL_CS0 0x00000000
156#define MD_CNTL_CS_SEL_CS1 0x10000000
157#define MD_CNTL_CS_SEL_CS2 0x20000000
158#define MD_CNTL_CS_SEL_CS3 0x30000000
159#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
160#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
161#define MD_CNTL_MD_SEL_MR 0x00000000
162#define MD_CNTL_MD_SEL_EMR 0x01000000
163#define MD_CNTL_MD_SEL_EMR2 0x02000000
164#define MD_CNTL_MD_SEL_EMR3 0x03000000
165#define MD_CNTL_SET_REF 0x00800000
166#define MD_CNTL_SET_PRE 0x00400000
167#define MD_CNTL_CKE_CNTL_LOW 0x00100000
168#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
169#define MD_CNTL_WRCW 0x00080000
170#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
York Sun9f9f0092015-03-19 09:30:29 -0700171#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
172#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
York Sunfa8d23c2011-01-10 12:03:01 +0000173
York Sun6b06d7d2011-01-10 12:03:02 +0000174/* DDR_CDR1 */
175#define DDR_CDR1_DHC_EN 0x80000000
Hou Zhiqiang031acdb2016-12-09 16:09:00 +0800176#define DDR_CDR1_V0PT9_EN 0x40000000
York Sun57495e42012-10-08 07:44:22 +0000177#define DDR_CDR1_ODT_SHIFT 17
178#define DDR_CDR1_ODT_MASK 0x6
179#define DDR_CDR2_ODT_MASK 0x1
180#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
181#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
York Sun34e026f2014-03-27 17:54:47 -0700182#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
Tang Yuantiana7787b72014-11-21 11:17:15 +0800183#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
York Sun7288c2c2015-03-20 19:28:23 -0700184#define DDR_CDR2_VREF_RANGE_2 0x00000040
York Sun57495e42012-10-08 07:44:22 +0000185
Shengzhou Liueb118802016-03-10 17:36:56 +0800186/* DDR ERR_DISABLE */
187#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
188
189/* Mode Registers */
190#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
191#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
192
Shengzhou Liu5fc62fe2016-03-16 13:50:23 +0800193/* DEBUG_26 register */
194#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
195#define DDR_CAS_TO_PRE_SUB_SHIFT 12
196
Shengzhou Liu4a684892016-03-16 13:50:22 +0800197/* DEBUG_29 register */
198#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
199
Shengzhou Liueb118802016-03-10 17:36:56 +0800200
York Sun57495e42012-10-08 07:44:22 +0000201#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
202 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
York Sun34e026f2014-03-27 17:54:47 -0700203#ifdef CONFIG_SYS_FSL_DDR3L
204#define DDR_CDR_ODT_OFF 0x0
205#define DDR_CDR_ODT_120ohm 0x1
206#define DDR_CDR_ODT_200ohm 0x2
207#define DDR_CDR_ODT_75ohm 0x3
208#define DDR_CDR_ODT_60ohm 0x5
209#define DDR_CDR_ODT_46ohm 0x7
210#elif defined(CONFIG_SYS_FSL_DDR4)
211#define DDR_CDR_ODT_OFF 0x0
212#define DDR_CDR_ODT_100ohm 0x1
213#define DDR_CDR_ODT_120OHM 0x2
214#define DDR_CDR_ODT_80ohm 0x3
215#define DDR_CDR_ODT_60ohm 0x4
216#define DDR_CDR_ODT_40ohm 0x5
217#define DDR_CDR_ODT_50ohm 0x6
218#define DDR_CDR_ODT_30ohm 0x7
219#else
York Sun57495e42012-10-08 07:44:22 +0000220#define DDR_CDR_ODT_OFF 0x0
221#define DDR_CDR_ODT_120ohm 0x1
222#define DDR_CDR_ODT_180ohm 0x2
223#define DDR_CDR_ODT_75ohm 0x3
224#define DDR_CDR_ODT_110ohm 0x4
225#define DDR_CDR_ODT_60hm 0x5
226#define DDR_CDR_ODT_70ohm 0x6
227#define DDR_CDR_ODT_47ohm 0x7
York Sun34e026f2014-03-27 17:54:47 -0700228#endif /* DDR3L */
York Sun57495e42012-10-08 07:44:22 +0000229#else
230#define DDR_CDR_ODT_75ohm 0x0
231#define DDR_CDR_ODT_55ohm 0x1
232#define DDR_CDR_ODT_60ohm 0x2
233#define DDR_CDR_ODT_50ohm 0x3
234#define DDR_CDR_ODT_150ohm 0x4
235#define DDR_CDR_ODT_43ohm 0x5
236#define DDR_CDR_ODT_120ohm 0x6
237#endif
York Sun6b06d7d2011-01-10 12:03:02 +0000238
Tang Yuantiana7787b72014-11-21 11:17:15 +0800239#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
240
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500241/* Record of register values computed */
242typedef struct fsl_ddr_cfg_regs_s {
243 struct {
244 unsigned int bnds;
245 unsigned int config;
246 unsigned int config_2;
247 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
248 unsigned int timing_cfg_3;
249 unsigned int timing_cfg_0;
250 unsigned int timing_cfg_1;
251 unsigned int timing_cfg_2;
252 unsigned int ddr_sdram_cfg;
253 unsigned int ddr_sdram_cfg_2;
York Sun34e026f2014-03-27 17:54:47 -0700254 unsigned int ddr_sdram_cfg_3;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500255 unsigned int ddr_sdram_mode;
256 unsigned int ddr_sdram_mode_2;
York Sune1fd16b2011-01-10 12:03:00 +0000257 unsigned int ddr_sdram_mode_3;
258 unsigned int ddr_sdram_mode_4;
259 unsigned int ddr_sdram_mode_5;
260 unsigned int ddr_sdram_mode_6;
261 unsigned int ddr_sdram_mode_7;
262 unsigned int ddr_sdram_mode_8;
York Sun34e026f2014-03-27 17:54:47 -0700263 unsigned int ddr_sdram_mode_9;
264 unsigned int ddr_sdram_mode_10;
265 unsigned int ddr_sdram_mode_11;
266 unsigned int ddr_sdram_mode_12;
267 unsigned int ddr_sdram_mode_13;
268 unsigned int ddr_sdram_mode_14;
269 unsigned int ddr_sdram_mode_15;
270 unsigned int ddr_sdram_mode_16;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500271 unsigned int ddr_sdram_md_cntl;
272 unsigned int ddr_sdram_interval;
273 unsigned int ddr_data_init;
274 unsigned int ddr_sdram_clk_cntl;
275 unsigned int ddr_init_addr;
276 unsigned int ddr_init_ext_addr;
277 unsigned int timing_cfg_4;
278 unsigned int timing_cfg_5;
York Sun34e026f2014-03-27 17:54:47 -0700279 unsigned int timing_cfg_6;
280 unsigned int timing_cfg_7;
281 unsigned int timing_cfg_8;
282 unsigned int timing_cfg_9;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500283 unsigned int ddr_zq_cntl;
284 unsigned int ddr_wrlvl_cntl;
York Sun57495e42012-10-08 07:44:22 +0000285 unsigned int ddr_wrlvl_cntl_2;
286 unsigned int ddr_wrlvl_cntl_3;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500287 unsigned int ddr_sr_cntr;
288 unsigned int ddr_sdram_rcw_1;
289 unsigned int ddr_sdram_rcw_2;
York Sun34e026f2014-03-27 17:54:47 -0700290 unsigned int ddr_sdram_rcw_3;
291 unsigned int ddr_sdram_rcw_4;
292 unsigned int ddr_sdram_rcw_5;
293 unsigned int ddr_sdram_rcw_6;
294 unsigned int dq_map_0;
295 unsigned int dq_map_1;
296 unsigned int dq_map_2;
297 unsigned int dq_map_3;
york7fd101c2010-07-02 22:25:54 +0000298 unsigned int ddr_eor;
York Sund2a95682011-01-10 12:02:59 +0000299 unsigned int ddr_cdr1;
300 unsigned int ddr_cdr2;
301 unsigned int err_disable;
302 unsigned int err_int_en;
York Sunb4067312016-08-29 17:04:12 +0800303 unsigned int debug[64];
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500304} fsl_ddr_cfg_regs_t;
305
306typedef struct memctl_options_partial_s {
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530307 unsigned int all_dimms_ecc_capable;
308 unsigned int all_dimms_tckmax_ps;
309 unsigned int all_dimms_burst_lengths_bitmask;
310 unsigned int all_dimms_registered;
311 unsigned int all_dimms_unbuffered;
York Sun34e026f2014-03-27 17:54:47 -0700312 /* unsigned int lowest_common_spd_caslat; */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530313 unsigned int all_dimms_minimum_trcd_ps;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500314} memctl_options_partial_t;
315
York Sun51d498f2011-05-27 07:25:51 +0800316#define DDR_DATA_BUS_WIDTH_64 0
317#define DDR_DATA_BUS_WIDTH_32 1
318#define DDR_DATA_BUS_WIDTH_16 2
York Sunef87cab2014-09-05 13:52:43 +0800319#define DDR_CSWL_CS0 0x04000001
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500320/*
321 * Generalized parameters for memory controller configuration,
322 * might be a little specific to the FSL memory controller
323 */
324typedef struct memctl_options_s {
325 /*
326 * Memory organization parameters
327 *
328 * if DIMM is present in the system
329 * where DIMMs are with respect to chip select
330 * where chip selects are with respect to memory boundaries
331 */
332 unsigned int registered_dimm_en; /* use registered DIMM support */
333
334 /* Options local to a Chip Select */
335 struct cs_local_opts_s {
336 unsigned int auto_precharge;
337 unsigned int odt_rd_cfg;
338 unsigned int odt_wr_cfg;
York Sune1fd16b2011-01-10 12:03:00 +0000339 unsigned int odt_rtt_norm;
340 unsigned int odt_rtt_wr;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500341 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
342
343 /* Special configurations for chip select */
344 unsigned int memctl_interleaving;
345 unsigned int memctl_interleaving_mode;
346 unsigned int ba_intlv_ctl;
york7fd101c2010-07-02 22:25:54 +0000347 unsigned int addr_hash;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500348
349 /* Operational mode parameters */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530350 unsigned int ecc_mode; /* Use ECC? */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500351 /* Initialize ECC using memory controller? */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530352 unsigned int ecc_init_using_memctl;
353 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500354 /* SREN - self-refresh during sleep */
355 unsigned int self_refresh_in_sleep;
Joakim Tjernlunde368c202015-10-14 16:32:00 +0200356 /* SR_IE - Self-refresh interrupt enable */
357 unsigned int self_refresh_interrupt_en;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500358 unsigned int dynamic_power; /* DYN_PWR */
359 /* memory data width to use (16-bit, 32-bit, 64-bit) */
360 unsigned int data_bus_width;
Dave Liuc360cea2009-03-14 12:48:30 +0800361 unsigned int burst_length; /* BL4, OTF and BL8 */
362 /* On-The-Fly Burst Chop enable */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530363 unsigned int otf_burst_chop_en;
Dave Liuc360cea2009-03-14 12:48:30 +0800364 /* mirrior DIMMs for DDR3 */
365 unsigned int mirrored_dimm;
york5800e7a2010-07-02 22:25:53 +0000366 unsigned int quad_rank_present;
Shengzhou Liueb118802016-03-10 17:36:56 +0800367 unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
York Sunb61e0612013-06-25 11:37:47 -0700368 unsigned int x4_en; /* enable x4 devices */
York Sunc0c32af2018-01-29 09:44:35 -0800369 unsigned int package_3ds;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500370
371 /* Global Timing Parameters */
372 unsigned int cas_latency_override;
373 unsigned int cas_latency_override_value;
374 unsigned int use_derated_caslat;
375 unsigned int additive_latency_override;
376 unsigned int additive_latency_override_value;
377
378 unsigned int clk_adjust; /* */
Shengzhou Liu02fb2762016-11-21 11:36:48 +0800379 unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
380 unsigned int cpo_sample; /* optimize debug_29[24:31] */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500381 unsigned int write_data_delay; /* DQS adjust */
Dave Liubdc9f7b2009-12-16 10:24:37 -0600382
York Sunef87cab2014-09-05 13:52:43 +0800383 unsigned int cswl_override;
Dave Liubdc9f7b2009-12-16 10:24:37 -0600384 unsigned int wrlvl_override;
385 unsigned int wrlvl_sample; /* Write leveling */
386 unsigned int wrlvl_start;
York Sun57495e42012-10-08 07:44:22 +0000387 unsigned int wrlvl_ctl_2;
388 unsigned int wrlvl_ctl_3;
Dave Liubdc9f7b2009-12-16 10:24:37 -0600389
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500390 unsigned int half_strength_driver_enable;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530391 unsigned int twot_en;
392 unsigned int threet_en;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500393 unsigned int bstopre;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530394 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
Dave Liu22cca7e2008-11-21 16:31:35 +0800395
Dave Liuc360cea2009-03-14 12:48:30 +0800396 /* Rtt impedance */
397 unsigned int rtt_override; /* rtt_override enable */
398 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
Dave Liu1aa3d082009-12-16 10:24:38 -0600399 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
Dave Liuc360cea2009-03-14 12:48:30 +0800400
Dave Liu22cca7e2008-11-21 16:31:35 +0800401 /* Automatic self refresh */
402 unsigned int auto_self_refresh_en;
403 unsigned int sr_it;
Dave Liuc360cea2009-03-14 12:48:30 +0800404 /* ZQ calibration */
405 unsigned int zq_en;
406 /* Write leveling */
407 unsigned int wrlvl_en;
York Sund2a95682011-01-10 12:02:59 +0000408 /* RCW override for RDIMM */
409 unsigned int rcw_override;
410 unsigned int rcw_1;
411 unsigned int rcw_2;
York Sun426230a2018-01-29 09:44:33 -0800412 unsigned int rcw_3;
York Sund2a95682011-01-10 12:02:59 +0000413 /* control register 1 */
414 unsigned int ddr_cdr1;
York Sun57495e42012-10-08 07:44:22 +0000415 unsigned int ddr_cdr2;
York Sun23f96702011-05-27 13:44:28 +0800416
417 unsigned int trwt_override;
418 unsigned int trwt; /* read-to-write turnaround */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500419} memctl_options_t;
420
York Sun1d71efb2014-08-01 15:51:00 -0700421phys_size_t fsl_ddr_sdram(void);
422phys_size_t fsl_ddr_sdram_size(void);
423phys_size_t fsl_other_ddr_sdram(unsigned long long base,
424 unsigned int first_ctrl,
425 unsigned int num_ctrls,
426 unsigned int dimm_slots_per_ctrl,
427 int (*board_need_reset)(void),
428 void (*board_reset)(void),
429 void (*board_de_reset)(void));
Kumar Gala3dbd5d72011-01-09 14:06:28 -0600430extern int fsl_use_spd(void);
York Sun1d71efb2014-08-01 15:51:00 -0700431void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
432 unsigned int ctrl_num, int step);
York Sunf31cfd12012-10-08 07:44:24 +0000433u32 fsl_ddr_get_intl3r(void);
York Sun1d71efb2014-08-01 15:51:00 -0700434void print_ddr_info(unsigned int start_ctrl);
York Sun28a96672010-10-18 13:46:49 -0700435
York Sunc63e1372013-06-25 11:37:48 -0700436static void __board_assert_mem_reset(void)
437{
438}
439
440static void __board_deassert_mem_reset(void)
441{
442}
443
444void board_assert_mem_reset(void)
445 __attribute__((weak, alias("__board_assert_mem_reset")));
446
447void board_deassert_mem_reset(void)
448 __attribute__((weak, alias("__board_deassert_mem_reset")));
449
450static int __board_need_mem_reset(void)
451{
452 return 0;
453}
454
455int board_need_mem_reset(void)
456 __attribute__((weak, alias("__board_need_mem_reset")));
457
Tang Yuantiana7787b72014-11-21 11:17:15 +0800458#if defined(CONFIG_DEEP_SLEEP)
459void board_mem_sleep_setup(void);
460bool is_warm_boot(void);
461int fsl_dp_resume(void);
462#endif
Tang Yuantianaade2002014-04-17 15:33:46 +0800463
Becky Bruce38dba0c2010-12-17 17:17:56 -0600464/*
465 * The 85xx boards have a common prototype for fixed_sdram so put the
466 * declaration here.
467 */
468#ifdef CONFIG_MPC85xx
469extern phys_size_t fixed_sdram(void);
470#endif
471
472#if defined(CONFIG_DDR_ECC)
473extern void ddr_enable_ecc(unsigned int dram_size);
474#endif
475
476
York Sun28a96672010-10-18 13:46:49 -0700477typedef struct fixed_ddr_parm{
478 int min_freq;
479 int max_freq;
480 fsl_ddr_cfg_regs_t *ddr_settings;
481} fixed_ddr_parm_t;
Simon Glass3eace372017-04-06 12:47:04 -0600482
483/**
484 * fsl_initdram() - Set up the SDRAM
485 *
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100486 * Return: 0 if OK, -ve on error
Simon Glass3eace372017-04-06 12:47:04 -0600487 */
488int fsl_initdram(void);
489
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500490#endif