blob: 87c1d75f9f3cfb6dc22632f95d9367f29d7ac13f [file] [log] [blame]
Michal Simek1d6c54e2018-04-12 17:39:46 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
4 */
5
6#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07007#include <cpu_func.h>
Simon Glass691d7192020-05-10 11:40:02 -06008#include <init.h>
Michal Simek1d6c54e2018-04-12 17:39:46 +02009#include <asm/armv7_mpu.h>
10
11DECLARE_GLOBAL_DATA_PTR;
12
13struct mpu_region_config region_config[] = {
Michal Simeke3259a72020-09-14 16:33:46 +020014 { 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
15 SHARED_WRITE_BUFFERED, REGION_4GB },
16 { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
Michal Simek1d6c54e2018-04-12 17:39:46 +020017 O_I_WB_RD_WR_ALLOC, REGION_1GB },
18};
19
20int arch_cpu_init(void)
21{
22 gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
23
Michal Simeke3259a72020-09-14 16:33:46 +020024 setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
Michal Simek1d6c54e2018-04-12 17:39:46 +020025
26 return 0;
27}
28
29/*
30 * Perform the low-level reset.
31 */
32void reset_cpu(ulong addr)
33{
34 while (1)
35 ;
36}