blob: 98c7feb6cfab47218473740956219fd40fd53c40 [file] [log] [blame]
Kever Yangc43acfd2018-12-20 11:33:42 +08001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Kever Yang39648e62017-06-23 16:11:07 +08002/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
Kever Yang39648e62017-06-23 16:11:07 +08004 */
Kever Yang39648e62017-06-23 16:11:07 +08005#include <common.h>
Kever Yang85a38742019-08-02 10:39:59 +03006#include <clk.h>
7#include <debug_uart.h>
Kever Yang39648e62017-06-23 16:11:07 +08008#include <dm.h>
Kever Yang85a38742019-08-02 10:39:59 +03009#include <dt-structs.h>
Simon Glass691d7192020-05-10 11:40:02 -060010#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Kever Yang39648e62017-06-23 16:11:07 +080012#include <ram.h>
Kever Yang85a38742019-08-02 10:39:59 +030013#include <regmap.h>
Kever Yang39648e62017-06-23 16:11:07 +080014#include <syscon.h>
Kever Yang85a38742019-08-02 10:39:59 +030015#include <asm/io.h>
Kever Yang15f09a12019-03-28 11:01:23 +080016#include <asm/arch-rockchip/clock.h>
Kever Yang85a38742019-08-02 10:39:59 +030017#include <asm/arch-rockchip/cru_rk3328.h>
Kever Yang15f09a12019-03-28 11:01:23 +080018#include <asm/arch-rockchip/grf_rk3328.h>
Kever Yang5d19ddf2019-11-15 11:04:33 +080019#include <asm/arch-rockchip/sdram.h>
Kever Yang85a38742019-08-02 10:39:59 +030020#include <asm/arch-rockchip/sdram_rk3328.h>
21#include <asm/arch-rockchip/uart.h>
Simon Glassc05ed002020-05-10 11:40:11 -060022#include <linux/delay.h>
Kever Yang39648e62017-06-23 16:11:07 +080023
Kever Yang39648e62017-06-23 16:11:07 +080024struct dram_info {
Kever Yang85a38742019-08-02 10:39:59 +030025#ifdef CONFIG_TPL_BUILD
YouMin Chenca93e322019-11-15 11:04:44 +080026 struct ddr_pctl_regs *pctl;
27 struct ddr_phy_regs *phy;
Kever Yang85a38742019-08-02 10:39:59 +030028 struct clk ddr_clk;
29 struct rk3328_cru *cru;
YouMin Chenca93e322019-11-15 11:04:44 +080030 struct msch_regs *msch;
Kever Yang85a38742019-08-02 10:39:59 +030031 struct rk3328_ddr_grf_regs *ddr_grf;
32#endif
Kever Yang39648e62017-06-23 16:11:07 +080033 struct ram_info info;
34 struct rk3328_grf_regs *grf;
35};
36
Kever Yang85a38742019-08-02 10:39:59 +030037#ifdef CONFIG_TPL_BUILD
38
39struct rk3328_sdram_channel sdram_ch;
40
41struct rockchip_dmc_plat {
42#if CONFIG_IS_ENABLED(OF_PLATDATA)
43 struct dtd_rockchip_rk3328_dmc dtplat;
44#else
45 struct rk3328_sdram_params sdram_params;
46#endif
47 struct regmap *map;
48};
49
50#if CONFIG_IS_ENABLED(OF_PLATDATA)
51static int conv_of_platdata(struct udevice *dev)
52{
53 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
54 struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
55 int ret;
56
57 ret = regmap_init_mem_platdata(dev, dtplat->reg,
58 ARRAY_SIZE(dtplat->reg) / 2,
59 &plat->map);
60 if (ret)
61 return ret;
62
63 return 0;
64}
65#endif
66
67static void rkclk_ddr_reset(struct dram_info *dram,
68 u32 ctl_srstn, u32 ctl_psrstn,
69 u32 phy_srstn, u32 phy_psrstn)
70{
71 writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) |
72 ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
73 &dram->cru->softrst_con[5]);
74 writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
75}
76
YouMin Chenca93e322019-11-15 11:04:44 +080077static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)
Kever Yang85a38742019-08-02 10:39:59 +030078{
79 unsigned int refdiv, postdiv1, postdiv2, fbdiv;
80 int delay = 1000;
YouMin Chenca93e322019-11-15 11:04:44 +080081 u32 mhz = hz / MHZ;
Kever Yang85a38742019-08-02 10:39:59 +030082
83 refdiv = 1;
84 if (mhz <= 300) {
85 postdiv1 = 4;
86 postdiv2 = 2;
87 } else if (mhz <= 400) {
88 postdiv1 = 6;
89 postdiv2 = 1;
90 } else if (mhz <= 600) {
91 postdiv1 = 4;
92 postdiv2 = 1;
93 } else if (mhz <= 800) {
94 postdiv1 = 3;
95 postdiv2 = 1;
96 } else if (mhz <= 1600) {
97 postdiv1 = 2;
98 postdiv2 = 1;
99 } else {
100 postdiv1 = 1;
101 postdiv2 = 1;
102 }
103 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
104
105 writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con);
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]);
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
108 &dram->cru->dpll_con[1]);
109
110 while (delay > 0) {
111 udelay(1);
112 if (LOCK(readl(&dram->cru->dpll_con[1])))
113 break;
114 delay--;
115 }
116
117 writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con);
118}
119
120static void rkclk_configure_ddr(struct dram_info *dram,
121 struct rk3328_sdram_params *sdram_params)
122{
123 void __iomem *phy_base = dram->phy;
124
125 /* choose DPLL for ddr clk source */
126 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
127
128 /* for inno ddr phy need 2*freq */
YouMin Chenca93e322019-11-15 11:04:44 +0800129 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2);
Kever Yang85a38742019-08-02 10:39:59 +0300130}
131
132/* return ddrconfig value
133 * (-1), find ddrconfig fail
134 * other, the ddrconfig value
135 * only support cs0_row >= cs1_row
136 */
YouMin Chenca93e322019-11-15 11:04:44 +0800137static u32 calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
Kever Yang85a38742019-08-02 10:39:59 +0300138{
YouMin Chenca93e322019-11-15 11:04:44 +0800139 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
Kever Yang85a38742019-08-02 10:39:59 +0300140 u32 cs, bw, die_bw, col, row, bank;
YouMin Chenca93e322019-11-15 11:04:44 +0800141 u32 cs1_row;
Kever Yang85a38742019-08-02 10:39:59 +0300142 u32 i, tmp;
143 u32 ddrconf = -1;
144
YouMin Chenca93e322019-11-15 11:04:44 +0800145 cs = cap_info->rank;
146 bw = cap_info->bw;
147 die_bw = cap_info->dbw;
148 col = cap_info->col;
149 row = cap_info->cs0_row;
150 cs1_row = cap_info->cs1_row;
151 bank = cap_info->bk;
Kever Yang85a38742019-08-02 10:39:59 +0300152
YouMin Chenca93e322019-11-15 11:04:44 +0800153 if (sdram_params->base.dramtype == DDR4) {
154 /* when DDR_TEST, CS always at MSB position for easy test */
155 if (cs == 2 && row == cs1_row) {
156 /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
157 tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) |
158 die_bw;
159 for (i = 17; i < 21; i++) {
160 if (((tmp & 0x7) ==
161 (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
162 ((tmp & 0x3c) <=
163 (ddr4_cfg_2_rbc[i - 10] & 0x3c))) {
164 ddrconf = i;
165 goto out;
166 }
167 }
168 }
169
Kever Yang85a38742019-08-02 10:39:59 +0300170 tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
171 for (i = 10; i < 17; i++) {
172 if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
173 ((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) &&
174 ((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) {
175 ddrconf = i;
176 goto out;
177 }
178 }
179 } else {
180 if (bank == 2) {
181 ddrconf = 8;
182 goto out;
183 }
184
YouMin Chenca93e322019-11-15 11:04:44 +0800185 /* when DDR_TEST, CS always at MSB position for easy test */
186 if (cs == 2 && row == cs1_row) {
187 /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
188 for (i = 5; i < 8; i++) {
189 if ((bw + col - 11) == (ddr_cfg_2_rbc[i] &
190 0x3)) {
191 ddrconf = i;
192 goto out;
193 }
194 }
195 }
196
Kever Yang85a38742019-08-02 10:39:59 +0300197 tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
198 for (i = 0; i < 5; i++)
199 if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
200 ((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) {
201 ddrconf = i;
202 goto out;
203 }
204 }
205
206out:
207 if (ddrconf > 20)
YouMin Chenca93e322019-11-15 11:04:44 +0800208 printf("calculate ddrconfig error\n");
Kever Yang85a38742019-08-02 10:39:59 +0300209
210 return ddrconf;
211}
212
Kever Yang85a38742019-08-02 10:39:59 +0300213/*******
214 * calculate controller dram address map, and setting to register.
215 * argument sdram_ch.ddrconf must be right value before
216 * call this function.
217 *******/
218static void set_ctl_address_map(struct dram_info *dram,
219 struct rk3328_sdram_params *sdram_params)
220{
YouMin Chenca93e322019-11-15 11:04:44 +0800221 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
Kever Yang85a38742019-08-02 10:39:59 +0300222 void __iomem *pctl_base = dram->pctl;
223
YouMin Chenca93e322019-11-15 11:04:44 +0800224 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
225 &addrmap[cap_info->ddrconfig][0], 9 * 4);
226 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4)
Kever Yang85a38742019-08-02 10:39:59 +0300227 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
YouMin Chenca93e322019-11-15 11:04:44 +0800228 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)
Kever Yang85a38742019-08-02 10:39:59 +0300229 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
230
YouMin Chenca93e322019-11-15 11:04:44 +0800231 if (cap_info->rank == 1)
Kever Yang85a38742019-08-02 10:39:59 +0300232 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
233}
234
Kever Yang85a38742019-08-02 10:39:59 +0300235static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
236{
Kever Yang85a38742019-08-02 10:39:59 +0300237 void __iomem *pctl_base = dram->pctl;
YouMin Chenca93e322019-11-15 11:04:44 +0800238 u32 dis_auto_zq = 0;
239 u32 pwrctl;
240 u32 ret;
Kever Yang85a38742019-08-02 10:39:59 +0300241
YouMin Chenca93e322019-11-15 11:04:44 +0800242 /* disable auto low-power */
243 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
244 writel(0, pctl_base + DDR_PCTL2_PWRCTL);
Kever Yang85a38742019-08-02 10:39:59 +0300245
YouMin Chenca93e322019-11-15 11:04:44 +0800246 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);
Kever Yang85a38742019-08-02 10:39:59 +0300247
YouMin Chenca93e322019-11-15 11:04:44 +0800248 ret = phy_data_training(dram->phy, cs, dramtype);
Kever Yang85a38742019-08-02 10:39:59 +0300249
YouMin Chenca93e322019-11-15 11:04:44 +0800250 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
251
252 /* restore auto low-power */
253 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
254
Kever Yang85a38742019-08-02 10:39:59 +0300255 return ret;
256}
257
Kever Yang85a38742019-08-02 10:39:59 +0300258static void rx_deskew_switch_adjust(struct dram_info *dram)
259{
260 u32 i, deskew_val;
261 u32 gate_val = 0;
262 void __iomem *phy_base = dram->phy;
263
264 for (i = 0; i < 4; i++)
YouMin Chenca93e322019-11-15 11:04:44 +0800265 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
Kever Yang85a38742019-08-02 10:39:59 +0300266
267 deskew_val = (gate_val >> 3) + 1;
268 deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
269 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2);
270 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4,
271 (deskew_val & 0x1c) << 2);
272}
273
Kever Yang85a38742019-08-02 10:39:59 +0300274static void tx_deskew_switch_adjust(struct dram_info *dram)
275{
276 void __iomem *phy_base = dram->phy;
277
278 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1);
279}
280
281static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
282{
283 writel(ddrconfig, &dram->msch->ddrconf);
284}
285
YouMin Chenca93e322019-11-15 11:04:44 +0800286static void sdram_msch_config(struct msch_regs *msch,
287 struct sdram_msch_timings *noc_timings)
288{
289 writel(noc_timings->ddrtiming.d32, &msch->ddrtiming);
290
291 writel(noc_timings->ddrmode.d32, &msch->ddrmode);
292 writel(noc_timings->readlatency, &msch->readlatency);
293
294 writel(noc_timings->activate.d32, &msch->activate);
295 writel(noc_timings->devtodev.d32, &msch->devtodev);
296 writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing);
297 writel(noc_timings->agingx0, &msch->aging0);
298 writel(noc_timings->agingx0, &msch->aging1);
299 writel(noc_timings->agingx0, &msch->aging2);
300 writel(noc_timings->agingx0, &msch->aging3);
301 writel(noc_timings->agingx0, &msch->aging4);
302 writel(noc_timings->agingx0, &msch->aging5);
303}
304
Kever Yang85a38742019-08-02 10:39:59 +0300305static void dram_all_config(struct dram_info *dram,
306 struct rk3328_sdram_params *sdram_params)
307{
YouMin Chenca93e322019-11-15 11:04:44 +0800308 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
309 u32 sys_reg2 = 0;
310 u32 sys_reg3 = 0;
Kever Yang85a38742019-08-02 10:39:59 +0300311
YouMin Chenca93e322019-11-15 11:04:44 +0800312 set_ddrconfig(dram, cap_info->ddrconfig);
313 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,
314 &sys_reg3, 0);
315 writel(sys_reg2, &dram->grf->os_reg[2]);
316 writel(sys_reg3, &dram->grf->os_reg[3]);
Kever Yang85a38742019-08-02 10:39:59 +0300317
YouMin Chenca93e322019-11-15 11:04:44 +0800318 sdram_msch_config(dram->msch, &sdram_ch.noc_timings);
Kever Yang85a38742019-08-02 10:39:59 +0300319}
320
321static void enable_low_power(struct dram_info *dram,
322 struct rk3328_sdram_params *sdram_params)
323{
324 void __iomem *pctl_base = dram->pctl;
325
326 /* enable upctl2 axi clock auto gating */
327 writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]);
328 writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]);
329 /* enable upctl2 core clock auto gating */
330 writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]);
331 /* enable sr, pd */
332 if (PD_IDLE == 0)
333 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
334 else
335 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
336 if (SR_IDLE == 0)
337 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
338 else
339 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
340 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
341}
342
343static int sdram_init(struct dram_info *dram,
344 struct rk3328_sdram_params *sdram_params, u32 pre_init)
345{
YouMin Chenca93e322019-11-15 11:04:44 +0800346 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
Kever Yang85a38742019-08-02 10:39:59 +0300347 void __iomem *pctl_base = dram->pctl;
348
349 rkclk_ddr_reset(dram, 1, 1, 1, 1);
350 udelay(10);
351 /*
352 * dereset ddr phy psrstn to config pll,
353 * if using phy pll psrstn must be dereset
354 * before config pll
355 */
356 rkclk_ddr_reset(dram, 1, 1, 1, 0);
357 rkclk_configure_ddr(dram, sdram_params);
YouMin Chenca93e322019-11-15 11:04:44 +0800358
Kever Yang85a38742019-08-02 10:39:59 +0300359 /* release phy srst to provide clk to ctrl */
360 rkclk_ddr_reset(dram, 1, 1, 0, 0);
361 udelay(10);
YouMin Chenca93e322019-11-15 11:04:44 +0800362 phy_soft_reset(dram->phy);
Kever Yang85a38742019-08-02 10:39:59 +0300363 /* release ctrl presetn, and config ctl registers */
364 rkclk_ddr_reset(dram, 1, 0, 0, 0);
YouMin Chenca93e322019-11-15 11:04:44 +0800365 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);
366 cap_info->ddrconfig = calculate_ddrconfig(sdram_params);
Kever Yang85a38742019-08-02 10:39:59 +0300367 set_ctl_address_map(dram, sdram_params);
YouMin Chenca93e322019-11-15 11:04:44 +0800368 phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew,
369 &sdram_params->base, cap_info->bw);
Kever Yang85a38742019-08-02 10:39:59 +0300370
371 /* enable dfi_init_start to init phy after ctl srstn deassert */
372 setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
373 rkclk_ddr_reset(dram, 0, 0, 0, 0);
374 /* wait for dfi_init_done and dram init complete */
375 while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
376 continue;
377
378 /* do ddr gate training */
YouMin Chenca93e322019-11-15 11:04:44 +0800379 if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {
380 printf("data training error\n");
381 return -1;
382 }
Kever Yang85a38742019-08-02 10:39:59 +0300383
YouMin Chenca93e322019-11-15 11:04:44 +0800384 if (sdram_params->base.dramtype == DDR4)
385 pctl_write_vrefdq(dram->pctl, 0x3, 5670,
386 sdram_params->base.dramtype);
Kever Yang85a38742019-08-02 10:39:59 +0300387
Kever Yang31531f62020-01-07 15:15:20 +0800388 if (pre_init != 0) {
Kever Yang85a38742019-08-02 10:39:59 +0300389 rx_deskew_switch_adjust(dram);
390 tx_deskew_switch_adjust(dram);
391 }
392
393 dram_all_config(dram, sdram_params);
394 enable_low_power(dram, sdram_params);
395
396 return 0;
397}
398
399static u64 dram_detect_cap(struct dram_info *dram,
400 struct rk3328_sdram_params *sdram_params,
401 unsigned char channel)
402{
YouMin Chenca93e322019-11-15 11:04:44 +0800403 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
Kever Yang85a38742019-08-02 10:39:59 +0300404
405 /*
406 * for ddr3: ddrconf = 3
407 * for ddr4: ddrconf = 12
408 * for lpddr3: ddrconf = 3
409 * default bw = 1
410 */
411 u32 bk, bktmp;
412 u32 col, coltmp;
YouMin Chenca93e322019-11-15 11:04:44 +0800413 u32 rowtmp;
Kever Yang85a38742019-08-02 10:39:59 +0300414 u32 cs;
415 u32 bw = 1;
YouMin Chenca93e322019-11-15 11:04:44 +0800416 u32 dram_type = sdram_params->base.dramtype;
Kever Yang85a38742019-08-02 10:39:59 +0300417
418 if (dram_type != DDR4) {
419 /* detect col and bk for ddr3/lpddr3 */
420 coltmp = 12;
421 bktmp = 3;
422 rowtmp = 16;
423
YouMin Chenca93e322019-11-15 11:04:44 +0800424 if (sdram_detect_col(cap_info, coltmp) != 0)
Kever Yang85a38742019-08-02 10:39:59 +0300425 goto cap_err;
YouMin Chenca93e322019-11-15 11:04:44 +0800426 sdram_detect_bank(cap_info, coltmp, bktmp);
427 sdram_detect_dbw(cap_info, dram_type);
Kever Yang85a38742019-08-02 10:39:59 +0300428 } else {
429 /* detect bg for ddr4 */
430 coltmp = 10;
431 bktmp = 4;
432 rowtmp = 17;
433
434 col = 10;
435 bk = 2;
YouMin Chenca93e322019-11-15 11:04:44 +0800436 cap_info->col = col;
437 cap_info->bk = bk;
438 sdram_detect_bg(cap_info, coltmp);
Kever Yang85a38742019-08-02 10:39:59 +0300439 }
YouMin Chenca93e322019-11-15 11:04:44 +0800440
Kever Yang85a38742019-08-02 10:39:59 +0300441 /* detect row */
YouMin Chenca93e322019-11-15 11:04:44 +0800442 if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)
Kever Yang85a38742019-08-02 10:39:59 +0300443 goto cap_err;
YouMin Chenca93e322019-11-15 11:04:44 +0800444
Kever Yang85a38742019-08-02 10:39:59 +0300445 /* detect row_3_4 */
YouMin Chenca93e322019-11-15 11:04:44 +0800446 sdram_detect_row_3_4(cap_info, coltmp, bktmp);
Kever Yang85a38742019-08-02 10:39:59 +0300447
YouMin Chenca93e322019-11-15 11:04:44 +0800448 /* bw and cs detect using data training */
Kever Yang85a38742019-08-02 10:39:59 +0300449 if (data_training(dram, 1, dram_type) == 0)
450 cs = 1;
451 else
452 cs = 0;
YouMin Chenca93e322019-11-15 11:04:44 +0800453 cap_info->rank = cs + 1;
Kever Yang85a38742019-08-02 10:39:59 +0300454
455 bw = 2;
YouMin Chenca93e322019-11-15 11:04:44 +0800456 cap_info->bw = bw;
Kever Yang85a38742019-08-02 10:39:59 +0300457
YouMin Chenca93e322019-11-15 11:04:44 +0800458 cap_info->cs0_high16bit_row = cap_info->cs0_row;
459 if (cs) {
460 cap_info->cs1_row = cap_info->cs0_row;
461 cap_info->cs1_high16bit_row = cap_info->cs0_row;
462 } else {
463 cap_info->cs1_row = 0;
464 cap_info->cs1_high16bit_row = 0;
465 }
Kever Yang85a38742019-08-02 10:39:59 +0300466
YouMin Chenca93e322019-11-15 11:04:44 +0800467 return 0;
Kever Yang85a38742019-08-02 10:39:59 +0300468cap_err:
YouMin Chenca93e322019-11-15 11:04:44 +0800469 return -1;
Kever Yang85a38742019-08-02 10:39:59 +0300470}
471
472static int sdram_init_detect(struct dram_info *dram,
473 struct rk3328_sdram_params *sdram_params)
474{
YouMin Chenca93e322019-11-15 11:04:44 +0800475 u32 sys_reg = 0;
476 u32 sys_reg3 = 0;
477 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
478
Kever Yang85a38742019-08-02 10:39:59 +0300479 debug("Starting SDRAM initialization...\n");
480
481 memcpy(&sdram_ch, &sdram_params->ch,
482 sizeof(struct rk3328_sdram_channel));
483
Kever Yang31531f62020-01-07 15:15:20 +0800484 sdram_init(dram, sdram_params, 0);
Kever Yang85a38742019-08-02 10:39:59 +0300485 dram_detect_cap(dram, sdram_params, 0);
486
487 /* modify bw, cs related timing */
YouMin Chenca93e322019-11-15 11:04:44 +0800488 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,
489 sdram_params->base.dramtype);
490
491 if (cap_info->bw == 2)
492 sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
493 else
494 sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
495
Kever Yang85a38742019-08-02 10:39:59 +0300496 /* reinit sdram by real dram cap */
Kever Yang31531f62020-01-07 15:15:20 +0800497 sdram_init(dram, sdram_params, 1);
Kever Yang85a38742019-08-02 10:39:59 +0300498
499 /* redetect cs1 row */
YouMin Chenca93e322019-11-15 11:04:44 +0800500 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
501 if (cap_info->cs1_row) {
502 sys_reg = readl(&dram->grf->os_reg[2]);
503 sys_reg3 = readl(&dram->grf->os_reg[3]);
504 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,
505 sys_reg, sys_reg3, 0);
506 writel(sys_reg, &dram->grf->os_reg[2]);
507 writel(sys_reg3, &dram->grf->os_reg[3]);
508 }
509
510 sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base);
Kever Yang85a38742019-08-02 10:39:59 +0300511
512 return 0;
513}
514
515static int rk3328_dmc_init(struct udevice *dev)
516{
517 struct dram_info *priv = dev_get_priv(dev);
518 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
519 int ret;
520
521#if !CONFIG_IS_ENABLED(OF_PLATDATA)
522 struct rk3328_sdram_params *params = &plat->sdram_params;
523#else
524 struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
525 struct rk3328_sdram_params *params =
526 (void *)dtplat->rockchip_sdram_params;
527
528 ret = conv_of_platdata(dev);
529 if (ret)
530 return ret;
531#endif
532 priv->phy = regmap_get_range(plat->map, 0);
533 priv->pctl = regmap_get_range(plat->map, 1);
534 priv->grf = regmap_get_range(plat->map, 2);
535 priv->cru = regmap_get_range(plat->map, 3);
536 priv->msch = regmap_get_range(plat->map, 4);
537 priv->ddr_grf = regmap_get_range(plat->map, 5);
538
539 debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n",
540 __func__, priv->phy, priv->pctl, priv->grf, priv->cru,
541 priv->msch, priv->ddr_grf);
542 ret = sdram_init_detect(priv, params);
543 if (ret < 0) {
544 printf("%s DRAM init failed%d\n", __func__, ret);
545 return ret;
546 }
547
548 return 0;
549}
550
551static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev)
552{
553#if !CONFIG_IS_ENABLED(OF_PLATDATA)
554 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
555 int ret;
556
557 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
558 (u32 *)&plat->sdram_params,
559 sizeof(plat->sdram_params) / sizeof(u32));
560 if (ret) {
561 printf("%s: Cannot read rockchip,sdram-params %d\n",
562 __func__, ret);
563 return ret;
564 }
565 ret = regmap_init_mem(dev, &plat->map);
566 if (ret)
567 printf("%s: regmap failed %d\n", __func__, ret);
568#endif
569 return 0;
570}
571
572#endif
573
Kever Yang39648e62017-06-23 16:11:07 +0800574static int rk3328_dmc_probe(struct udevice *dev)
575{
Kever Yang85a38742019-08-02 10:39:59 +0300576#ifdef CONFIG_TPL_BUILD
577 if (rk3328_dmc_init(dev))
578 return 0;
579#else
Kever Yang39648e62017-06-23 16:11:07 +0800580 struct dram_info *priv = dev_get_priv(dev);
581
582 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
583 debug("%s: grf=%p\n", __func__, priv->grf);
584 priv->info.base = CONFIG_SYS_SDRAM_BASE;
585 priv->info.size = rockchip_sdram_size(
586 (phys_addr_t)&priv->grf->os_reg[2]);
Kever Yang85a38742019-08-02 10:39:59 +0300587#endif
Kever Yang39648e62017-06-23 16:11:07 +0800588 return 0;
589}
590
591static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info)
592{
593 struct dram_info *priv = dev_get_priv(dev);
594
595 *info = priv->info;
596
597 return 0;
598}
599
600static struct ram_ops rk3328_dmc_ops = {
601 .get_info = rk3328_dmc_get_info,
602};
603
Kever Yang39648e62017-06-23 16:11:07 +0800604static const struct udevice_id rk3328_dmc_ids[] = {
605 { .compatible = "rockchip,rk3328-dmc" },
606 { }
607};
608
Walter Lozanoe3e24702020-06-25 01:10:04 -0300609U_BOOT_DRIVER(rockchip_rk3328_dmc) = {
Kever Yang39648e62017-06-23 16:11:07 +0800610 .name = "rockchip_rk3328_dmc",
611 .id = UCLASS_RAM,
612 .of_match = rk3328_dmc_ids,
613 .ops = &rk3328_dmc_ops,
Kever Yang85a38742019-08-02 10:39:59 +0300614#ifdef CONFIG_TPL_BUILD
615 .ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata,
616#endif
Kever Yang39648e62017-06-23 16:11:07 +0800617 .probe = rk3328_dmc_probe,
618 .priv_auto_alloc_size = sizeof(struct dram_info),
Kever Yang85a38742019-08-02 10:39:59 +0300619#ifdef CONFIG_TPL_BUILD
620 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
621#endif
Kever Yang39648e62017-06-23 16:11:07 +0800622};