blob: 1679144caa60d2b158314bbaa21f30521d288c9d [file] [log] [blame]
Wang Huan550e3dc2014-09-05 13:52:44 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <asm/io.h>
10#include <asm/arch/immap_ls102xa.h>
Xiubo Lie87f3b32014-11-21 17:40:58 +080011#include <asm/arch/ns_access.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080012#include <asm/arch/clock.h>
13#include <asm/arch/fsl_serdes.h>
Minghuan Lianda419022014-10-31 13:43:44 +080014#include <asm/pcie_layerscape.h>
Yao Yuanbca11bd2014-11-26 14:54:33 +080015#include <hwconfig.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080016#include <mmc.h>
17#include <fsl_esdhc.h>
18#include <fsl_ifc.h>
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053019#include <fsl_sec.h>
Alison Wang86949c22014-12-03 15:00:47 +080020#include <spl.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080021
22#include "../common/qixis.h"
23#include "ls1021aqds_qixis.h"
Zhao Qiang63e75fd2014-09-26 16:25:32 +080024#ifdef CONFIG_U_QE
25#include "../../../drivers/qe/qe.h"
26#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080027
Yao Yuanbca11bd2014-11-26 14:54:33 +080028#define PIN_MUX_SEL_CAN 0x03
29#define PIN_MUX_SEL_IIC2 0xa0
30#define PIN_MUX_SEL_RGMII 0x00
31#define PIN_MUX_SEL_SAI 0x0c
32#define PIN_MUX_SEL_SDHC 0x00
33
34#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
35#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
Wang Huan550e3dc2014-09-05 13:52:44 +080036DECLARE_GLOBAL_DATA_PTR;
37
38enum {
Yao Yuanbca11bd2014-11-26 14:54:33 +080039 MUX_TYPE_CAN,
40 MUX_TYPE_IIC2,
41 MUX_TYPE_RGMII,
42 MUX_TYPE_SAI,
43 MUX_TYPE_SDHC,
Wang Huan550e3dc2014-09-05 13:52:44 +080044 MUX_TYPE_SD_PCI4,
45 MUX_TYPE_SD_PC_SA_SG_SG,
46 MUX_TYPE_SD_PC_SA_PC_SG,
47 MUX_TYPE_SD_PC_SG_SG,
48};
49
50int checkboard(void)
51{
Alison Wangd612f0a2014-12-09 17:38:02 +080052#ifndef CONFIG_QSPI_BOOT
Wang Huan550e3dc2014-09-05 13:52:44 +080053 char buf[64];
Alison Wangd612f0a2014-12-09 17:38:02 +080054#endif
Alison Wang86949c22014-12-03 15:00:47 +080055#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
Wang Huan550e3dc2014-09-05 13:52:44 +080056 u8 sw;
Alison Wang86949c22014-12-03 15:00:47 +080057#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080058
59 puts("Board: LS1021AQDS\n");
60
Alison Wang86949c22014-12-03 15:00:47 +080061#ifdef CONFIG_SD_BOOT
62 puts("SD\n");
63#elif CONFIG_QSPI_BOOT
64 puts("QSPI\n");
65#else
Wang Huan550e3dc2014-09-05 13:52:44 +080066 sw = QIXIS_READ(brdcfg[0]);
67 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
68
69 if (sw < 0x8)
70 printf("vBank: %d\n", sw);
71 else if (sw == 0x8)
72 puts("PromJet\n");
73 else if (sw == 0x9)
74 puts("NAND\n");
75 else if (sw == 0x15)
76 printf("IFCCard\n");
77 else
78 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
Alison Wang86949c22014-12-03 15:00:47 +080079#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080080
Alison Wangd612f0a2014-12-09 17:38:02 +080081#ifndef CONFIG_QSPI_BOOT
Wang Huan550e3dc2014-09-05 13:52:44 +080082 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
83 QIXIS_READ(id), QIXIS_READ(arch));
84
85 printf("FPGA: v%d (%s), build %d\n",
86 (int)QIXIS_READ(scver), qixis_read_tag(buf),
87 (int)qixis_read_minor());
Alison Wangd612f0a2014-12-09 17:38:02 +080088#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080089
90 return 0;
91}
92
93unsigned long get_board_sys_clk(void)
94{
95 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
96
97 switch (sysclk_conf & 0x0f) {
98 case QIXIS_SYSCLK_64:
99 return 64000000;
100 case QIXIS_SYSCLK_83:
101 return 83333333;
102 case QIXIS_SYSCLK_100:
103 return 100000000;
104 case QIXIS_SYSCLK_125:
105 return 125000000;
106 case QIXIS_SYSCLK_133:
107 return 133333333;
108 case QIXIS_SYSCLK_150:
109 return 150000000;
110 case QIXIS_SYSCLK_160:
111 return 160000000;
112 case QIXIS_SYSCLK_166:
113 return 166666666;
114 }
115 return 66666666;
116}
117
118unsigned long get_board_ddr_clk(void)
119{
120 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
121
122 switch ((ddrclk_conf & 0x30) >> 4) {
123 case QIXIS_DDRCLK_100:
124 return 100000000;
125 case QIXIS_DDRCLK_125:
126 return 125000000;
127 case QIXIS_DDRCLK_133:
128 return 133333333;
129 }
130 return 66666666;
131}
132
Chenhui Zhaoafff1372014-11-06 10:51:59 +0800133int select_i2c_ch_pca9547(u8 ch)
134{
135 int ret;
136
137 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
138 if (ret) {
139 puts("PCA: failed to select proper channel\n");
140 return ret;
141 }
142
143 return 0;
144}
145
Wang Huan550e3dc2014-09-05 13:52:44 +0800146int dram_init(void)
147{
Chenhui Zhaoafff1372014-11-06 10:51:59 +0800148 /*
149 * When resuming from deep sleep, the I2C channel may not be
150 * in the default channel. So, switch to the default channel
151 * before accessing DDR SPD.
152 */
153 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
Wang Huan550e3dc2014-09-05 13:52:44 +0800154 gd->ram_size = initdram(0);
155
156 return 0;
157}
158
159#ifdef CONFIG_FSL_ESDHC
160struct fsl_esdhc_cfg esdhc_cfg[1] = {
161 {CONFIG_SYS_FSL_ESDHC_ADDR},
162};
163
164int board_mmc_init(bd_t *bis)
165{
166 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
167
168 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
169}
170#endif
171
Wang Huan550e3dc2014-09-05 13:52:44 +0800172int board_early_init_f(void)
173{
174 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
175 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
176
177#ifdef CONFIG_TSEC_ENET
Wang Huan550e3dc2014-09-05 13:52:44 +0800178 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
Alison Wang0ab17232014-10-17 15:26:36 +0800179 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
Wang Huan550e3dc2014-09-05 13:52:44 +0800180#endif
181
182#ifdef CONFIG_FSL_IFC
183 init_early_memctl_regs();
184#endif
185
Alison Wangd612f0a2014-12-09 17:38:02 +0800186#ifdef CONFIG_FSL_QSPI
187 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
188#endif
189
Wang Huan550e3dc2014-09-05 13:52:44 +0800190 /* Workaround for the issue that DDR could not respond to
191 * barrier transaction which is generated by executing DSB/ISB
192 * instruction. Set CCI-400 control override register to
193 * terminate the barrier transaction. After DDR is initialized,
194 * allow barrier transaction to DDR again */
195 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
196
197 return 0;
198}
199
Alison Wang86949c22014-12-03 15:00:47 +0800200#ifdef CONFIG_SPL_BUILD
201void board_init_f(ulong dummy)
202{
203 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
204
Alison Wang8ab967b2014-12-09 17:38:14 +0800205#ifdef CONFIG_NAND_BOOT
206 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
207 u32 porsr1, pinctl;
208
209 /*
210 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
211 * NAND boot because IFC signals > IFC_AD7 are not enabled.
212 * This workaround changes RCW source to make all signals enabled.
213 */
214 porsr1 = in_be32(&gur->porsr1);
215 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
216 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
217 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
218 pinctl);
219#endif
220
Alison Wang86949c22014-12-03 15:00:47 +0800221 /* Set global data pointer */
222 gd = &gdata;
223
224 /* Clear the BSS */
225 memset(__bss_start, 0, __bss_end - __bss_start);
226
227#ifdef CONFIG_FSL_IFC
228 init_early_memctl_regs();
229#endif
230
231 get_clocks();
232
233 preloader_console_init();
234
235#ifdef CONFIG_SPL_I2C_SUPPORT
236 i2c_init_all();
237#endif
238 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
239
240 dram_init();
241
242 board_init_r(NULL, 0);
243}
244#endif
245
Wang Huan550e3dc2014-09-05 13:52:44 +0800246int config_board_mux(int ctrl_type)
247{
Yao Yuanbca11bd2014-11-26 14:54:33 +0800248 u8 reg12, reg14;
Wang Huan550e3dc2014-09-05 13:52:44 +0800249
250 reg12 = QIXIS_READ(brdcfg[12]);
Yao Yuanbca11bd2014-11-26 14:54:33 +0800251 reg14 = QIXIS_READ(brdcfg[14]);
Wang Huan550e3dc2014-09-05 13:52:44 +0800252
253 switch (ctrl_type) {
Yao Yuanbca11bd2014-11-26 14:54:33 +0800254 case MUX_TYPE_CAN:
255 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
256 break;
257 case MUX_TYPE_IIC2:
258 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
259 break;
260 case MUX_TYPE_RGMII:
261 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
262 break;
263 case MUX_TYPE_SAI:
264 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
265 break;
266 case MUX_TYPE_SDHC:
267 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
268 break;
Wang Huan550e3dc2014-09-05 13:52:44 +0800269 case MUX_TYPE_SD_PCI4:
270 reg12 = 0x38;
271 break;
272 case MUX_TYPE_SD_PC_SA_SG_SG:
273 reg12 = 0x01;
274 break;
275 case MUX_TYPE_SD_PC_SA_PC_SG:
276 reg12 = 0x01;
277 break;
278 case MUX_TYPE_SD_PC_SG_SG:
279 reg12 = 0x21;
280 break;
281 default:
282 printf("Wrong mux interface type\n");
283 return -1;
284 }
285
286 QIXIS_WRITE(brdcfg[12], reg12);
Yao Yuanbca11bd2014-11-26 14:54:33 +0800287 QIXIS_WRITE(brdcfg[14], reg14);
Wang Huan550e3dc2014-09-05 13:52:44 +0800288
289 return 0;
290}
291
292int config_serdes_mux(void)
293{
294 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
295 u32 cfg;
296
297 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
298 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
299
300 switch (cfg) {
301 case 0x0:
302 config_board_mux(MUX_TYPE_SD_PCI4);
303 break;
304 case 0x30:
305 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
306 break;
307 case 0x60:
308 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
309 break;
310 case 0x70:
311 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
312 break;
313 default:
314 printf("SRDS1 prtcl:0x%x\n", cfg);
315 break;
316 }
317
318 return 0;
319}
320
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530321int misc_init_r(void)
322{
Yao Yuanbca11bd2014-11-26 14:54:33 +0800323 int conflict_flag;
324
325 /* some signals can not enable simultaneous*/
326 conflict_flag = 0;
327 if (hwconfig("sdhc"))
328 conflict_flag++;
329 if (hwconfig("iic2"))
330 conflict_flag++;
331 if (conflict_flag > 1) {
332 printf("WARNING: pin conflict !\n");
333 return 0;
334 }
335
336 conflict_flag = 0;
337 if (hwconfig("rgmii"))
338 conflict_flag++;
339 if (hwconfig("can"))
340 conflict_flag++;
341 if (hwconfig("sai"))
342 conflict_flag++;
343 if (conflict_flag > 1) {
344 printf("WARNING: pin conflict !\n");
345 return 0;
346 }
347
348 if (hwconfig("can"))
349 config_board_mux(MUX_TYPE_CAN);
350 else if (hwconfig("rgmii"))
351 config_board_mux(MUX_TYPE_RGMII);
352 else if (hwconfig("sai"))
353 config_board_mux(MUX_TYPE_SAI);
354
355 if (hwconfig("iic2"))
356 config_board_mux(MUX_TYPE_IIC2);
357 else if (hwconfig("sdhc"))
358 config_board_mux(MUX_TYPE_SDHC);
359
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530360#ifdef CONFIG_FSL_CAAM
361 return sec_init();
362#endif
Yao Yuanbca11bd2014-11-26 14:54:33 +0800363 return 0;
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530364}
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530365
Xiubo Lie87f3b32014-11-21 17:40:58 +0800366#ifdef CONFIG_LS102XA_NS_ACCESS
367static struct csu_ns_dev ns_dev[] = {
368 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
369 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
370 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
371 { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
372 { CSU_CSLX_OCRAM, CSU_ALL_RW },
373 { CSU_CSLX_GIC, CSU_ALL_RW },
374 { CSU_CSLX_PCIE1, CSU_ALL_RW },
375 { CSU_CSLX_OCRAM2, CSU_ALL_RW },
376 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
377 { CSU_CSLX_PCIE2, CSU_ALL_RW },
378 { CSU_CSLX_SATA, CSU_ALL_RW },
379 { CSU_CSLX_USB3, CSU_ALL_RW },
380 { CSU_CSLX_SERDES, CSU_ALL_RW },
381 { CSU_CSLX_QDMA, CSU_ALL_RW },
382 { CSU_CSLX_LPUART2, CSU_ALL_RW },
383 { CSU_CSLX_LPUART1, CSU_ALL_RW },
384 { CSU_CSLX_LPUART4, CSU_ALL_RW },
385 { CSU_CSLX_LPUART3, CSU_ALL_RW },
386 { CSU_CSLX_LPUART6, CSU_ALL_RW },
387 { CSU_CSLX_LPUART5, CSU_ALL_RW },
388 { CSU_CSLX_DSPI2, CSU_ALL_RW },
389 { CSU_CSLX_DSPI1, CSU_ALL_RW },
390 { CSU_CSLX_QSPI, CSU_ALL_RW },
391 { CSU_CSLX_ESDHC, CSU_ALL_RW },
392 { CSU_CSLX_2D_ACE, CSU_ALL_RW },
393 { CSU_CSLX_IFC, CSU_ALL_RW },
394 { CSU_CSLX_I2C1, CSU_ALL_RW },
395 { CSU_CSLX_USB2, CSU_ALL_RW },
396 { CSU_CSLX_I2C3, CSU_ALL_RW },
397 { CSU_CSLX_I2C2, CSU_ALL_RW },
398 { CSU_CSLX_DUART2, CSU_ALL_RW },
399 { CSU_CSLX_DUART1, CSU_ALL_RW },
400 { CSU_CSLX_WDT2, CSU_ALL_RW },
401 { CSU_CSLX_WDT1, CSU_ALL_RW },
402 { CSU_CSLX_EDMA, CSU_ALL_RW },
403 { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
404 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
405 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
406 { CSU_CSLX_DDR, CSU_ALL_RW },
407 { CSU_CSLX_QUICC, CSU_ALL_RW },
408 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
409 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
410 { CSU_CSLX_SFP, CSU_ALL_RW },
411 { CSU_CSLX_TMU, CSU_ALL_RW },
412 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
413 { CSU_CSLX_RESERVED0, CSU_ALL_RW },
414 { CSU_CSLX_ETSEC1, CSU_ALL_RW },
415 { CSU_CSLX_SEC5_5, CSU_ALL_RW },
416 { CSU_CSLX_ETSEC3, CSU_ALL_RW },
417 { CSU_CSLX_ETSEC2, CSU_ALL_RW },
418 { CSU_CSLX_GPIO2, CSU_ALL_RW },
419 { CSU_CSLX_GPIO1, CSU_ALL_RW },
420 { CSU_CSLX_GPIO4, CSU_ALL_RW },
421 { CSU_CSLX_GPIO3, CSU_ALL_RW },
422 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
423 { CSU_CSLX_CSU, CSU_ALL_RW },
424 { CSU_CSLX_ASRC, CSU_ALL_RW },
425 { CSU_CSLX_SPDIF, CSU_ALL_RW },
426 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
427 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
428 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
429 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
430 { CSU_CSLX_SAI2, CSU_ALL_RW },
431 { CSU_CSLX_SAI1, CSU_ALL_RW },
432 { CSU_CSLX_SAI4, CSU_ALL_RW },
433 { CSU_CSLX_SAI3, CSU_ALL_RW },
434 { CSU_CSLX_FTM2, CSU_ALL_RW },
435 { CSU_CSLX_FTM1, CSU_ALL_RW },
436 { CSU_CSLX_FTM4, CSU_ALL_RW },
437 { CSU_CSLX_FTM3, CSU_ALL_RW },
438 { CSU_CSLX_FTM6, CSU_ALL_RW },
439 { CSU_CSLX_FTM5, CSU_ALL_RW },
440 { CSU_CSLX_FTM8, CSU_ALL_RW },
441 { CSU_CSLX_FTM7, CSU_ALL_RW },
442 { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
443 { CSU_CSLX_EPU, CSU_ALL_RW },
444 { CSU_CSLX_GDI, CSU_ALL_RW },
445 { CSU_CSLX_DDI, CSU_ALL_RW },
446 { CSU_CSLX_RESERVED1, CSU_ALL_RW },
447 { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
448 { CSU_CSLX_RESERVED2, CSU_ALL_RW },
449};
450#endif
451
Wang Huan550e3dc2014-09-05 13:52:44 +0800452int board_init(void)
453{
454 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
455
456 /* Set CCI-400 control override register to
457 * enable barrier transaction */
458 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
Jason Jin644bc7e2014-10-17 15:26:32 +0800459 /*
460 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
461 * All transactions are treated as non-shareable
462 */
463 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
464 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
465 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
Wang Huan550e3dc2014-09-05 13:52:44 +0800466
467 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
468
469#ifndef CONFIG_SYS_FSL_NO_SERDES
470 fsl_serdes_init();
471 config_serdes_mux();
472#endif
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800473
Xiubo Lie87f3b32014-11-21 17:40:58 +0800474#ifdef CONFIG_LS102XA_NS_ACCESS
475 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
476#endif
477
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800478#ifdef CONFIG_U_QE
479 u_qe_init();
480#endif
481
Wang Huan550e3dc2014-09-05 13:52:44 +0800482 return 0;
483}
484
Simon Glasse895a4b2014-10-23 18:58:47 -0600485int ft_board_setup(void *blob, bd_t *bd)
Wang Huan550e3dc2014-09-05 13:52:44 +0800486{
487 ft_cpu_setup(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600488
Minghuan Lianda419022014-10-31 13:43:44 +0800489#ifdef CONFIG_PCIE_LAYERSCAPE
490 ft_pcie_setup(blob, bd);
491#endif
492
Simon Glasse895a4b2014-10-23 18:58:47 -0600493 return 0;
Wang Huan550e3dc2014-09-05 13:52:44 +0800494}
495
496u8 flash_read8(void *addr)
497{
498 return __raw_readb(addr + 1);
499}
500
501void flash_write16(u16 val, void *addr)
502{
503 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
504
505 __raw_writew(shftval, addr);
506}
507
508u16 flash_read16(void *addr)
509{
510 u16 val = __raw_readw(addr);
511
512 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
513}