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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / bcfdf055f8956b784085bafa14f1731cc141c414 / . / arch / sandbox / dts / test.dts
blob: b0f0ca8f19ce9104c58737ff8840aca58f26dfb3 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]15 mmc0 = "/mmc0";
16 mmc1 = "/mmc1";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]17 pci0 = &pci;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]18 remoteproc1 = &rproc_1;
19 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]20 rtc0 = &rtc_0;
21 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]22 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]23 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]24 testbus3 = "/some-bus";
25 testfdt0 = "/some-bus/c-test@0";
26 testfdt1 = "/some-bus/c-test@1";
27 testfdt3 = "/b-test";
28 testfdt5 = "/some-bus/c-test@5";
29 testfdt8 = "/a-test";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]30 usb0 = &usb_0;
31 usb1 = &usb_1;
32 usb2 = &usb_2;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]33 };
34
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]35 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]36 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]37 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]38 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]39 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]40 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]41 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
42 <0>, <&gpio_a 12>;
43 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
44 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
45 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]46 };
47
48 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]49 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]50 compatible = "not,compatible";
51 };
52
53 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]54 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]55 };
56
57 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]58 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]59 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]60 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]61 ping-add = <3>;
62 };
63
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]64 phy_provider0: gen_phy@0 {
65 compatible = "sandbox,phy";
66 #phy-cells = <1>;
67 };
68
69 phy_provider1: gen_phy@1 {
70 compatible = "sandbox,phy";
71 #phy-cells = <0>;
72 broken;
73 };
74
75 gen_phy_user: gen_phy_user {
76 compatible = "simple-bus";
77 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
78 phy-names = "phy1", "phy2", "phy3";
79 };
80
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]81 some-bus {
82 #address-cells = <1>;
83 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]84 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]85 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]86 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]87 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]88 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]89 compatible = "denx,u-boot-fdt-test";
90 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]91 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]92 ping-add = <5>;
93 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]94 c-test@0 {
95 compatible = "denx,u-boot-fdt-test";
96 reg = <0>;
97 ping-expect = <6>;
98 ping-add = <6>;
99 };
100 c-test@1 {
101 compatible = "denx,u-boot-fdt-test";
102 reg = <1>;
103 ping-expect = <7>;
104 ping-add = <7>;
105 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]106 };
107
108 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]109 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]110 ping-expect = <6>;
111 ping-add = <6>;
112 compatible = "google,another-fdt-test";
113 };
114
115 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]116 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]117 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]118 ping-add = <6>;
119 compatible = "google,another-fdt-test";
120 };
121
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]122 f-test {
123 compatible = "denx,u-boot-fdt-test";
124 };
125
126 g-test {
127 compatible = "denx,u-boot-fdt-test";
128 };
129
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]130 clocks {
131 clk_fixed: clk-fixed {
132 compatible = "fixed-clock";
133 #clock-cells = <0>;
134 clock-frequency = <1234>;
135 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]136 };
137
138 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]139 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]140 #clock-cells = <1>;
141 };
142
143 clk-test {
144 compatible = "sandbox,clk-test";
145 clocks = <&clk_fixed>,
146 <&clk_sandbox 1>,
147 <&clk_sandbox 0>;
148 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]149 };
150
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]151 eth@10002000 {
152 compatible = "sandbox,eth";
153 reg = <0x10002000 0x1000>;
154 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
155 };
156
157 eth_5: eth@10003000 {
158 compatible = "sandbox,eth";
159 reg = <0x10003000 0x1000>;
160 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
161 };
162
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]163 eth_3: sbe5 {
164 compatible = "sandbox,eth";
165 reg = <0x10005000 0x1000>;
166 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>;
167 };
168
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]169 eth@10004000 {
170 compatible = "sandbox,eth";
171 reg = <0x10004000 0x1000>;
172 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
173 };
174
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]175 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]176 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]177 gpio-controller;
178 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]179 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]180 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]181 };
182
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]183 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]184 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]185 gpio-controller;
186 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]187 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]188 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]189 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]190
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]191 i2c@0 {
192 #address-cells = <1>;
193 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]194 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]195 compatible = "sandbox,i2c";
196 clock-frequency = <100000>;
197 eeprom@2c {
198 reg = <0x2c>;
199 compatible = "i2c-eeprom";
200 emul {
201 compatible = "sandbox,i2c-eeprom";
202 sandbox,filename = "i2c.bin";
203 sandbox,size = <256>;
204 };
205 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]206
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]207 rtc_0: rtc@43 {
208 reg = <0x43>;
209 compatible = "sandbox-rtc";
210 emul {
211 compatible = "sandbox,i2c-rtc";
212 };
213 };
214
215 rtc_1: rtc@61 {
216 reg = <0x61>;
217 compatible = "sandbox-rtc";
218 emul {
219 compatible = "sandbox,i2c-rtc";
220 };
221 };
222
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]223 sandbox_pmic: sandbox_pmic {
224 reg = <0x40>;
225 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]226 };
227
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]228 adc@0 {
229 compatible = "sandbox,adc";
230 vdd-supply = <&buck2>;
231 vss-microvolts = <0>;
232 };
233
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]234 lcd {
235 u-boot,dm-pre-reloc;
236 compatible = "sandbox,lcd-sdl";
237 xres = <1366>;
238 yres = <768>;
239 };
240
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]241 leds {
242 compatible = "gpio-leds";
243
244 iracibble {
245 gpios = <&gpio_a 1 0>;
246 label = "sandbox:red";
247 };
248
249 martinet {
250 gpios = <&gpio_a 2 0>;
251 label = "sandbox:green";
252 };
253 };
254
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]255 mbox: mbox {
256 compatible = "sandbox,mbox";
257 #mbox-cells = <1>;
258 };
259
260 mbox-test {
261 compatible = "sandbox,mbox-test";
262 mboxes = <&mbox 100>, <&mbox 1>;
263 mbox-names = "other", "test";
264 };
265
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]266 mmc2 {
267 compatible = "sandbox,mmc";
268 };
269
270 mmc1 {
271 compatible = "sandbox,mmc";
272 };
273
274 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]275 compatible = "sandbox,mmc";
276 };
277
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]278 pci: pci-controller {
279 compatible = "sandbox,pci";
280 device_type = "pci";
281 #address-cells = <3>;
282 #size-cells = <2>;
283 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
284 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
285 pci@1f,0 {
286 compatible = "pci-generic";
287 reg = <0xf800 0 0 0 0>;
288 emul@1f,0 {
289 compatible = "sandbox,swap-case";
290 };
291 };
292 };
293
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]294 probing {
295 compatible = "simple-bus";
296 test1 {
297 compatible = "denx,u-boot-probe-test";
298 };
299
300 test2 {
301 compatible = "denx,u-boot-probe-test";
302 };
303
304 test3 {
305 compatible = "denx,u-boot-probe-test";
306 };
307
308 test4 {
309 compatible = "denx,u-boot-probe-test";
310 };
311 };
312
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]313 pwrdom: power-domain {
314 compatible = "sandbox,power-domain";
315 #power-domain-cells = <1>;
316 };
317
318 power-domain-test {
319 compatible = "sandbox,power-domain-test";
320 power-domains = <&pwrdom 2>;
321 };
322
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]323 pwm {
324 compatible = "sandbox,pwm";
325 };
326
327 pwm2 {
328 compatible = "sandbox,pwm";
329 };
330
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]331 ram {
332 compatible = "sandbox,ram";
333 };
334
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]335 reset@0 {
336 compatible = "sandbox,warm-reset";
337 };
338
339 reset@1 {
340 compatible = "sandbox,reset";
341 };
342
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]343 resetc: reset-ctl {
344 compatible = "sandbox,reset-ctl";
345 #reset-cells = <1>;
346 };
347
348 reset-ctl-test {
349 compatible = "sandbox,reset-ctl-test";
350 resets = <&resetc 100>, <&resetc 2>;
351 reset-names = "other", "test";
352 };
353
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]354 rproc_1: rproc@1 {
355 compatible = "sandbox,test-processor";
356 remoteproc-name = "remoteproc-test-dev1";
357 };
358
359 rproc_2: rproc@2 {
360 compatible = "sandbox,test-processor";
361 internal-memory-mapped;
362 remoteproc-name = "remoteproc-test-dev2";
363 };
364
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]365 spi@0 {
366 #address-cells = <1>;
367 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]368 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]369 compatible = "sandbox,spi";
370 cs-gpios = <0>, <&gpio_a 0>;
371 spi.bin@0 {
372 reg = <0>;
373 compatible = "spansion,m25p16", "spi-flash";
374 spi-max-frequency = <40000000>;
375 sandbox,filename = "spi.bin";
376 };
377 };
378
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]379 syscon@0 {
380 compatible = "sandbox,syscon0";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]381 reg = <0x10 4>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]382 };
383
384 syscon@1 {
385 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]386 reg = <0x20 5
387 0x28 6
388 0x30 7
389 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]390 };
391
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]392 timer {
393 compatible = "sandbox,timer";
394 clock-frequency = <1000000>;
395 };
396
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]397 uart0: serial {
398 compatible = "sandbox,serial";
399 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]400 };
401
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]402 usb_0: usb@0 {
403 compatible = "sandbox,usb";
404 status = "disabled";
405 hub {
406 compatible = "sandbox,usb-hub";
407 #address-cells = <1>;
408 #size-cells = <0>;
409 flash-stick {
410 reg = <0>;
411 compatible = "sandbox,usb-flash";
412 };
413 };
414 };
415
416 usb_1: usb@1 {
417 compatible = "sandbox,usb";
418 hub {
419 compatible = "usb-hub";
420 usb,device-class = <9>;
421 hub-emul {
422 compatible = "sandbox,usb-hub";
423 #address-cells = <1>;
424 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]425 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]426 reg = <0>;
427 compatible = "sandbox,usb-flash";
428 sandbox,filepath = "testflash.bin";
429 };
430
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]431 flash-stick@1 {
432 reg = <1>;
433 compatible = "sandbox,usb-flash";
434 sandbox,filepath = "testflash1.bin";
435 };
436
437 flash-stick@2 {
438 reg = <2>;
439 compatible = "sandbox,usb-flash";
440 sandbox,filepath = "testflash2.bin";
441 };
442
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]443 keyb@3 {
444 reg = <3>;
445 compatible = "sandbox,usb-keyb";
446 };
447
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]448 };
449 };
450 };
451
452 usb_2: usb@2 {
453 compatible = "sandbox,usb";
454 status = "disabled";
455 };
456
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]457 spmi: spmi@0 {
458 compatible = "sandbox,spmi";
459 #address-cells = <0x1>;
460 #size-cells = <0x1>;
461 pm8916@0 {
462 compatible = "qcom,spmi-pmic";
463 reg = <0x0 0x1>;
464 #address-cells = <0x1>;
465 #size-cells = <0x1>;
466
467 spmi_gpios: gpios@c000 {
468 compatible = "qcom,pm8916-gpio";
469 reg = <0xc000 0x400>;
470 gpio-controller;
471 gpio-count = <4>;
472 #gpio-cells = <2>;
473 gpio-bank-name="spmi";
474 };
475 };
476 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]477
478 wdt0: wdt@0 {
479 compatible = "sandbox,wdt";
480 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]481
482 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]483 #address-cells = <1>;
484 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]485 chosen-test {
486 compatible = "denx,u-boot-fdt-test";
487 reg = <9 1>;
488 };
489 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]490};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]491
492#include "sandbox_pmic.dtsi"