Blame - arch/arm/mach-zynqmp/Kconfig - platform/external/u-boot

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Siva Durga Prasad Paladugu	0b54a9d	2015-06-10 15:50:57 +0530	[diff] [blame]	1	if ARCH_ZYNQMP
				2
Tien Fong Chee	0c3a9ed	2019-01-23 14:20:03 +0800	[diff] [blame]	3	config SPL_FS_FAT
Simon Glass	ae56db5	2016-09-12 23:18:38 -0600	[diff] [blame]	4	default y
				5
Simon Glass	77d2f7f	2016-09-12 23:18:41 -0600	[diff] [blame]	6	config SPL_LIBCOMMON_SUPPORT
				7	default y
				8
Simon Glass	1646eba	2016-09-12 23:18:42 -0600	[diff] [blame]	9	config SPL_LIBDISK_SUPPORT
				10	default y
				11
Simon Glass	cc4288e	2016-09-12 23:18:43 -0600	[diff] [blame]	12	config SPL_LIBGENERIC_SUPPORT
				13	default y
				14
Simon Glass	103c5f1	2021-08-08 12:20:09 -0600	[diff] [blame]	15	config SPL_MMC
Alexandru Gagniuc	0dcf18c	2017-04-04 10:02:58 -0700	[diff] [blame]	16	default y if MMC_SDHCI_ZYNQ
Simon Glass	1fdf7c6	2016-09-12 23:18:44 -0600	[diff] [blame]	17
Simon Glass	2a73606	2021-08-08 12:20:12 -0600	[diff] [blame]	18	config SPL_SERIAL
Simon Glass	e00f76c	2016-09-12 23:18:56 -0600	[diff] [blame]	19	default y
				20
Simon Glass	e404ade	2016-09-12 23:18:57 -0600	[diff] [blame]	21	config SPL_SPI_FLASH_SUPPORT
				22	default y if ZYNQ_QSPI
				23
Simon Glass	ea2ca7e	2021-08-08 12:20:14 -0600	[diff] [blame]	24	config SPL_SPI
Simon Glass	f35ed9e	2016-09-12 23:18:58 -0600	[diff] [blame]	25	default y if ZYNQ_QSPI
				26
Michal Simek	84c7204	2015-01-15 10:01:51 +0100	[diff] [blame]	27	config SYS_BOARD
Liam Beguin	1814194	2021-10-20 11:25:18 -0400	[diff] [blame]	28	string "Board name"
Michal Simek	84c7204	2015-01-15 10:01:51 +0100	[diff] [blame]	29	default "zynqmp"
				30
				31	config SYS_VENDOR
Mike Looijmans	ef4cab9	2017-01-03 09:47:52 +0100	[diff] [blame]	32	string "Vendor name"
Michal Simek	84c7204	2015-01-15 10:01:51 +0100	[diff] [blame]	33	default "xilinx"
				34
				35	config SYS_SOC
				36	default "zynqmp"
				37
Siva Durga Prasad Paladugu	e042d36	2017-07-13 19:01:11 +0530	[diff] [blame]	38	config SYS_MEM_RSVD_FOR_MMU
				39	bool "Reserve memory for MMU Table"
				40	help
				41	If defined this option is used to setup different space for
				42	MMU table than the one which will be allocated during
				43	relocation.
				44
Mike Looijmans	3b64608	2016-09-20 11:37:24 +0200	[diff] [blame]	45	config BOOT_INIT_FILE
				46	string "boot.bin init register filename"
Michal Simek	9cf9da7	2016-12-16 13:00:26 +0100	[diff] [blame]	47	depends on SPL
Mike Looijmans	3b64608	2016-09-20 11:37:24 +0200	[diff] [blame]	48	default ""
				49	help
				50	Add register writes to boot.bin format (max 256 pairs).
				51	Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
				52
Michal Simek	c85a6b7	2016-10-21 12:58:17 +0200	[diff] [blame]	53	config PMUFW_INIT_FILE
				54	string "PMU firmware"
				55	depends on SPL
				56	default ""
				57	help
				58	Include external PMUFW (Platform Management Unit FirmWare) to
				59	a Xilinx bootable image (boot.bin).
				60
Luca Ceresoli	c28a9cf	2019-05-21 18:06:43 +0200	[diff] [blame]	61	config ZYNQMP_SPL_PM_CFG_OBJ_FILE
				62	string "PMU firmware configuration object to load at runtime by SPL"
				63	depends on SPL
				64	help
				65	Path to a binary PMU firmware configuration object to be linked
				66	into U-Boot SPL and loaded at runtime into the PMU firmware.
				67
				68	The ZynqMP Power Management Unit (PMU) needs a configuration
				69	object for most SoC peripherals to work. To have it loaded by
				70	U-Boot SPL set here the file name (absolute path or relative to
				71	the top source tree) of your configuration, which must be a
				72	binary blob. It will be linked in the SPL binary and loaded
				73	into the PMU firmware by U-Boot SPL during board
				74	initialization.
				75
				76	Leave this option empty if your PMU firmware has a hard-coded
				77	configuration object or you are loading it by any other means.
				78
Siva Durga Prasad Paladugu	3b644a3	2018-01-12 15:35:46 +0530	[diff] [blame]	79	config ZYNQMP_NO_DDR
				80	bool "Disable DDR MMU mapping"
				81	help
				82	This option configures MMU with no DDR to avoid speculative
				83	access to DDR memory where DDR is not present.
				84
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	85	config SPL_ZYNQMP_DRAM_ECC_INIT
				86	bool "Initialize DRAM ECC"
				87	depends on SPL
				88	help
				89	This option initializes all memory to 0xdeadbeef. Must be set if your
				90	memory is of ECC type.
				91
				92	config SPL_ZYNQMP_DRAM_BANK1_BASE
				93	depends on SPL_ZYNQMP_DRAM_ECC_INIT
				94	hex "DRAM Bank1 address"
Michal Simek	a156b6c	2023-10-26 08:34:31 +0200	[diff] [blame]	95	default 0x00000000
				96	help
				97	Start address of DRAM ECC bank1
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	98
				99	config SPL_ZYNQMP_DRAM_BANK1_LEN
				100	depends on SPL_ZYNQMP_DRAM_ECC_INIT
				101	hex "DRAM Bank1 size"
Michal Simek	a156b6c	2023-10-26 08:34:31 +0200	[diff] [blame]	102	default 0x80000000
				103	help
				104	Size in bytes of the DRAM ECC bank1
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	105
				106	config SPL_ZYNQMP_DRAM_BANK2_BASE
				107	depends on SPL_ZYNQMP_DRAM_ECC_INIT
				108	hex "DRAM Bank2 address"
Michal Simek	a156b6c	2023-10-26 08:34:31 +0200	[diff] [blame]	109	default 0x800000000
				110	help
				111	Start address of DRAM ECC bank2
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	112
				113	config SPL_ZYNQMP_DRAM_BANK2_LEN
				114	depends on SPL_ZYNQMP_DRAM_ECC_INIT
				115	hex "DRAM Bank2 size"
Michal Simek	a156b6c	2023-10-26 08:34:31 +0200	[diff] [blame]	116	default 0x0
				117	help
				118	Size in bytes of the DRAM ECC bank2. A null size takes no action.
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	119
Simon Glass	04e3890	2016-07-05 17:10:13 -0600	[diff] [blame]	120	config SYS_MALLOC_F_LEN
				121	default 0x600
				122
Siva Durga Prasad Paladugu	189bec4	2017-07-13 19:01:10 +0530	[diff] [blame]	123	config DEFINE_TCM_OCM_MMAP
				124	bool "Define TCM and OCM memory in MMU Table"
Siva Durga Prasad Paladugu	8940148	2017-08-01 16:24:50 +0530	[diff] [blame]	125	default y if MP
Siva Durga Prasad Paladugu	189bec4	2017-07-13 19:01:10 +0530	[diff] [blame]	126	help
				127	This option if enabled defines the TCM and OCM memory and its
				128	memory attributes in MMU table entry.
				129
Michal Simek	fd1b635	2017-07-12 13:21:27 +0200	[diff] [blame]	130	config ZYNQMP_PSU_INIT_ENABLED
				131	bool "Include psu_init"
Michal Simek	83d2941	2022-02-17 14:28:40 +0100	[diff] [blame]	132	select BOARD_EARLY_INIT_F
Michal Simek	fd1b635	2017-07-12 13:21:27 +0200	[diff] [blame]	133	help
Michal Simek	74673ca	2022-12-02 09:18:06 +0100	[diff] [blame]	134	Include psu_init to full u-boot.
				135
				136	config SPL_ZYNQMP_PSU_INIT_ENABLED
				137	bool "Include psu_init in SPL"
				138	default y if SPL
				139	select BOARD_EARLY_INIT_F
				140	help
				141	Include psu_init by default in SPL.
Michal Simek	fd1b635	2017-07-12 13:21:27 +0200	[diff] [blame]	142
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	143	config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
				144	bool "Overwrite SPL bootmode"
				145	depends on SPL
				146	help
				147	Overwrite bootmode selected via boot mode pins to tell SPL what should
				148	be the next boot device.
				149
Jorge Ramirez-Ortiz	398a74a	2021-10-13 15:48:00 +0200	[diff] [blame]	150	config SPL_ZYNQMP_RESTORE_JTAG
				151	bool "Restore JTAG"
				152	depends on SPL
				153	help
				154	Booting SPL in secure mode causes the CSU to disable the JTAG interface
				155	even if no eFuses were burnt. This option restores the interface if
				156	possible.
				157
Vipul Kumar	5dc5a53	2018-02-28 15:53:28 +0530	[diff] [blame]	158	config ZYNQ_SDHCI_MAX_FREQ
				159	default 200000000
				160
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	161	config SPL_ZYNQMP_ALT_BOOTMODE
				162	hex
				163	default 0x0 if JTAG_MODE
				164	default 0x1 if QSPI_MODE_24BIT
				165	default 0x2 if QSPI_MODE_32BIT
				166	default 0x3 if SD_MODE
				167	default 0x4 if NAND_MODE
				168	default 0x5 if SD_MODE1
				169	default 0x6 if EMMC_MODE
				170	default 0x7 if USB_MODE
Michal Simek	2661081	2016-10-26 09:24:32 +0200	[diff] [blame]	171	default 0xa if SW_USBHOST_MODE
				172	default 0xb if SW_SATA_MODE
Michal Simek	011f0c4	2017-02-15 09:41:53 +0100	[diff] [blame]	173	default 0xe if SD1_LSHFT_MODE
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	174
				175	choice
				176	prompt "Boot mode"
Michal Simek	e367240	2016-08-30 16:17:27 +0200	[diff] [blame]	177	depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
Ulf Magnusson	e7563c2	2018-01-30 14:02:01 +0100	[diff] [blame]	178	default JTAG_MODE
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	179
				180	config JTAG_MODE
				181	bool "JTAG_MODE"
				182
				183	config QSPI_MODE_24BIT
				184	bool "QSPI_MODE_24BIT"
				185
				186	config QSPI_MODE_32BIT
				187	bool "QSPI_MODE_32BIT"
				188
				189	config SD_MODE
				190	bool "SD_MODE"
				191
				192	config SD_MODE1
				193	bool "SD_MODE1"
				194
				195	config NAND_MODE
				196	bool "NAND_MODE"
				197
				198	config EMMC_MODE
				199	bool "EMMC_MODE"
				200
				201	config USB_MODE
				202	bool "USB"
				203
Michal Simek	2661081	2016-10-26 09:24:32 +0200	[diff] [blame]	204	config SW_USBHOST_MODE
				205	bool "SW USBHOST_MODE"
				206
				207	config SW_SATA_MODE
				208	bool "SW SATA_MODE"
				209
Michal Simek	011f0c4	2017-02-15 09:41:53 +0100	[diff] [blame]	210	config SD1_LSHFT_MODE
				211	bool "SD1_LSHFT_MODE"
				212
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	213	endchoice
Simon Glass	04e3890	2016-07-05 17:10:13 -0600	[diff] [blame]	214
Michal Simek	6ba36c0	2020-08-27 15:34:11 +0200	[diff] [blame]	215	source "board/xilinx/Kconfig"
				216	source "board/xilinx/zynqmp/Kconfig"
				217
Michal Simek	84c7204	2015-01-15 10:01:51 +0100	[diff] [blame]	218	endif