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Jon Loeliger5c9efb32006-04-27 10:15:16 -05001/*
Kumar Gala1b77ca82011-01-04 17:45:13 -06002 * Copyright 2006, 2010-2011 Freescale Semiconductor.
Jon Loeliger5c9efb32006-04-27 10:15:16 -05003 *
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Jon Loeligerdebb7352006-04-26 17:58:56 -05007 */
8
9/*
Jon Loeliger5c9efb32006-04-27 10:15:16 -050010 * MPC8641HPCN board configuration file
Jon Loeligerdebb7352006-04-26 17:58:56 -050011 *
12 * Make sure you change the MAC address and other network params first,
13 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
14 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/* High Level Configuration Options */
Jon Loeligerdebb7352006-04-26 17:58:56 -050020#define CONFIG_MPC8641 1 /* MPC8641 specific */
21#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
Kumar Gala7649a592009-03-31 23:02:38 -050022#define CONFIG_MP 1 /* support multiple processors */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020023#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
Becky Bruce3111d322008-11-06 17:37:35 -060024/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
Becky Bruced591a802009-02-03 18:10:54 -060025#define CONFIG_ADDR_MAP 1 /* Use addr map */
Jon Loeligerdebb7352006-04-26 17:58:56 -050026
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027/*
28 * default CCSRBAR is at 0xff700000
29 * assume U-Boot is less than 0.5MB
30 */
31#define CONFIG_SYS_TEXT_BASE 0xeff00000
32
Jon Loeligerdebb7352006-04-26 17:58:56 -050033#ifdef RUN_DIAG
Becky Bruce6bf98b12008-11-05 14:55:33 -060034#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -050035#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -050036
Becky Bruceaf5d1002008-10-31 17:14:14 -050037/*
Becky Bruce1266df82008-11-03 15:44:01 -060038 * virtual address to be used for temporary mappings. There
39 * should be 128k free at this VA.
40 */
41#define CONFIG_SYS_SCRATCH_VA 0xe0000000
42
Kumar Gala1b77ca82011-01-04 17:45:13 -060043#define CONFIG_SYS_SRIO
44#define CONFIG_SRIO1 /* SRIO port 1 */
Becky Bruceaf5d1002008-10-31 17:14:14 -050045
Ed Swarthout63cec582007-08-02 14:09:49 -050046#define CONFIG_PCI 1 /* Enable PCI/PCIE */
Kumar Gala46f3e382010-07-09 00:02:34 -050047#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */
48#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */
Ed Swarthout63cec582007-08-02 14:09:49 -050049#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ba93f62008-10-21 18:06:15 -050050#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Becky Bruce4933b912008-01-23 16:31:01 -060051#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
Jon Loeliger5c9efb32006-04-27 10:15:16 -050052
Wolfgang Denk53677ef2008-05-20 16:00:29 +020053#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerdebb7352006-04-26 17:58:56 -050054#define CONFIG_ENV_OVERWRITE
Jon Loeliger5c9efb32006-04-27 10:15:16 -050055
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050056#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050057#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
Becky Bruced591a802009-02-03 18:10:54 -060058#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
Jon Loeligerdebb7352006-04-26 17:58:56 -050059
Wolfgang Denk53677ef2008-05-20 16:00:29 +020060#define CONFIG_ALTIVEC 1
Jon Loeligerdebb7352006-04-26 17:58:56 -050061
Jon Loeliger5c9efb32006-04-27 10:15:16 -050062/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050063 * L2CR setup -- make sure this is right for your board!
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_L2
Jon Loeligerdebb7352006-04-26 17:58:56 -050066#define L2_INIT 0
67#define L2_ENABLE (L2CR_L2E)
68
69#ifndef CONFIG_SYS_CLK_FREQ
Ed Swarthout63cec582007-08-02 14:09:49 -050070#ifndef __ASSEMBLY__
71extern unsigned long get_board_sys_clk(unsigned long dummy);
72#endif
Wolfgang Denk53677ef2008-05-20 16:00:29 +020073#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -050074#endif
75
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
77#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerdebb7352006-04-26 17:58:56 -050078
Jon Loeligerdebb7352006-04-26 17:58:56 -050079/*
Becky Bruce3111d322008-11-06 17:37:35 -060080 * With the exception of PCI Memory and Rapid IO, most devices will simply
81 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
82 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
83 */
84#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -050085#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
Becky Bruce3111d322008-11-06 17:37:35 -060086#else
Becky Bruce1605cc92011-10-03 19:10:51 -050087#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -060088#endif
89
90/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050091 * Base addresses -- Note these are effective addresses where the
92 * actual resources get mapped (not physical addresses)
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Becky Brucec759a012008-11-06 17:36:04 -060095#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeligerdebb7352006-04-26 17:58:56 -050097
Becky Bruce3111d322008-11-06 17:37:35 -060098/* Physical addresses */
99#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Becky Bruce1605cc92011-10-03 19:10:51 -0500100#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
101#define CONFIG_SYS_CCSRBAR_PHYS \
102 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
103 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600104
york076bff82010-07-02 22:25:52 +0000105#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
106
Jon Loeligerdebb7352006-04-26 17:58:56 -0500107/*
108 * DDR Setup
109 */
York Sun5614e712013-09-30 09:22:09 -0700110#define CONFIG_SYS_FSL_DDR2
Kumar Gala6a8e5692008-08-26 15:01:35 -0500111#undef CONFIG_FSL_DDR_INTERACTIVE
112#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
113#define CONFIG_DDR_SPD
114
115#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
116#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
119#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -0600120#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jin Zhengxiongfcb28e72006-07-13 10:35:10 -0500121#define CONFIG_VERY_BIG_RAM
Jon Loeligerdebb7352006-04-26 17:58:56 -0500122
Kumar Gala6a8e5692008-08-26 15:01:35 -0500123#define CONFIG_NUM_DDR_CONTROLLERS 2
124#define CONFIG_DIMM_SLOTS_PER_CTLR 2
125#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500126
Kumar Gala6a8e5692008-08-26 15:01:35 -0500127/*
128 * I2C addresses of SPD EEPROMs
129 */
130#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
131#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
132#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
133#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500134
Jon Loeligerdebb7352006-04-26 17:58:56 -0500135
Kumar Gala6a8e5692008-08-26 15:01:35 -0500136/*
137 * These are used when DDR doesn't use SPD.
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
140#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
141#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
142#define CONFIG_SYS_DDR_TIMING_3 0x00000000
143#define CONFIG_SYS_DDR_TIMING_0 0x00260802
144#define CONFIG_SYS_DDR_TIMING_1 0x39357322
145#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
146#define CONFIG_SYS_DDR_MODE_1 0x00480432
147#define CONFIG_SYS_DDR_MODE_2 0x00000000
148#define CONFIG_SYS_DDR_INTERVAL 0x06090100
149#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
150#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
151#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
152#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
153#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
154#define CONFIG_SYS_DDR_CONTROL2 0x04400000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500155
Jon Loeligerad8f8682008-01-15 13:42:41 -0600156#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200158#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
160#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500161
Becky Brucec759a012008-11-06 17:36:04 -0600162#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
Becky Bruce1605cc92011-10-03 19:10:51 -0500163#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
164#define CONFIG_SYS_FLASH_BASE_PHYS \
165 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
166 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600167
Becky Bruceb81b7732009-02-02 16:34:52 -0600168#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Jon Loeligerdebb7352006-04-26 17:58:56 -0500169
Becky Bruce3111d322008-11-06 17:37:35 -0600170#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
171 | 0x00001001) /* port size 16bit */
172#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500173
Becky Bruce3111d322008-11-06 17:37:35 -0600174#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
175 | 0x00001001) /* port size 16bit */
176#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500177
Becky Bruce3111d322008-11-06 17:37:35 -0600178#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
179 | 0x00000801) /* port size 8bit */
180#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500181
Becky Brucec759a012008-11-06 17:36:04 -0600182/*
183 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
184 * The PIXIS and CF by themselves aren't large enough to take up the 128k
185 * required for the smallest BAT mapping, so there's a 64k hole.
186 */
187#define CONFIG_SYS_LBC_BASE 0xffde0000
Becky Bruce1605cc92011-10-03 19:10:51 -0500188#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500189
Kim Phillips7608d752007-08-21 17:00:17 -0500190#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Becky Brucec759a012008-11-06 17:36:04 -0600191#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
Becky Bruce1605cc92011-10-03 19:10:51 -0500192#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
193#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
194 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Brucec759a012008-11-06 17:36:04 -0600195#define PIXIS_SIZE 0x00008000 /* 32k */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500196#define PIXIS_ID 0x0 /* Board ID at offset 0 */
197#define PIXIS_VER 0x1 /* Board version at offset 1 */
198#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
199#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
200#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
201#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
202#define PIXIS_VCTL 0x10 /* VELA Control Register */
203#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
204#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
205#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala9af9c6b2009-07-15 13:45:00 -0500206#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
207#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500208#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
209#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
210#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
211#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500213
Becky Bruceb5431562008-10-31 17:13:49 -0500214/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
Becky Brucec759a012008-11-06 17:36:04 -0600215#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
Becky Bruce3111d322008-11-06 17:37:35 -0600216#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
Becky Bruceb5431562008-10-31 17:13:49 -0500217
Becky Bruce170deac2008-11-05 14:55:32 -0600218#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#undef CONFIG_SYS_FLASH_CHECKSUM
222#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
223#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200224#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600225#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500226
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200227#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_FLASH_CFI
229#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
232#define CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500233#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#undef CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500235#endif
236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#if defined(CONFIG_SYS_RAMBOOT)
Jin Zhengxiong-R64188fa7db9c2006-06-27 18:11:54 +0800238#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeligerdebb7352006-04-26 17:58:56 -0500240#endif
241
242#undef CONFIG_CLOCKS_IN_MHZ
243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_INIT_RAM_LOCK 1
245#ifndef CONFIG_SYS_INIT_RAM_LOCK
246#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500247#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500249#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200250#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500251
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200252#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerdebb7352006-04-26 17:58:56 -0500254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
256#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500257
258/* Serial Port */
259#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_NS16550
261#define CONFIG_SYS_NS16550_SERIAL
262#define CONFIG_SYS_NS16550_REG_SIZE 1
263#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerdebb7352006-04-26 17:58:56 -0500266 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
269#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500270
271/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_HUSH_PARSER
Jon Loeligerdebb7352006-04-26 17:58:56 -0500273
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500274/*
275 * Pass open firmware flat tree to kernel
276 */
Jon Loeligerea9f7392007-11-28 14:47:18 -0600277#define CONFIG_OF_LIBFDT 1
278#define CONFIG_OF_BOARD_SETUP 1
279#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500280
Jon Loeliger586d1d52006-05-19 13:22:44 -0500281/*
282 * I2C
283 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200284#define CONFIG_SYS_I2C
285#define CONFIG_SYS_I2C_FSL
286#define CONFIG_SYS_FSL_I2C_SPEED 400000
287#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
288#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
289#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jon Loeligerdebb7352006-04-26 17:58:56 -0500290
Jon Loeliger586d1d52006-05-19 13:22:44 -0500291/*
292 * RapidIO MMU
293 */
Kumar Gala1b77ca82011-01-04 17:45:13 -0600294#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
Becky Bruce3111d322008-11-06 17:37:35 -0600295#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -0500296#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
297#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600298#else
Becky Bruce1605cc92011-10-03 19:10:51 -0500299#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
300#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600301#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500302#define CONFIG_SYS_SRIO1_MEM_PHYS \
303 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
304 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600305#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500306
307/*
308 * General PCI
309 * Addresses are mapped 1-1.
310 */
Becky Bruce49f46f32009-02-03 18:10:53 -0600311
Kumar Gala64e55d52010-12-17 10:47:36 -0600312#define CONFIG_SYS_PCIE1_NAME "ULI"
Kumar Gala46f3e382010-07-09 00:02:34 -0500313#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Becky Bruce3111d322008-11-06 17:37:35 -0600314#ifdef CONFIG_PHYS_64BIT
Kumar Gala46f3e382010-07-09 00:02:34 -0500315#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Becky Bruce1605cc92011-10-03 19:10:51 -0500316#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
317#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600318#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500319#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
Becky Bruce1605cc92011-10-03 19:10:51 -0500320#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
321#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600322#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500323#define CONFIG_SYS_PCIE1_MEM_PHYS \
324 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
325 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500326#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
327#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
328#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
Becky Bruce1605cc92011-10-03 19:10:51 -0500329#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
330#define CONFIG_SYS_PCIE1_IO_PHYS \
331 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
332 CONFIG_SYS_PHYS_ADDR_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500333#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500334
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600335#ifdef CONFIG_PHYS_64BIT
336/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500337 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600338 * This will increase the amount of PCI address space available for
339 * for mapping RAM.
340 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500341#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600342#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500343#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
344 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600345#endif
Kumar Gala46f3e382010-07-09 00:02:34 -0500346#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
347 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500348#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
349 + CONFIG_SYS_PCIE1_MEM_SIZE)
350#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
Kumar Gala46f3e382010-07-09 00:02:34 -0500351#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
352 + CONFIG_SYS_PCIE1_MEM_SIZE)
353#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
354#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
355#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
356 + CONFIG_SYS_PCIE1_IO_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500357#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
358 + CONFIG_SYS_PCIE1_IO_SIZE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500359#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
360 + CONFIG_SYS_PCIE1_IO_SIZE)
361#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500362
Jon Loeligerdebb7352006-04-26 17:58:56 -0500363#if defined(CONFIG_PCI)
364
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200365#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500366
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500368
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200369#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500370
371#define CONFIG_RTL8139
372
Jon Loeligerdebb7352006-04-26 17:58:56 -0500373#undef CONFIG_EEPRO100
374#undef CONFIG_TULIP
375
Zhang Weia81d1c02007-06-06 10:08:14 +0200376/************************************************************
377 * USB support
378 ************************************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200379#define CONFIG_PCI_OHCI 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200380#define CONFIG_USB_OHCI_NEW 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200381#define CONFIG_USB_KEYBOARD 1
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200382#define CONFIG_SYS_STDIO_DEREGISTER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_USB_EVENT_POLL 1
384#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
385#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
386#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200387
Jason Jin0f460a12007-07-13 12:14:58 +0800388/*PCIE video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500389#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800390
391/*PCI video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500392/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
Jason Jin0f460a12007-07-13 12:14:58 +0800393
394/* video */
395#define CONFIG_VIDEO
396
397#if defined(CONFIG_VIDEO)
398#define CONFIG_BIOSEMU
399#define CONFIG_CFB_CONSOLE
400#define CONFIG_VIDEO_SW_CURSOR
401#define CONFIG_VGA_AS_SINGLE_DEVICE
402#define CONFIG_ATI_RADEON_FB
403#define CONFIG_VIDEO_LOGO
404/*#define CONFIG_CONSOLE_CURSOR*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500405#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800406#endif
407
Jon Loeligerdebb7352006-04-26 17:58:56 -0500408#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500409
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800410#define CONFIG_DOS_PARTITION
411#define CONFIG_SCSI_AHCI
412
413#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500414#define CONFIG_LIBATA
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800415#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
417#define CONFIG_SYS_SCSI_MAX_LUN 1
418#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
419#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800420#endif
421
Jon Loeligerdebb7352006-04-26 17:58:56 -0500422#endif /* CONFIG_PCI */
423
Jon Loeligerdebb7352006-04-26 17:58:56 -0500424#if defined(CONFIG_TSEC_ENET)
425
Jon Loeligerdebb7352006-04-26 17:58:56 -0500426#define CONFIG_MII 1 /* MII PHY management */
427
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200428#define CONFIG_TSEC1 1
429#define CONFIG_TSEC1_NAME "eTSEC1"
430#define CONFIG_TSEC2 1
431#define CONFIG_TSEC2_NAME "eTSEC2"
432#define CONFIG_TSEC3 1
433#define CONFIG_TSEC3_NAME "eTSEC3"
434#define CONFIG_TSEC4 1
435#define CONFIG_TSEC4_NAME "eTSEC4"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500436
Jon Loeligerdebb7352006-04-26 17:58:56 -0500437#define TSEC1_PHY_ADDR 0
438#define TSEC2_PHY_ADDR 1
439#define TSEC3_PHY_ADDR 2
440#define TSEC4_PHY_ADDR 3
441#define TSEC1_PHYIDX 0
442#define TSEC2_PHYIDX 0
443#define TSEC3_PHYIDX 0
444#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500445#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
446#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
447#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
448#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500449
450#define CONFIG_ETHPRIME "eTSEC1"
451
452#endif /* CONFIG_TSEC_ENET */
453
Becky Bruce1605cc92011-10-03 19:10:51 -0500454
Becky Bruce3111d322008-11-06 17:37:35 -0600455#ifdef CONFIG_PHYS_64BIT
Becky Bruce3111d322008-11-06 17:37:35 -0600456#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
457#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
458
Becky Bruce1605cc92011-10-03 19:10:51 -0500459/* Put physical address into the BAT format */
460#define BAT_PHYS_ADDR(low, high) \
461 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
462/* Convert high/low pairs to actual 64-bit value */
463#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
464#else
465/* 32-bit systems just ignore the "high" bits */
466#define BAT_PHYS_ADDR(low, high) (low)
467#define PAIRED_PHYS_TO_PHYS(low, high) (low)
468#endif
469
Jon Loeliger586d1d52006-05-19 13:22:44 -0500470/*
Becky Brucec759a012008-11-06 17:36:04 -0600471 * BAT0 DDR
Jon Loeligerdebb7352006-04-26 17:58:56 -0500472 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Timur Tabi9ff32d82010-03-29 12:51:07 -0500474#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500475
Jon Loeliger586d1d52006-05-19 13:22:44 -0500476/*
Becky Brucec759a012008-11-06 17:36:04 -0600477 * BAT1 LBC (PIXIS/CF)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500478 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500479#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
480 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600481 | BATL_PP_RW | BATL_CACHEINHIBIT | \
482 BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600483#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
484 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500485#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
486 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600487 | BATL_PP_RW | BATL_MEMCOHERENCE)
Becky Brucec759a012008-11-06 17:36:04 -0600488#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500489
490/* if CONFIG_PCI:
Kumar Gala46f3e382010-07-09 00:02:34 -0500491 * BAT2 PCIE1 and PCIE1 MEM
Becky Bruceaf5d1002008-10-31 17:14:14 -0500492 * if CONFIG_RIO
Becky Brucec759a012008-11-06 17:36:04 -0600493 * BAT2 Rapidio Memory
Jon Loeligerdebb7352006-04-26 17:58:56 -0500494 */
Becky Bruceaf5d1002008-10-31 17:14:14 -0500495#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000496#define CONFIG_PCI_INDIRECT_BRIDGE
Becky Bruce1605cc92011-10-03 19:10:51 -0500497#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
498 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600499 | BATL_PP_RW | BATL_CACHEINHIBIT \
500 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500501#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
Becky Bruceaf5d1002008-10-31 17:14:14 -0500502 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500503#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
504 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600505 | BATL_PP_RW | BATL_CACHEINHIBIT)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500506#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
507#else /* CONFIG_RIO */
Becky Bruce1605cc92011-10-03 19:10:51 -0500508#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
509 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600510 | BATL_PP_RW | BATL_CACHEINHIBIT | \
511 BATL_GUARDEDSTORAGE)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600512#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
Becky Bruce3111d322008-11-06 17:37:35 -0600513 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500514#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
515 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600516 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500518#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500519
Jon Loeliger586d1d52006-05-19 13:22:44 -0500520/*
Becky Brucec759a012008-11-06 17:36:04 -0600521 * BAT3 CCSR Space
Jon Loeligerdebb7352006-04-26 17:58:56 -0500522 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500523#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
524 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600525 | BATL_PP_RW | BATL_CACHEINHIBIT \
526 | BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600527#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
528 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500529#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
530 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600531 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500533
Becky Bruce3111d322008-11-06 17:37:35 -0600534#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
535#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
536 | BATL_PP_RW | BATL_CACHEINHIBIT \
537 | BATL_GUARDEDSTORAGE)
538#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
539 | BATU_BL_1M | BATU_VS | BATU_VP)
540#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
541 | BATL_PP_RW | BATL_CACHEINHIBIT)
542#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
543#endif
544
Jon Loeliger586d1d52006-05-19 13:22:44 -0500545/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500546 * BAT4 PCIE1_IO and PCIE2_IO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500547 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500548#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
549 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600550 | BATL_PP_RW | BATL_CACHEINHIBIT \
551 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500552#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
Becky Brucec759a012008-11-06 17:36:04 -0600553 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500554#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
555 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600556 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500558
Jon Loeliger586d1d52006-05-19 13:22:44 -0500559/*
Becky Brucec759a012008-11-06 17:36:04 -0600560 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500561 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
563#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
564#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
565#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500566
Jon Loeliger586d1d52006-05-19 13:22:44 -0500567/*
Becky Brucec759a012008-11-06 17:36:04 -0600568 * BAT6 FLASH
Jon Loeligerdebb7352006-04-26 17:58:56 -0500569 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500570#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
571 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600572 | BATL_PP_RW | BATL_CACHEINHIBIT \
573 | BATL_GUARDEDSTORAGE)
Becky Bruce170deac2008-11-05 14:55:32 -0600574#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
575 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500576#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
577 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600578 | BATL_PP_RW | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500580
Becky Brucebf9a8c32008-11-05 14:55:35 -0600581/* Map the last 1M of flash where we're running from reset */
582#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
583 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200584#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600585#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
586 | BATL_MEMCOHERENCE)
587#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
588
Becky Brucec759a012008-11-06 17:36:04 -0600589/*
590 * BAT7 FREE - used later for tmp mappings
591 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200592#define CONFIG_SYS_DBAT7L 0x00000000
593#define CONFIG_SYS_DBAT7U 0x00000000
594#define CONFIG_SYS_IBAT7L 0x00000000
595#define CONFIG_SYS_IBAT7U 0x00000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500596
Jon Loeligerdebb7352006-04-26 17:58:56 -0500597/*
598 * Environment
599 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200601 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200603 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500604#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200605 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200606 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500607#endif
Becky Bruce0f2d6602008-11-05 14:55:31 -0600608#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500609
610#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200611#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500612
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500613
614/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500615 * BOOTP options
616 */
617#define CONFIG_BOOTP_BOOTFILESIZE
618#define CONFIG_BOOTP_BOOTPATH
619#define CONFIG_BOOTP_GATEWAY
620#define CONFIG_BOOTP_HOSTNAME
621
622
623/*
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500624 * Command line configuration.
625 */
626#include <config_cmd_default.h>
627
628#define CONFIG_CMD_PING
629#define CONFIG_CMD_I2C
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600630#define CONFIG_CMD_REGINFO
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500631
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200632#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500633 #undef CONFIG_CMD_SAVEENV
Jon Loeligerdebb7352006-04-26 17:58:56 -0500634#endif
635
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500636#if defined(CONFIG_PCI)
637 #define CONFIG_CMD_PCI
638 #define CONFIG_CMD_SCSI
639 #define CONFIG_CMD_EXT2
Zhang Weibbf47962007-10-25 17:30:04 +0800640 #define CONFIG_CMD_USB
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500641#endif
642
Jon Loeligerdebb7352006-04-26 17:58:56 -0500643
644#undef CONFIG_WATCHDOG /* watchdog disabled */
645
646/*
647 * Miscellaneous configurable options
648 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200649#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200650#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200651#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500652
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500653#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200654 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500655#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200656 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500657#endif
658
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200659#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
660#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
661#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500662
663/*
664 * For booting Linux, the board info and command line data
665 * have to be in the first 8 MB of memory, since this is
666 * the maximum mapped by the Linux kernel during initialization.
667 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200668#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500669
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500670#if defined(CONFIG_CMD_KGDB)
671 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500672#endif
673
Jon Loeligerdebb7352006-04-26 17:58:56 -0500674/*
675 * Environment Configuration
676 */
677
678/* The mac addresses for all ethernet interface */
679#if defined(CONFIG_TSEC_ENET)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200680#define CONFIG_ETHADDR 00:E0:0C:00:00:01
Jon Loeligerdebb7352006-04-26 17:58:56 -0500681#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
682#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
683#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
684#endif
685
Andy Fleming10327dc2007-08-16 16:35:02 -0500686#define CONFIG_HAS_ETH0 1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500687#define CONFIG_HAS_ETH1 1
688#define CONFIG_HAS_ETH2 1
689#define CONFIG_HAS_ETH3 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500690
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500691#define CONFIG_IPADDR 192.168.1.100
Jon Loeligerdebb7352006-04-26 17:58:56 -0500692
693#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000694#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000695#define CONFIG_BOOTFILE "uImage"
Ed Swarthout32922cd2007-06-05 12:30:52 -0500696#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500697
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500698#define CONFIG_SERVERIP 192.168.1.1
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500699#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500700#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500701
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500702/* default location for tftp and bootm */
703#define CONFIG_LOADADDR 1000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500704
705#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200706#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500707
708#define CONFIG_BAUDRATE 115200
709
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200710#define CONFIG_EXTRA_ENV_SETTINGS \
711 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200712 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200713 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200714 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
715 " +$filesize; " \
716 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
717 " +$filesize; " \
718 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
719 " $filesize; " \
720 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
721 " +$filesize; " \
722 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
723 " $filesize\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200724 "consoledev=ttyS0\0" \
725 "ramdiskaddr=2000000\0" \
726 "ramdiskfile=your.ramdisk.u-boot\0" \
727 "fdtaddr=c00000\0" \
728 "fdtfile=mpc8641_hpcn.dtb\0" \
Becky Bruce3111d322008-11-06 17:37:35 -0600729 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
730 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200731 "maxcpus=2"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500732
733
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200734#define CONFIG_NFSBOOTCOMMAND \
735 "setenv bootargs root=/dev/nfs rw " \
736 "nfsroot=$serverip:$rootpath " \
737 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
738 "console=$consoledev,$baudrate $othbootargs;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr - $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500742
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200743#define CONFIG_RAMBOOTCOMMAND \
744 "setenv bootargs root=/dev/ram rw " \
745 "console=$consoledev,$baudrate $othbootargs;" \
746 "tftp $ramdiskaddr $ramdiskfile;" \
747 "tftp $loadaddr $bootfile;" \
748 "tftp $fdtaddr $fdtfile;" \
749 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500750
751#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
752
753#endif /* __CONFIG_H */