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Wolfgang Denk72a087e2006-10-24 14:27:35 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk72a087e2006-10-24 14:27:35 +02005 */
6#include <common.h>
7#include <command.h>
8
9#include <asm/io.h>
10#include <asm/sections.h>
11#include <asm/sysreg.h>
12
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010013#include <asm/arch/clk.h>
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000014#include <asm/arch/hardware.h>
Wolfgang Denk72a087e2006-10-24 14:27:35 +020015
16#include "hsmc3.h"
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010017
18/* Sanity checks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020019#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \
20 || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \
21 || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010022# error Constraint fCPU >= fHSB >= fPB{A,B} violated
23#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1))
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010025# error Invalid PLL multiplier and/or divider
26#endif
Wolfgang Denk72a087e2006-10-24 14:27:35 +020027
28DECLARE_GLOBAL_DATA_PTR;
29
30int cpu_init(void)
31{
Wolfgang Denk72a087e2006-10-24 14:27:35 +020032 extern void _evba(void);
Wolfgang Denk72a087e2006-10-24 14:27:35 +020033
Simon Glass3d0f8c82012-12-13 20:49:10 +000034 gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ;
Wolfgang Denk72a087e2006-10-24 14:27:35 +020035
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010036 /* TODO: Move somewhere else, but needs to be run before we
37 * increase the clock frequency. */
38 hsmc3_writel(MODE0, 0x00031103);
39 hsmc3_writel(CYCLE0, 0x000c000d);
40 hsmc3_writel(PULSE0, 0x0b0a0906);
41 hsmc3_writel(SETUP0, 0x00010002);
Wolfgang Denk72a087e2006-10-24 14:27:35 +020042
Haavard Skinnemoen3ace2522008-05-02 15:21:40 +020043 clk_init();
Wolfgang Denk72a087e2006-10-24 14:27:35 +020044
Haavard Skinnemoen3ace2522008-05-02 15:21:40 +020045 /* Update the CPU speed according to the PLL configuration */
Simon Glass3d0f8c82012-12-13 20:49:10 +000046 gd->arch.cpu_hz = get_cpu_clk_rate();
Haavard Skinnemoen3ace2522008-05-02 15:21:40 +020047
48 /* Set up the exception handler table and enable exceptions */
Wolfgang Denk72a087e2006-10-24 14:27:35 +020049 sysreg_write(EVBA, (unsigned long)&_evba);
50 asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
Wolfgang Denk72a087e2006-10-24 14:27:35 +020051
Wolfgang Denk72a087e2006-10-24 14:27:35 +020052 return 0;
53}
54
55void prepare_to_boot(void)
56{
57 /* Flush both caches and the write buffer */
58 asm volatile("cache %0[4], 010\n\t"
59 "cache %0[0], 000\n\t"
60 "sync 0" : : "r"(0) : "memory");
61}
62
Wolfgang Denk54841ab2010-06-28 22:00:46 +020063int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Wolfgang Denk72a087e2006-10-24 14:27:35 +020064{
65 /* This will reset the CPU core, caches, MMU and all internal busses */
66 __builtin_mtdr(8, 1 << 13); /* set DC:DBE */
67 __builtin_mtdr(8, 1 << 30); /* set DC:RES */
68
69 /* Flush the pipeline before we declare it a failure */
70 asm volatile("sub pc, pc, -4");
71
72 return -1;
73}