Blame - arch/arm/mach-socfpga/Kconfig - platform/external/u-boot

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Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Simon Glass	77d2f7f	2016-09-12 23:18:41 -0600	[diff] [blame]	3	config SPL_LIBCOMMON_SUPPORT
				4	default y
				5
Simon Glass	1646eba	2016-09-12 23:18:42 -0600	[diff] [blame]	6	config SPL_LIBDISK_SUPPORT
				7	default y
				8
Simon Glass	cc4288e	2016-09-12 23:18:43 -0600	[diff] [blame]	9	config SPL_LIBGENERIC_SUPPORT
				10	default y
				11
Simon Glass	1fdf7c6	2016-09-12 23:18:44 -0600	[diff] [blame]	12	config SPL_MMC_SUPPORT
				13	default y if DM_MMC
				14
Simon Glass	d6b9bd8	2016-09-12 23:18:48 -0600	[diff] [blame]	15	config SPL_NAND_SUPPORT
				16	default y if SPL_NAND_DENALI
				17
Simon Glass	e00f76c	2016-09-12 23:18:56 -0600	[diff] [blame]	18	config SPL_SERIAL_SUPPORT
				19	default y
				20
Simon Glass	e404ade	2016-09-12 23:18:57 -0600	[diff] [blame^]	21	config SPL_SPI_FLASH_SUPPORT
				22	default y if DM_SPI
				23
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	24	config TARGET_SOCFPGA_ARRIA5
				25	bool
Dinh Nguyen	ed77aeb	2015-12-02 13:31:25 -0600	[diff] [blame]	26	select TARGET_SOCFPGA_GEN5
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	27
				28	config TARGET_SOCFPGA_CYCLONE5
				29	bool
Dinh Nguyen	ed77aeb	2015-12-02 13:31:25 -0600	[diff] [blame]	30	select TARGET_SOCFPGA_GEN5
				31
				32	config TARGET_SOCFPGA_GEN5
				33	bool
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	34
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	35	choice
				36	prompt "Altera SOCFPGA board select"
Joe Hershberger	a26cd04	2015-05-12 14:46:23 -0500	[diff] [blame]	37	optional
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	38
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	39	config TARGET_SOCFPGA_ARRIA5_SOCDK
				40	bool "Altera SOCFPGA SoCDK (Arria V)"
				41	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	42
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	43	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				44	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				45	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	46
Marek Vasut	d88995a	2015-08-03 01:37:28 +0200	[diff] [blame]	47	config TARGET_SOCFPGA_DENX_MCVEVK
				48	bool "DENX MCVEVK (Cyclone V)"
				49	select TARGET_SOCFPGA_CYCLONE5
				50
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	51	config TARGET_SOCFPGA_EBV_SOCRATES
				52	bool "EBV SoCrates (Cyclone V)"
				53	select TARGET_SOCFPGA_CYCLONE5
				54
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	55	config TARGET_SOCFPGA_IS1
				56	bool "IS1 (Cyclone V)"
				57	select TARGET_SOCFPGA_CYCLONE5
				58
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	59	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				60	bool "samtec VIN\|ING FPGA (Cyclone V)"
				61	select TARGET_SOCFPGA_CYCLONE5
				62
Marek Vasut	cf0a8da	2016-06-08 02:57:05 +0200	[diff] [blame]	63	config TARGET_SOCFPGA_SR1500
				64	bool "SR1500 (Cyclone V)"
				65	select TARGET_SOCFPGA_CYCLONE5
				66
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	67	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				68	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				69	select TARGET_SOCFPGA_CYCLONE5
				70
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	71	config TARGET_SOCFPGA_TERASIC_SOCKIT
				72	bool "Terasic SoCkit (Cyclone V)"
				73	select TARGET_SOCFPGA_CYCLONE5
				74
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	75	endchoice
				76
				77	config SYS_BOARD
Marek Vasut	f089240	2015-08-10 21:24:53 +0200	[diff] [blame]	78	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
				79	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	80	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	81	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	d88995a	2015-08-03 01:37:28 +0200	[diff] [blame]	82	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	83	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	84	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	ae9996c	2015-11-18 11:06:09 +0100	[diff] [blame]	85	default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	86	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	87
				88	config SYS_VENDOR
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	89	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
				90	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	d88995a	2015-08-03 01:37:28 +0200	[diff] [blame]	91	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	92	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	93	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	94	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	95	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	96
				97	config SYS_SOC
				98	default "socfpga"
				99
				100	config SYS_CONFIG_NAME
Dinh Nguyen	3cbc7b8	2015-09-22 17:01:32 -0500	[diff] [blame]	101	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
				102	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	103	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	104	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	d88995a	2015-08-03 01:37:28 +0200	[diff] [blame]	105	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	106	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	107	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	ae9996c	2015-11-18 11:06:09 +0100	[diff] [blame]	108	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	109	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	110
				111	endif