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wdenk2d24a3a2004-06-09 21:50:45 +00001/*
2 * include/configs/mx1ads.h
wdenk49822e22004-06-19 21:19:10 +00003 *
wdenk2d24a3a2004-06-09 21:50:45 +00004 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
10 * This is the Configuration setting for Motorola MX1ADS board
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk281e00a2004-08-01 22:48:16 +000019 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk2d24a3a2004-06-09 21:50:45 +000020 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
wdenk2d24a3a2004-06-09 21:50:45 +000028#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
wdenk2d24a3a2004-06-09 21:50:45 +000032 * High Level Configuration Options
33 * (easy to change)
34 */
35#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
wdenk281e00a2004-08-01 22:48:16 +000036#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
37#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39
40/*
41 * Select serial console configuration
42 */
Jean-Christophe PLAGNIOL-VILLARDd3e55d02009-03-30 18:58:38 +020043#define CONFIG_IMX_SERIAL
wdenk281e00a2004-08-01 22:48:16 +000044#define CONFIG_IMX_SERIAL1 /* internal uart 1 */
45/* #define _CONFIG_UART2 */ /* internal uart 2 */
46/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
wdenk2d24a3a2004-06-09 21:50:45 +000047
wdenk49822e22004-06-19 21:19:10 +000048#define BOARD_LATE_INIT 1
wdenk2d24a3a2004-06-09 21:50:45 +000049#define USE_920T_MMU 1
wdenk2d24a3a2004-06-09 21:50:45 +000050
wdenk49822e22004-06-19 21:19:10 +000051#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
53#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
54#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
wdenk49822e22004-06-19 21:19:10 +000055#endif
wdenk2d24a3a2004-06-09 21:50:45 +000056
57/*
58 * Size of malloc() pool
59 */
60
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk281e00a2004-08-01 22:48:16 +000062
63
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk2d24a3a2004-06-09 21:50:45 +000065
66/*
67 * CS8900 Ethernet drivers
68 */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070069#define CONFIG_NET_MULTI
70#define CONFIG_CS8900 /* we have a CS8900 on-board */
71#define CONFIG_CS8900_BASE 0x15000300
72#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
wdenk2d24a3a2004-06-09 21:50:45 +000073
74/*
75 * select serial console configuration
76 */
77
wdenk281e00a2004-08-01 22:48:16 +000078/* #define CONFIG_UART1 */
wdenk2d24a3a2004-06-09 21:50:45 +000079/* #define CONFIG_UART2 1 */
80
81#define CONFIG_BAUDRATE 115200
82
wdenk2d24a3a2004-06-09 21:50:45 +000083
Jon Loeliger5dc11a52007-07-04 22:33:01 -050084/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050085 * BOOTP options
86 */
87#define CONFIG_BOOTP_BOOTFILESIZE
88#define CONFIG_BOOTP_BOOTPATH
89#define CONFIG_BOOTP_GATEWAY
90#define CONFIG_BOOTP_HOSTNAME
91
92
93/*
Jon Loeliger5dc11a52007-07-04 22:33:01 -050094 * Command line configuration.
95 */
96#include <config_cmd_default.h>
wdenk2d24a3a2004-06-09 21:50:45 +000097
Jon Loeliger5dc11a52007-07-04 22:33:01 -050098#define CONFIG_CMD_CACHE
99#define CONFIG_CMD_REGINFO
100#define CONFIG_CMD_ELF
101
wdenk2d24a3a2004-06-09 21:50:45 +0000102
103#define CONFIG_BOOTDELAY 3
wdenk281e00a2004-08-01 22:48:16 +0000104#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
wdenk2d24a3a2004-06-09 21:50:45 +0000105#define CONFIG_BOOTFILE "mx1ads"
wdenk281e00a2004-08-01 22:48:16 +0000106#define CONFIG_BOOTCOMMAND "tftp; bootm"
wdenk2d24a3a2004-06-09 21:50:45 +0000107
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500108#if defined(CONFIG_CMD_KGDB)
wdenk2d24a3a2004-06-09 21:50:45 +0000109#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
110 /* what's this ? it's not used anywhere */
111#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
112#endif
113
114/*
115 * Miscellaneous configurable options
116 */
wdenk49822e22004-06-19 21:19:10 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_HUSH_PARSER 1
119#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk49822e22004-06-19 21:19:10 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk2d24a3a2004-06-09 21:50:45 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#ifdef CONFIG_SYS_HUSH_PARSER
124#define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
wdenk2d24a3a2004-06-09 21:50:45 +0000125#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
wdenk2d24a3a2004-06-09 21:50:45 +0000127#endif
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
wdenk2d24a3a2004-06-09 21:50:45 +0000131 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk2d24a3a2004-06-09 21:50:45 +0000134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */
136#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
wdenk2d24a3a2004-06-09 21:50:45 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */
139/*#define CONFIG_SYS_HZ 1000 */
140#define CONFIG_SYS_HZ 3686400
141#define CONFIG_SYS_CPUSPEED 0x141
wdenk2d24a3a2004-06-09 21:50:45 +0000142
143/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk2d24a3a2004-06-09 21:50:45 +0000145
146/*-----------------------------------------------------------------------
147 * Stack sizes
148 *
149 * The stack sizes are set up in start.S using the settings below
150 */
151#define CONFIG_STACKSIZE (128*1024) /* regular stack */
152#ifdef CONFIG_USE_IRQ
153#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
154#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
155#endif
156
157/*-----------------------------------------------------------------------
158 * Physical Memory Map
159 */
wdenk49822e22004-06-19 21:19:10 +0000160
wdenk281e00a2004-08-01 22:48:16 +0000161#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
162#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
163#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
wdenk2d24a3a2004-06-09 21:50:45 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
166#define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
wdenk281e00a2004-08-01 22:48:16 +0000167#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
wdenk2d24a3a2004-06-09 21:50:45 +0000168
169/*-----------------------------------------------------------------------
170 * FLASH and environment organization
171 */
172
wdenk2d24a3a2004-06-09 21:50:45 +0000173#define CONFIG_SYNCFLASH 1
174#define PHYS_FLASH_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_MAX_FLASH_SECT (16)
176#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000)
wdenk49822e22004-06-19 21:19:10 +0000177
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200178#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200179#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
180#define CONFIG_ENV_SECT_SIZE 0x100000
wdenk281e00a2004-08-01 22:48:16 +0000181
182/*-----------------------------------------------------------------------
183 * Enable passing ATAGS
184 */
185
186#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
187#define CONFIG_SETUP_MEMORY_TAGS 1
188
189#define CONFIG_SYS_CLK_FREQ 16780000
190#define CONFIG_SYSPLL_CLK_FREQ 16000000
191
wdenk2d24a3a2004-06-09 21:50:45 +0000192#endif /* __CONFIG_H */