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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk1df49e22002-09-17 21:37:55 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk1df49e22002-09-17 21:37:55 +00005 */
6
7#include <common.h>
Marek Vasut047a8002020-05-23 15:07:30 +02008#include <asm/io.h>
Marek Vasut5116aae2020-05-23 14:55:26 +02009#include <cpu_func.h>
wdenk1df49e22002-09-17 21:37:55 +000010#include <malloc.h>
Marek Vasut047a8002020-05-23 15:07:30 +020011#include <miiphy.h>
wdenk1df49e22002-09-17 21:37:55 +000012#include <net.h>
Ben Warren10efa022008-08-31 20:37:00 -070013#include <netdev.h>
wdenk1df49e22002-09-17 21:37:55 +000014#include <pci.h>
Simon Glassc05ed002020-05-10 11:40:11 -060015#include <linux/delay.h>
wdenk1df49e22002-09-17 21:37:55 +000016
Marek Vasutaba283d2020-05-23 12:49:16 +020017/* Ethernet chip registers. */
Marek Vasutf3878f52020-05-23 13:52:50 +020018#define SCB_STATUS 0 /* Rx/Command Unit Status *Word* */
19#define SCB_INT_ACK_BYTE 1 /* Rx/Command Unit STAT/ACK byte */
20#define SCB_CMD 2 /* Rx/Command Unit Command *Word* */
21#define SCB_INTR_CTL_BYTE 3 /* Rx/Command Unit Intr.Control Byte */
22#define SCB_POINTER 4 /* General purpose pointer. */
23#define SCB_PORT 8 /* Misc. commands and operands. */
24#define SCB_FLASH 12 /* Flash memory control. */
25#define SCB_EEPROM 14 /* EEPROM memory control. */
26#define SCB_CTRL_MDI 16 /* MDI interface control. */
27#define SCB_EARLY_RX 20 /* Early receive byte count. */
28#define SCB_GEN_CONTROL 28 /* 82559 General Control Register */
29#define SCB_GEN_STATUS 29 /* 82559 General Status register */
wdenk1df49e22002-09-17 21:37:55 +000030
Marek Vasutaba283d2020-05-23 12:49:16 +020031/* 82559 SCB status word defnitions */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020032#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
33#define SCB_STATUS_FR 0x4000 /* frame received */
34#define SCB_STATUS_CNA 0x2000 /* CU left active state */
35#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
36#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
37#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
38#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
wdenk1df49e22002-09-17 21:37:55 +000039
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020040#define SCB_INTACK_MASK 0xFD00 /* all the above */
wdenk1df49e22002-09-17 21:37:55 +000041
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020042#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
43#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
wdenk1df49e22002-09-17 21:37:55 +000044
Marek Vasutaba283d2020-05-23 12:49:16 +020045/* System control block commands */
wdenk1df49e22002-09-17 21:37:55 +000046/* CU Commands */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020047#define CU_NOP 0x0000
48#define CU_START 0x0010
49#define CU_RESUME 0x0020
50#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
51#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
52#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
53#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
wdenk1df49e22002-09-17 21:37:55 +000054
55/* RUC Commands */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020056#define RUC_NOP 0x0000
57#define RUC_START 0x0001
58#define RUC_RESUME 0x0002
59#define RUC_ABORT 0x0004
60#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
61#define RUC_RESUMENR 0x0007
wdenk1df49e22002-09-17 21:37:55 +000062
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020063#define CU_CMD_MASK 0x00f0
64#define RU_CMD_MASK 0x0007
wdenk1df49e22002-09-17 21:37:55 +000065
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020066#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
67#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
wdenk1df49e22002-09-17 21:37:55 +000068
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020069#define CU_STATUS_MASK 0x00C0
70#define RU_STATUS_MASK 0x003C
wdenk1df49e22002-09-17 21:37:55 +000071
Marek Vasutdb9f1812020-05-23 13:17:03 +020072#define RU_STATUS_IDLE (0 << 2)
73#define RU_STATUS_SUS (1 << 2)
74#define RU_STATUS_NORES (2 << 2)
75#define RU_STATUS_READY (4 << 2)
76#define RU_STATUS_NO_RBDS_SUS ((1 << 2) | (8 << 2))
77#define RU_STATUS_NO_RBDS_NORES ((2 << 2) | (8 << 2))
78#define RU_STATUS_NO_RBDS_READY ((4 << 2) | (8 << 2))
wdenk1df49e22002-09-17 21:37:55 +000079
Marek Vasutaba283d2020-05-23 12:49:16 +020080/* 82559 Port interface commands. */
wdenk1df49e22002-09-17 21:37:55 +000081#define I82559_RESET 0x00000000 /* Software reset */
82#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
83#define I82559_SELECTIVE_RESET 0x00000002
84#define I82559_DUMP 0x00000003
85#define I82559_DUMP_WAKEUP 0x00000007
86
Marek Vasutaba283d2020-05-23 12:49:16 +020087/* 82559 Eeprom interface. */
wdenk1df49e22002-09-17 21:37:55 +000088#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
89#define EE_CS 0x02 /* EEPROM chip select. */
90#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
91#define EE_WRITE_0 0x01
92#define EE_WRITE_1 0x05
93#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
94#define EE_ENB (0x4800 | EE_CS)
95#define EE_CMD_BITS 3
96#define EE_DATA_BITS 16
97
Marek Vasutaba283d2020-05-23 12:49:16 +020098/* The EEPROM commands include the alway-set leading bit. */
Marek Vasuta6c06ec2020-05-23 16:23:28 +020099#define EE_EWENB_CMD(addr_len) (4 << (addr_len))
100#define EE_WRITE_CMD(addr_len) (5 << (addr_len))
101#define EE_READ_CMD(addr_len) (6 << (addr_len))
102#define EE_ERASE_CMD(addr_len) (7 << (addr_len))
wdenk1df49e22002-09-17 21:37:55 +0000103
Marek Vasutaba283d2020-05-23 12:49:16 +0200104/* Receive frame descriptors. */
Marek Vasutf3878f52020-05-23 13:52:50 +0200105struct eepro100_rxfd {
Marek Vasutd47cf872020-05-23 15:02:47 +0200106 u16 status;
107 u16 control;
108 u32 link; /* struct eepro100_rxfd * */
109 u32 rx_buf_addr; /* void * */
110 u32 count;
wdenk1df49e22002-09-17 21:37:55 +0000111
Marek Vasutd47cf872020-05-23 15:02:47 +0200112 u8 data[PKTSIZE_ALIGN];
wdenk1df49e22002-09-17 21:37:55 +0000113};
114
115#define RFD_STATUS_C 0x8000 /* completion of received frame */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200116#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
wdenk1df49e22002-09-17 21:37:55 +0000117
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200118#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
119#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
120#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
121#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
wdenk1df49e22002-09-17 21:37:55 +0000122
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200123#define RFD_COUNT_MASK 0x3fff
124#define RFD_COUNT_F 0x4000
125#define RFD_COUNT_EOF 0x8000
wdenk1df49e22002-09-17 21:37:55 +0000126
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200127#define RFD_RX_CRC 0x0800 /* crc error */
128#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
129#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
130#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
131#define RFD_RX_SHORT 0x0080 /* short frame error */
132#define RFD_RX_LENGTH 0x0020
133#define RFD_RX_ERROR 0x0010 /* receive error */
134#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
135#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
136#define RFD_RX_TCO 0x0001 /* TCO indication */
wdenk1df49e22002-09-17 21:37:55 +0000137
Marek Vasutaba283d2020-05-23 12:49:16 +0200138/* Transmit frame descriptors */
Marek Vasutd47cf872020-05-23 15:02:47 +0200139struct eepro100_txfd { /* Transmit frame descriptor set. */
140 u16 status;
141 u16 command;
142 u32 link; /* void * */
143 u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
144 s32 count;
wdenk1df49e22002-09-17 21:37:55 +0000145
Marek Vasutd47cf872020-05-23 15:02:47 +0200146 u32 tx_buf_addr0; /* void *, frame to be transmitted. */
147 s32 tx_buf_size0; /* Length of Tx frame. */
148 u32 tx_buf_addr1; /* void *, frame to be transmitted. */
149 s32 tx_buf_size1; /* Length of Tx frame. */
wdenk1df49e22002-09-17 21:37:55 +0000150};
151
Marek Vasutf3878f52020-05-23 13:52:50 +0200152#define TXCB_CMD_TRANSMIT 0x0004 /* transmit command */
153#define TXCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
154#define TXCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
155#define TXCB_CMD_I 0x2000 /* generate interrupt on completion */
156#define TXCB_CMD_S 0x4000 /* suspend on completion */
157#define TXCB_CMD_EL 0x8000 /* last command block in CBL */
wdenk1df49e22002-09-17 21:37:55 +0000158
Marek Vasutf3878f52020-05-23 13:52:50 +0200159#define TXCB_COUNT_MASK 0x3fff
160#define TXCB_COUNT_EOF 0x8000
wdenk1df49e22002-09-17 21:37:55 +0000161
Marek Vasutaba283d2020-05-23 12:49:16 +0200162/* The Speedo3 Rx and Tx frame/buffer descriptors. */
Marek Vasutd47cf872020-05-23 15:02:47 +0200163struct descriptor { /* A generic descriptor. */
164 u16 status;
165 u16 command;
166 u32 link; /* struct descriptor * */
wdenk1df49e22002-09-17 21:37:55 +0000167
168 unsigned char params[0];
169};
170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CMD_EL 0x8000
172#define CONFIG_SYS_CMD_SUSPEND 0x4000
173#define CONFIG_SYS_CMD_INT 0x2000
174#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
175#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
wdenk1df49e22002-09-17 21:37:55 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_STATUS_C 0x8000
178#define CONFIG_SYS_STATUS_OK 0x2000
wdenk1df49e22002-09-17 21:37:55 +0000179
Marek Vasutaba283d2020-05-23 12:49:16 +0200180/* Misc. */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200181#define NUM_RX_DESC PKTBUFSRX
Marek Vasutaba283d2020-05-23 12:49:16 +0200182#define NUM_TX_DESC 1 /* Number of TX descriptors */
wdenk1df49e22002-09-17 21:37:55 +0000183
184#define TOUT_LOOP 1000000
185
wdenk1df49e22002-09-17 21:37:55 +0000186/*
187 * The parameters for a CmdConfigure operation.
188 * There are so many options that it would be difficult to document
189 * each bit. We mostly use the default or recommended settings.
190 */
wdenk1df49e22002-09-17 21:37:55 +0000191static const char i82558_config_cmd[] = {
192 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
193 0, 0x2E, 0, 0x60, 0x08, 0x88,
194 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
195 0x31, 0x05,
196};
197
Marek Vasutbd159c62020-05-23 16:49:07 +0200198struct eepro100_priv {
Marek Vasutfb8307e2020-05-23 17:13:26 +0200199 /* RX descriptor ring */
200 struct eepro100_rxfd rx_ring[NUM_RX_DESC];
201 /* TX descriptor ring */
202 struct eepro100_txfd tx_ring[NUM_TX_DESC];
203 /* RX descriptor ring pointer */
204 int rx_next;
205 /* TX descriptor ring pointer */
206 int tx_next;
207 int tx_threshold;
Marek Vasutbd159c62020-05-23 16:49:07 +0200208 struct eth_device dev;
Marek Vasut389da972020-05-23 17:10:03 +0200209 pci_dev_t devno;
210 char *name;
211 void __iomem *iobase;
212 u8 *enetaddr;
Marek Vasutbd159c62020-05-23 16:49:07 +0200213};
214
Wolfgang Denk03b00402014-10-21 15:23:32 +0200215#if defined(CONFIG_E500)
Marek Vasutfa9e1212020-05-23 16:38:41 +0200216#define bus_to_phys(dev, a) (a)
217#define phys_to_bus(dev, a) (a)
wdenk42d1f032003-10-15 23:53:47 +0000218#else
Marek Vasutfa9e1212020-05-23 16:38:41 +0200219#define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a))
220#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
wdenk42d1f032003-10-15 23:53:47 +0000221#endif
wdenk1df49e22002-09-17 21:37:55 +0000222
Marek Vasut389da972020-05-23 17:10:03 +0200223static int INW(struct eepro100_priv *priv, u_long addr)
wdenk1df49e22002-09-17 21:37:55 +0000224{
Marek Vasut389da972020-05-23 17:10:03 +0200225 return le16_to_cpu(readw(addr + priv->iobase));
wdenk1df49e22002-09-17 21:37:55 +0000226}
227
Marek Vasut389da972020-05-23 17:10:03 +0200228static void OUTW(struct eepro100_priv *priv, int command, u_long addr)
wdenk1df49e22002-09-17 21:37:55 +0000229{
Marek Vasut389da972020-05-23 17:10:03 +0200230 writew(cpu_to_le16(command), addr + priv->iobase);
wdenk1df49e22002-09-17 21:37:55 +0000231}
232
Marek Vasut389da972020-05-23 17:10:03 +0200233static void OUTL(struct eepro100_priv *priv, int command, u_long addr)
wdenk1df49e22002-09-17 21:37:55 +0000234{
Marek Vasut389da972020-05-23 17:10:03 +0200235 writel(cpu_to_le32(command), addr + priv->iobase);
wdenk1df49e22002-09-17 21:37:55 +0000236}
237
Jon Loeliger07d38a12007-07-09 17:30:01 -0500238#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marek Vasut389da972020-05-23 17:10:03 +0200239static int INL(struct eepro100_priv *priv, u_long addr)
Wolfgang Denka9127332005-09-26 00:39:59 +0200240{
Marek Vasut389da972020-05-23 17:10:03 +0200241 return le32_to_cpu(readl(addr + priv->iobase));
Wolfgang Denka9127332005-09-26 00:39:59 +0200242}
243
Marek Vasut389da972020-05-23 17:10:03 +0200244static int get_phyreg(struct eepro100_priv *priv, unsigned char addr,
Marek Vasut773af832020-05-23 13:21:43 +0200245 unsigned char reg, unsigned short *value)
Wolfgang Denka9127332005-09-26 00:39:59 +0200246{
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200247 int timeout = 50;
Marek Vasut389da972020-05-23 17:10:03 +0200248 int cmd;
Wolfgang Denka9127332005-09-26 00:39:59 +0200249
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200250 /* read requested data */
251 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
Marek Vasut389da972020-05-23 17:10:03 +0200252 OUTL(priv, cmd, SCB_CTRL_MDI);
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200253
Wolfgang Denka9127332005-09-26 00:39:59 +0200254 do {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200255 udelay(1000);
Marek Vasut389da972020-05-23 17:10:03 +0200256 cmd = INL(priv, SCB_CTRL_MDI);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200257 } while (!(cmd & (1 << 28)) && (--timeout));
258
259 if (timeout == 0)
260 return -1;
Wolfgang Denka9127332005-09-26 00:39:59 +0200261
Marek Vasutdb9f1812020-05-23 13:17:03 +0200262 *value = (unsigned short)(cmd & 0xffff);
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200263
Wolfgang Denka9127332005-09-26 00:39:59 +0200264 return 0;
265}
266
Marek Vasut389da972020-05-23 17:10:03 +0200267static int set_phyreg(struct eepro100_priv *priv, unsigned char addr,
Marek Vasut773af832020-05-23 13:21:43 +0200268 unsigned char reg, unsigned short value)
Wolfgang Denka9127332005-09-26 00:39:59 +0200269{
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200270 int timeout = 50;
Marek Vasut389da972020-05-23 17:10:03 +0200271 int cmd;
Wolfgang Denka9127332005-09-26 00:39:59 +0200272
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200273 /* write requested data */
274 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
Marek Vasut389da972020-05-23 17:10:03 +0200275 OUTL(priv, cmd | value, SCB_CTRL_MDI);
Wolfgang Denka9127332005-09-26 00:39:59 +0200276
Marek Vasut389da972020-05-23 17:10:03 +0200277 while (!(INL(priv, SCB_CTRL_MDI) & (1 << 28)) && (--timeout))
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200278 udelay(1000);
279
280 if (timeout == 0)
281 return -1;
Wolfgang Denka9127332005-09-26 00:39:59 +0200282
283 return 0;
284}
Wolfgang Denka9127332005-09-26 00:39:59 +0200285
Marek Vasutaba283d2020-05-23 12:49:16 +0200286/*
287 * Check if given phyaddr is valid, i.e. there is a PHY connected.
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200288 * Do this by checking model value field from ID2 register.
289 */
Marek Vasut389da972020-05-23 17:10:03 +0200290static int verify_phyaddr(struct eepro100_priv *priv, unsigned char addr)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200291{
Marek Vasut389da972020-05-23 17:10:03 +0200292 unsigned short value, model;
293 int ret;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200294
295 /* read id2 register */
Marek Vasut389da972020-05-23 17:10:03 +0200296 ret = get_phyreg(priv, addr, MII_PHYSID2, &value);
297 if (ret) {
298 printf("%s: mii read timeout!\n", priv->name);
299 return ret;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200300 }
301
302 /* get model */
Marek Vasut389da972020-05-23 17:10:03 +0200303 model = (value >> 4) & 0x003f;
304 if (!model) {
305 printf("%s: no PHY at address %d\n", priv->name, addr);
306 return -EINVAL;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200307 }
308
Marek Vasut389da972020-05-23 17:10:03 +0200309 return 0;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200310}
311
Joe Hershberger5a49f172016-08-08 11:28:38 -0500312static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
313 int reg)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200314{
Marek Vasut39daab22020-05-23 17:55:50 +0200315 struct eepro100_priv *priv = bus->priv;
Joe Hershberger5a49f172016-08-08 11:28:38 -0500316 unsigned short value = 0;
Marek Vasut389da972020-05-23 17:10:03 +0200317 int ret;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200318
Marek Vasut389da972020-05-23 17:10:03 +0200319 ret = verify_phyaddr(priv, addr);
320 if (ret)
321 return ret;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200322
Marek Vasut389da972020-05-23 17:10:03 +0200323 ret = get_phyreg(priv, addr, reg, &value);
324 if (ret) {
Joe Hershberger5a49f172016-08-08 11:28:38 -0500325 printf("%s: mii read timeout!\n", bus->name);
Marek Vasut389da972020-05-23 17:10:03 +0200326 return ret;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200327 }
328
Joe Hershberger5a49f172016-08-08 11:28:38 -0500329 return value;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200330}
331
Joe Hershberger5a49f172016-08-08 11:28:38 -0500332static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
333 int reg, u16 value)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200334{
Marek Vasut39daab22020-05-23 17:55:50 +0200335 struct eepro100_priv *priv = bus->priv;
Marek Vasut389da972020-05-23 17:10:03 +0200336 int ret;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200337
Marek Vasut389da972020-05-23 17:10:03 +0200338 ret = verify_phyaddr(priv, addr);
339 if (ret)
340 return ret;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200341
Marek Vasut389da972020-05-23 17:10:03 +0200342 ret = set_phyreg(priv, addr, reg, value);
343 if (ret) {
Joe Hershberger5a49f172016-08-08 11:28:38 -0500344 printf("%s: mii write timeout!\n", bus->name);
Marek Vasut389da972020-05-23 17:10:03 +0200345 return ret;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200346 }
347
348 return 0;
349}
Jon Loeliger07d38a12007-07-09 17:30:01 -0500350#endif
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200351
Marek Vasut389da972020-05-23 17:10:03 +0200352static void init_rx_ring(struct eepro100_priv *priv)
Marek Vasut047a8002020-05-23 15:07:30 +0200353{
Marek Vasutfb8307e2020-05-23 17:13:26 +0200354 struct eepro100_rxfd *rx_ring = priv->rx_ring;
Marek Vasut047a8002020-05-23 15:07:30 +0200355 int i;
356
357 for (i = 0; i < NUM_RX_DESC; i++) {
358 rx_ring[i].status = 0;
359 rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
360 cpu_to_le16 (RFD_CONTROL_S) : 0;
361 rx_ring[i].link =
Marek Vasut389da972020-05-23 17:10:03 +0200362 cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutfa9e1212020-05-23 16:38:41 +0200363 (u32)&rx_ring[(i + 1) %
Marek Vasut047a8002020-05-23 15:07:30 +0200364 NUM_RX_DESC]));
365 rx_ring[i].rx_buf_addr = 0xffffffff;
366 rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
367 }
368
369 flush_dcache_range((unsigned long)rx_ring,
370 (unsigned long)rx_ring +
371 (sizeof(*rx_ring) * NUM_RX_DESC));
372
Marek Vasutfb8307e2020-05-23 17:13:26 +0200373 priv->rx_next = 0;
Marek Vasut047a8002020-05-23 15:07:30 +0200374}
375
Marek Vasut389da972020-05-23 17:10:03 +0200376static void purge_tx_ring(struct eepro100_priv *priv)
Marek Vasut047a8002020-05-23 15:07:30 +0200377{
Marek Vasutfb8307e2020-05-23 17:13:26 +0200378 struct eepro100_txfd *tx_ring = priv->tx_ring;
379
380 priv->tx_next = 0;
381 priv->tx_threshold = 0x01208000;
Marek Vasut047a8002020-05-23 15:07:30 +0200382 memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
383
384 flush_dcache_range((unsigned long)tx_ring,
385 (unsigned long)tx_ring +
386 (sizeof(*tx_ring) * NUM_TX_DESC));
387}
388
Marek Vasutaba283d2020-05-23 12:49:16 +0200389/* Wait for the chip get the command. */
Marek Vasut389da972020-05-23 17:10:03 +0200390static int wait_for_eepro100(struct eepro100_priv *priv)
wdenk1df49e22002-09-17 21:37:55 +0000391{
392 int i;
393
Marek Vasut389da972020-05-23 17:10:03 +0200394 for (i = 0; INW(priv, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
Marek Vasut9b12ff92020-05-23 13:20:14 +0200395 if (i >= TOUT_LOOP)
wdenk1df49e22002-09-17 21:37:55 +0000396 return 0;
wdenk1df49e22002-09-17 21:37:55 +0000397 }
398
399 return 1;
400}
401
Marek Vasut389da972020-05-23 17:10:03 +0200402static int eepro100_txcmd_send(struct eepro100_priv *priv,
Marek Vasut95655b92020-05-23 14:30:31 +0200403 struct eepro100_txfd *desc)
404{
405 u16 rstat;
406 int i = 0;
407
Marek Vasut5116aae2020-05-23 14:55:26 +0200408 flush_dcache_range((unsigned long)desc,
409 (unsigned long)desc + sizeof(*desc));
410
Marek Vasut389da972020-05-23 17:10:03 +0200411 if (!wait_for_eepro100(priv))
Marek Vasut95655b92020-05-23 14:30:31 +0200412 return -ETIMEDOUT;
413
Marek Vasut389da972020-05-23 17:10:03 +0200414 OUTL(priv, phys_to_bus(priv->devno, (u32)desc), SCB_POINTER);
415 OUTW(priv, SCB_M | CU_START, SCB_CMD);
Marek Vasut95655b92020-05-23 14:30:31 +0200416
417 while (true) {
Marek Vasut5116aae2020-05-23 14:55:26 +0200418 invalidate_dcache_range((unsigned long)desc,
419 (unsigned long)desc + sizeof(*desc));
Marek Vasut95655b92020-05-23 14:30:31 +0200420 rstat = le16_to_cpu(desc->status);
421 if (rstat & CONFIG_SYS_STATUS_C)
422 break;
423
424 if (i++ >= TOUT_LOOP) {
Marek Vasut389da972020-05-23 17:10:03 +0200425 printf("%s: Tx error buffer not ready\n", priv->name);
Marek Vasut95655b92020-05-23 14:30:31 +0200426 return -EINVAL;
427 }
428 }
429
Marek Vasut5116aae2020-05-23 14:55:26 +0200430 invalidate_dcache_range((unsigned long)desc,
431 (unsigned long)desc + sizeof(*desc));
Marek Vasut95655b92020-05-23 14:30:31 +0200432 rstat = le16_to_cpu(desc->status);
433
434 if (!(rstat & CONFIG_SYS_STATUS_OK)) {
435 printf("TX error status = 0x%08X\n", rstat);
436 return -EIO;
437 }
438
439 return 0;
440}
441
Marek Vasut047a8002020-05-23 15:07:30 +0200442/* SROM Read. */
Marek Vasut389da972020-05-23 17:10:03 +0200443static int read_eeprom(struct eepro100_priv *priv, int location, int addr_len)
Marek Vasut047a8002020-05-23 15:07:30 +0200444{
445 unsigned short retval = 0;
Marek Vasuta6c06ec2020-05-23 16:23:28 +0200446 int read_cmd = location | EE_READ_CMD(addr_len);
Marek Vasut047a8002020-05-23 15:07:30 +0200447 int i;
448
Marek Vasut389da972020-05-23 17:10:03 +0200449 OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
450 OUTW(priv, EE_ENB, SCB_EEPROM);
Marek Vasut047a8002020-05-23 15:07:30 +0200451
452 /* Shift the read command bits out. */
453 for (i = 12; i >= 0; i--) {
454 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
455
Marek Vasut389da972020-05-23 17:10:03 +0200456 OUTW(priv, EE_ENB | dataval, SCB_EEPROM);
Marek Vasut047a8002020-05-23 15:07:30 +0200457 udelay(1);
Marek Vasut389da972020-05-23 17:10:03 +0200458 OUTW(priv, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
Marek Vasut047a8002020-05-23 15:07:30 +0200459 udelay(1);
460 }
Marek Vasut389da972020-05-23 17:10:03 +0200461 OUTW(priv, EE_ENB, SCB_EEPROM);
Marek Vasut047a8002020-05-23 15:07:30 +0200462
463 for (i = 15; i >= 0; i--) {
Marek Vasut389da972020-05-23 17:10:03 +0200464 OUTW(priv, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
Marek Vasut047a8002020-05-23 15:07:30 +0200465 udelay(1);
466 retval = (retval << 1) |
Marek Vasut389da972020-05-23 17:10:03 +0200467 !!(INW(priv, SCB_EEPROM) & EE_DATA_READ);
468 OUTW(priv, EE_ENB, SCB_EEPROM);
Marek Vasut047a8002020-05-23 15:07:30 +0200469 udelay(1);
470 }
471
472 /* Terminate the EEPROM access. */
Marek Vasut389da972020-05-23 17:10:03 +0200473 OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
Marek Vasut047a8002020-05-23 15:07:30 +0200474 return retval;
475}
476
Marek Vasut66fed732020-05-23 16:20:25 +0200477#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marek Vasut389da972020-05-23 17:10:03 +0200478static int eepro100_initialize_mii(struct eepro100_priv *priv)
Marek Vasut66fed732020-05-23 16:20:25 +0200479{
480 /* register mii command access routines */
481 struct mii_dev *mdiodev;
482 int ret;
483
484 mdiodev = mdio_alloc();
485 if (!mdiodev)
486 return -ENOMEM;
487
Marek Vasut389da972020-05-23 17:10:03 +0200488 strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
Marek Vasut66fed732020-05-23 16:20:25 +0200489 mdiodev->read = eepro100_miiphy_read;
490 mdiodev->write = eepro100_miiphy_write;
Marek Vasut39daab22020-05-23 17:55:50 +0200491 mdiodev->priv = priv;
Marek Vasut66fed732020-05-23 16:20:25 +0200492
493 ret = mdio_register(mdiodev);
494 if (ret < 0) {
495 mdio_free(mdiodev);
496 return ret;
497 }
498
499 return 0;
500}
501#else
Marek Vasut389da972020-05-23 17:10:03 +0200502static int eepro100_initialize_mii(struct eepro100_priv *priv)
Marek Vasut66fed732020-05-23 16:20:25 +0200503{
504 return 0;
505}
506#endif
507
Marek Vasut047a8002020-05-23 15:07:30 +0200508static struct pci_device_id supported[] = {
Marek Vasut3a156842020-05-23 15:11:30 +0200509 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557) },
510 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559) },
511 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER) },
512 { }
Marek Vasut047a8002020-05-23 15:07:30 +0200513};
514
Marek Vasut389da972020-05-23 17:10:03 +0200515static void read_hw_addr(struct eepro100_priv *priv, bd_t *bis)
Marek Vasut047a8002020-05-23 15:07:30 +0200516{
517 u16 sum = 0;
518 int i, j;
Marek Vasut389da972020-05-23 17:10:03 +0200519 int addr_len = read_eeprom(priv, 0, 6) == 0xffff ? 8 : 6;
Marek Vasut047a8002020-05-23 15:07:30 +0200520
521 for (j = 0, i = 0; i < 0x40; i++) {
Marek Vasut389da972020-05-23 17:10:03 +0200522 u16 value = read_eeprom(priv, i, addr_len);
Marek Vasut047a8002020-05-23 15:07:30 +0200523
524 sum += value;
525 if (i < 3) {
Marek Vasut389da972020-05-23 17:10:03 +0200526 priv->enetaddr[j++] = value;
527 priv->enetaddr[j++] = value >> 8;
Marek Vasut047a8002020-05-23 15:07:30 +0200528 }
529 }
530
531 if (sum != 0xBABA) {
Marek Vasut389da972020-05-23 17:10:03 +0200532 memset(priv->enetaddr, 0, ETH_ALEN);
Marek Vasut047a8002020-05-23 15:07:30 +0200533 debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
Marek Vasut389da972020-05-23 17:10:03 +0200534 priv->name, sum);
Marek Vasut047a8002020-05-23 15:07:30 +0200535 }
536}
537
Marek Vasut7a308732020-05-23 13:23:13 +0200538static int eepro100_init(struct eth_device *dev, bd_t *bis)
wdenk1df49e22002-09-17 21:37:55 +0000539{
Marek Vasut389da972020-05-23 17:10:03 +0200540 struct eepro100_priv *priv =
541 container_of(dev, struct eepro100_priv, dev);
Marek Vasutfb8307e2020-05-23 17:13:26 +0200542 struct eepro100_rxfd *rx_ring = priv->rx_ring;
543 struct eepro100_txfd *tx_ring = priv->tx_ring;
Marek Vasut95655b92020-05-23 14:30:31 +0200544 struct eepro100_txfd *ias_cmd, *cfg_cmd;
545 int ret, status = -1;
wdenk1df49e22002-09-17 21:37:55 +0000546 int tx_cur;
wdenk1df49e22002-09-17 21:37:55 +0000547
Marek Vasutaba283d2020-05-23 12:49:16 +0200548 /* Reset the ethernet controller */
Marek Vasut389da972020-05-23 17:10:03 +0200549 OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
Simon Glass07e11142020-05-10 11:40:10 -0600550 udelay(20);
wdenk1df49e22002-09-17 21:37:55 +0000551
Marek Vasut389da972020-05-23 17:10:03 +0200552 OUTL(priv, I82559_RESET, SCB_PORT);
Simon Glass07e11142020-05-10 11:40:10 -0600553 udelay(20);
wdenk1df49e22002-09-17 21:37:55 +0000554
Marek Vasut389da972020-05-23 17:10:03 +0200555 if (!wait_for_eepro100(priv)) {
Marek Vasutdb9f1812020-05-23 13:17:03 +0200556 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200557 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000558 }
Marek Vasut389da972020-05-23 17:10:03 +0200559 OUTL(priv, 0, SCB_POINTER);
560 OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000561
Marek Vasut389da972020-05-23 17:10:03 +0200562 if (!wait_for_eepro100(priv)) {
Marek Vasutdb9f1812020-05-23 13:17:03 +0200563 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200564 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000565 }
Marek Vasut389da972020-05-23 17:10:03 +0200566 OUTL(priv, 0, SCB_POINTER);
567 OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000568
Marek Vasutaba283d2020-05-23 12:49:16 +0200569 /* Initialize Rx and Tx rings. */
Marek Vasut389da972020-05-23 17:10:03 +0200570 init_rx_ring(priv);
571 purge_tx_ring(priv);
wdenk1df49e22002-09-17 21:37:55 +0000572
Marek Vasutaba283d2020-05-23 12:49:16 +0200573 /* Tell the adapter where the RX ring is located. */
Marek Vasut389da972020-05-23 17:10:03 +0200574 if (!wait_for_eepro100(priv)) {
Marek Vasutdb9f1812020-05-23 13:17:03 +0200575 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200576 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000577 }
578
Marek Vasut5116aae2020-05-23 14:55:26 +0200579 /* RX ring cache was already flushed in init_rx_ring() */
Marek Vasutfb8307e2020-05-23 17:13:26 +0200580 OUTL(priv, phys_to_bus(priv->devno, (u32)&rx_ring[priv->rx_next]),
Marek Vasutfa9e1212020-05-23 16:38:41 +0200581 SCB_POINTER);
Marek Vasut389da972020-05-23 17:10:03 +0200582 OUTW(priv, SCB_M | RUC_START, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000583
584 /* Send the Configure frame */
Marek Vasutfb8307e2020-05-23 17:13:26 +0200585 tx_cur = priv->tx_next;
586 priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
wdenk1df49e22002-09-17 21:37:55 +0000587
Marek Vasut95655b92020-05-23 14:30:31 +0200588 cfg_cmd = &tx_ring[tx_cur];
Marek Vasutb0131732020-05-23 13:45:41 +0200589 cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
590 CONFIG_SYS_CMD_CONFIGURE);
wdenk1df49e22002-09-17 21:37:55 +0000591 cfg_cmd->status = 0;
Marek Vasut389da972020-05-23 17:10:03 +0200592 cfg_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutfb8307e2020-05-23 17:13:26 +0200593 (u32)&tx_ring[priv->tx_next]));
wdenk1df49e22002-09-17 21:37:55 +0000594
Marek Vasut95655b92020-05-23 14:30:31 +0200595 memcpy(((struct descriptor *)cfg_cmd)->params, i82558_config_cmd,
Marek Vasut773af832020-05-23 13:21:43 +0200596 sizeof(i82558_config_cmd));
wdenk1df49e22002-09-17 21:37:55 +0000597
Marek Vasut389da972020-05-23 17:10:03 +0200598 ret = eepro100_txcmd_send(priv, cfg_cmd);
Marek Vasut95655b92020-05-23 14:30:31 +0200599 if (ret) {
600 if (ret == -ETIMEDOUT)
601 printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200602 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000603 }
604
Marek Vasutaba283d2020-05-23 12:49:16 +0200605 /* Send the Individual Address Setup frame */
Marek Vasutfb8307e2020-05-23 17:13:26 +0200606 tx_cur = priv->tx_next;
607 priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
wdenk1df49e22002-09-17 21:37:55 +0000608
Marek Vasut95655b92020-05-23 14:30:31 +0200609 ias_cmd = &tx_ring[tx_cur];
Marek Vasutb0131732020-05-23 13:45:41 +0200610 ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
611 CONFIG_SYS_CMD_IAS);
wdenk1df49e22002-09-17 21:37:55 +0000612 ias_cmd->status = 0;
Marek Vasut389da972020-05-23 17:10:03 +0200613 ias_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutfb8307e2020-05-23 17:13:26 +0200614 (u32)&tx_ring[priv->tx_next]));
wdenk1df49e22002-09-17 21:37:55 +0000615
Marek Vasut389da972020-05-23 17:10:03 +0200616 memcpy(((struct descriptor *)ias_cmd)->params, priv->enetaddr, 6);
wdenk1df49e22002-09-17 21:37:55 +0000617
Marek Vasut389da972020-05-23 17:10:03 +0200618 ret = eepro100_txcmd_send(priv, ias_cmd);
Marek Vasut95655b92020-05-23 14:30:31 +0200619 if (ret) {
620 if (ret == -ETIMEDOUT)
621 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200622 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000623 }
624
Ben Warren422b1a02008-01-09 18:15:53 -0500625 status = 0;
wdenk1df49e22002-09-17 21:37:55 +0000626
Marek Vasutf3878f52020-05-23 13:52:50 +0200627done:
wdenk1df49e22002-09-17 21:37:55 +0000628 return status;
629}
630
Joe Hershbergerbccbe612012-05-21 14:45:25 +0000631static int eepro100_send(struct eth_device *dev, void *packet, int length)
wdenk1df49e22002-09-17 21:37:55 +0000632{
Marek Vasut389da972020-05-23 17:10:03 +0200633 struct eepro100_priv *priv =
634 container_of(dev, struct eepro100_priv, dev);
Marek Vasutfb8307e2020-05-23 17:13:26 +0200635 struct eepro100_txfd *tx_ring = priv->tx_ring;
Marek Vasut5116aae2020-05-23 14:55:26 +0200636 struct eepro100_txfd *desc;
Marek Vasut95655b92020-05-23 14:30:31 +0200637 int ret, status = -1;
wdenk1df49e22002-09-17 21:37:55 +0000638 int tx_cur;
639
640 if (length <= 0) {
Marek Vasut389da972020-05-23 17:10:03 +0200641 printf("%s: bad packet size: %d\n", priv->name, length);
Marek Vasutf3878f52020-05-23 13:52:50 +0200642 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000643 }
644
Marek Vasutfb8307e2020-05-23 17:13:26 +0200645 tx_cur = priv->tx_next;
646 priv->tx_next = (priv->tx_next + 1) % NUM_TX_DESC;
wdenk1df49e22002-09-17 21:37:55 +0000647
Marek Vasut5116aae2020-05-23 14:55:26 +0200648 desc = &tx_ring[tx_cur];
649 desc->command = cpu_to_le16(TXCB_CMD_TRANSMIT | TXCB_CMD_SF |
650 TXCB_CMD_S | TXCB_CMD_EL);
651 desc->status = 0;
Marek Vasutfb8307e2020-05-23 17:13:26 +0200652 desc->count = cpu_to_le32(priv->tx_threshold);
Marek Vasut389da972020-05-23 17:10:03 +0200653 desc->link = cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutfb8307e2020-05-23 17:13:26 +0200654 (u32)&tx_ring[priv->tx_next]));
Marek Vasut389da972020-05-23 17:10:03 +0200655 desc->tx_desc_addr = cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutfa9e1212020-05-23 16:38:41 +0200656 (u32)&desc->tx_buf_addr0));
Marek Vasut389da972020-05-23 17:10:03 +0200657 desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutfa9e1212020-05-23 16:38:41 +0200658 (u_long)packet));
Marek Vasut5116aae2020-05-23 14:55:26 +0200659 desc->tx_buf_size0 = cpu_to_le32(length);
wdenk1df49e22002-09-17 21:37:55 +0000660
Marek Vasut389da972020-05-23 17:10:03 +0200661 ret = eepro100_txcmd_send(priv, &tx_ring[tx_cur]);
Marek Vasut95655b92020-05-23 14:30:31 +0200662 if (ret) {
663 if (ret == -ETIMEDOUT)
664 printf("%s: Tx error ethernet controller not ready.\n",
Marek Vasut389da972020-05-23 17:10:03 +0200665 priv->name);
Marek Vasutf3878f52020-05-23 13:52:50 +0200666 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000667 }
668
669 status = length;
670
Marek Vasutf3878f52020-05-23 13:52:50 +0200671done:
wdenk1df49e22002-09-17 21:37:55 +0000672 return status;
673}
674
Marek Vasutdb9f1812020-05-23 13:17:03 +0200675static int eepro100_recv(struct eth_device *dev)
wdenk1df49e22002-09-17 21:37:55 +0000676{
Marek Vasut389da972020-05-23 17:10:03 +0200677 struct eepro100_priv *priv =
678 container_of(dev, struct eepro100_priv, dev);
Marek Vasutfb8307e2020-05-23 17:13:26 +0200679 struct eepro100_rxfd *rx_ring = priv->rx_ring;
Marek Vasut5116aae2020-05-23 14:55:26 +0200680 struct eepro100_rxfd *desc;
wdenk1df49e22002-09-17 21:37:55 +0000681 int rx_prev, length = 0;
Marek Vasut5116aae2020-05-23 14:55:26 +0200682 u16 status, stat;
wdenk1df49e22002-09-17 21:37:55 +0000683
Marek Vasut389da972020-05-23 17:10:03 +0200684 stat = INW(priv, SCB_STATUS);
685 OUTW(priv, stat & SCB_STATUS_RNR, SCB_STATUS);
wdenk1df49e22002-09-17 21:37:55 +0000686
687 for (;;) {
Marek Vasutfb8307e2020-05-23 17:13:26 +0200688 desc = &rx_ring[priv->rx_next];
Marek Vasut5116aae2020-05-23 14:55:26 +0200689 invalidate_dcache_range((unsigned long)desc,
690 (unsigned long)desc + sizeof(*desc));
691 status = le16_to_cpu(desc->status);
wdenk1df49e22002-09-17 21:37:55 +0000692
Marek Vasut9b12ff92020-05-23 13:20:14 +0200693 if (!(status & RFD_STATUS_C))
wdenk1df49e22002-09-17 21:37:55 +0000694 break;
wdenk1df49e22002-09-17 21:37:55 +0000695
Marek Vasutaba283d2020-05-23 12:49:16 +0200696 /* Valid frame status. */
wdenk1df49e22002-09-17 21:37:55 +0000697 if ((status & RFD_STATUS_OK)) {
Marek Vasutaba283d2020-05-23 12:49:16 +0200698 /* A valid frame received. */
Marek Vasut5116aae2020-05-23 14:55:26 +0200699 length = le32_to_cpu(desc->count) & 0x3fff;
wdenk1df49e22002-09-17 21:37:55 +0000700
Marek Vasutaba283d2020-05-23 12:49:16 +0200701 /* Pass the packet up to the protocol layers. */
Marek Vasut5116aae2020-05-23 14:55:26 +0200702 net_process_received_packet((u8 *)desc->data, length);
wdenk1df49e22002-09-17 21:37:55 +0000703 } else {
Marek Vasutaba283d2020-05-23 12:49:16 +0200704 /* There was an error. */
Marek Vasutdb9f1812020-05-23 13:17:03 +0200705 printf("RX error status = 0x%08X\n", status);
wdenk1df49e22002-09-17 21:37:55 +0000706 }
707
Marek Vasut5116aae2020-05-23 14:55:26 +0200708 desc->control = cpu_to_le16(RFD_CONTROL_S);
709 desc->status = 0;
710 desc->count = cpu_to_le32(PKTSIZE_ALIGN << 16);
711 flush_dcache_range((unsigned long)desc,
712 (unsigned long)desc + sizeof(*desc));
wdenk1df49e22002-09-17 21:37:55 +0000713
Marek Vasutfb8307e2020-05-23 17:13:26 +0200714 rx_prev = (priv->rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
Marek Vasut5116aae2020-05-23 14:55:26 +0200715 desc = &rx_ring[rx_prev];
716 desc->control = 0;
717 flush_dcache_range((unsigned long)desc,
718 (unsigned long)desc + sizeof(*desc));
wdenk1df49e22002-09-17 21:37:55 +0000719
Marek Vasutaba283d2020-05-23 12:49:16 +0200720 /* Update entry information. */
Marek Vasutfb8307e2020-05-23 17:13:26 +0200721 priv->rx_next = (priv->rx_next + 1) % NUM_RX_DESC;
wdenk1df49e22002-09-17 21:37:55 +0000722 }
723
724 if (stat & SCB_STATUS_RNR) {
Marek Vasut389da972020-05-23 17:10:03 +0200725 printf("%s: Receiver is not ready, restart it !\n", priv->name);
wdenk1df49e22002-09-17 21:37:55 +0000726
Marek Vasutaba283d2020-05-23 12:49:16 +0200727 /* Reinitialize Rx ring. */
Marek Vasut389da972020-05-23 17:10:03 +0200728 init_rx_ring(priv);
wdenk1df49e22002-09-17 21:37:55 +0000729
Marek Vasut389da972020-05-23 17:10:03 +0200730 if (!wait_for_eepro100(priv)) {
Marek Vasutdb9f1812020-05-23 13:17:03 +0200731 printf("Error: Can not restart ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200732 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000733 }
734
Marek Vasut5116aae2020-05-23 14:55:26 +0200735 /* RX ring cache was already flushed in init_rx_ring() */
Marek Vasut389da972020-05-23 17:10:03 +0200736 OUTL(priv, phys_to_bus(priv->devno,
Marek Vasutfb8307e2020-05-23 17:13:26 +0200737 (u32)&rx_ring[priv->rx_next]),
738 SCB_POINTER);
Marek Vasut389da972020-05-23 17:10:03 +0200739 OUTW(priv, SCB_M | RUC_START, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000740 }
741
Marek Vasutf3878f52020-05-23 13:52:50 +0200742done:
wdenk1df49e22002-09-17 21:37:55 +0000743 return length;
744}
745
Marek Vasutdb9f1812020-05-23 13:17:03 +0200746static void eepro100_halt(struct eth_device *dev)
wdenk1df49e22002-09-17 21:37:55 +0000747{
Marek Vasut389da972020-05-23 17:10:03 +0200748 struct eepro100_priv *priv =
749 container_of(dev, struct eepro100_priv, dev);
750
Marek Vasutaba283d2020-05-23 12:49:16 +0200751 /* Reset the ethernet controller */
Marek Vasut389da972020-05-23 17:10:03 +0200752 OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
Simon Glass07e11142020-05-10 11:40:10 -0600753 udelay(20);
wdenk1df49e22002-09-17 21:37:55 +0000754
Marek Vasut389da972020-05-23 17:10:03 +0200755 OUTL(priv, I82559_RESET, SCB_PORT);
Simon Glass07e11142020-05-10 11:40:10 -0600756 udelay(20);
wdenk1df49e22002-09-17 21:37:55 +0000757
Marek Vasut389da972020-05-23 17:10:03 +0200758 if (!wait_for_eepro100(priv)) {
Marek Vasutdb9f1812020-05-23 13:17:03 +0200759 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200760 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000761 }
Marek Vasut389da972020-05-23 17:10:03 +0200762 OUTL(priv, 0, SCB_POINTER);
763 OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000764
Marek Vasut389da972020-05-23 17:10:03 +0200765 if (!wait_for_eepro100(priv)) {
Marek Vasutdb9f1812020-05-23 13:17:03 +0200766 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200767 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000768 }
Marek Vasut389da972020-05-23 17:10:03 +0200769 OUTL(priv, 0, SCB_POINTER);
770 OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000771
Marek Vasutf3878f52020-05-23 13:52:50 +0200772done:
wdenk1df49e22002-09-17 21:37:55 +0000773 return;
774}
775
Marek Vasut047a8002020-05-23 15:07:30 +0200776int eepro100_initialize(bd_t *bis)
wdenk1df49e22002-09-17 21:37:55 +0000777{
Marek Vasutbd159c62020-05-23 16:49:07 +0200778 struct eepro100_priv *priv;
Marek Vasut047a8002020-05-23 15:07:30 +0200779 struct eth_device *dev;
Marek Vasut66fed732020-05-23 16:20:25 +0200780 int card_number = 0;
Marek Vasut047a8002020-05-23 15:07:30 +0200781 u32 iobase, status;
Marek Vasut66fed732020-05-23 16:20:25 +0200782 pci_dev_t devno;
Marek Vasut047a8002020-05-23 15:07:30 +0200783 int idx = 0;
Marek Vasut66fed732020-05-23 16:20:25 +0200784 int ret;
wdenk1df49e22002-09-17 21:37:55 +0000785
Marek Vasut047a8002020-05-23 15:07:30 +0200786 while (1) {
787 /* Find PCI device */
788 devno = pci_find_devices(supported, idx++);
789 if (devno < 0)
790 break;
wdenk1df49e22002-09-17 21:37:55 +0000791
Marek Vasut047a8002020-05-23 15:07:30 +0200792 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
793 iobase &= ~0xf;
wdenk1df49e22002-09-17 21:37:55 +0000794
Marek Vasut047a8002020-05-23 15:07:30 +0200795 debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
796 iobase);
wdenk1df49e22002-09-17 21:37:55 +0000797
Marek Vasut047a8002020-05-23 15:07:30 +0200798 pci_write_config_dword(devno, PCI_COMMAND,
799 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
wdenk1df49e22002-09-17 21:37:55 +0000800
Marek Vasut047a8002020-05-23 15:07:30 +0200801 /* Check if I/O accesses and Bus Mastering are enabled. */
802 pci_read_config_dword(devno, PCI_COMMAND, &status);
803 if (!(status & PCI_COMMAND_MEMORY)) {
804 printf("Error: Can not enable MEM access.\n");
805 continue;
wdenk1df49e22002-09-17 21:37:55 +0000806 }
Marek Vasut047a8002020-05-23 15:07:30 +0200807
808 if (!(status & PCI_COMMAND_MASTER)) {
809 printf("Error: Can not enable Bus Mastering.\n");
810 continue;
811 }
812
Marek Vasutbd159c62020-05-23 16:49:07 +0200813 priv = calloc(1, sizeof(*priv));
814 if (!priv) {
Marek Vasut047a8002020-05-23 15:07:30 +0200815 printf("eepro100: Can not allocate memory\n");
816 break;
817 }
Marek Vasutbd159c62020-05-23 16:49:07 +0200818 dev = &priv->dev;
Marek Vasut047a8002020-05-23 15:07:30 +0200819
820 sprintf(dev->name, "i82559#%d", card_number);
Marek Vasut389da972020-05-23 17:10:03 +0200821 priv->name = dev->name;
822 /* this have to come before bus_to_phys() */
823 priv->devno = devno;
824 priv->iobase = (void __iomem *)bus_to_phys(devno, iobase);
825 priv->enetaddr = dev->enetaddr;
826
Marek Vasut047a8002020-05-23 15:07:30 +0200827 dev->init = eepro100_init;
828 dev->halt = eepro100_halt;
829 dev->send = eepro100_send;
830 dev->recv = eepro100_recv;
831
832 eth_register(dev);
833
Marek Vasut389da972020-05-23 17:10:03 +0200834 ret = eepro100_initialize_mii(priv);
Marek Vasut66fed732020-05-23 16:20:25 +0200835 if (ret) {
836 eth_unregister(dev);
Marek Vasutbd159c62020-05-23 16:49:07 +0200837 free(priv);
Marek Vasut66fed732020-05-23 16:20:25 +0200838 return ret;
839 }
Marek Vasut047a8002020-05-23 15:07:30 +0200840
841 card_number++;
842
843 /* Set the latency timer for value. */
844 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
845
846 udelay(10 * 1000);
847
Marek Vasut389da972020-05-23 17:10:03 +0200848 read_hw_addr(priv, bis);
wdenk1df49e22002-09-17 21:37:55 +0000849 }
850
Marek Vasut047a8002020-05-23 15:07:30 +0200851 return card_number;
wdenk1df49e22002-09-17 21:37:55 +0000852}