| Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 1 | config RISCV_NDS |
| Bin Meng | 44fe795 | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 2 | bool |
| Rick Chen | 8848474 | 2019-04-02 15:56:41 +0800 | [diff] [blame] | 3 | select ARCH_EARLY_INIT_R |
| Yu Chien Peter Lin | fd55792 | 2024-04-11 17:29:45 +0800 | [diff] [blame^] | 4 | select SYS_CACHE_SHIFT_6 |
| Rick Chen | 8848474 | 2019-04-02 15:56:41 +0800 | [diff] [blame] | 5 | imply CPU |
| 6 | imply CPU_RISCV |
| Sean Anderson | c33efaf | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 7 | imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) |
| Yu Chien Peter Lin | 8a0d5f2 | 2023-09-29 12:03:07 +0800 | [diff] [blame] | 8 | imply ANDES_PLMT_TIMER |
| 9 | imply SPL_ANDES_PLMT_TIMER |
| Yu Chien Peter Lin | a5dfa3b | 2022-10-25 23:03:50 +0800 | [diff] [blame] | 10 | imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) |
| Yu Chien Peter Lin | 487c211 | 2023-02-06 16:10:50 +0800 | [diff] [blame] | 11 | imply V5L2_CACHE |
| Simon Glass | 529d5f9 | 2021-03-15 18:11:18 +1300 | [diff] [blame] | 12 | imply SPL_CPU |
| Rick Chen | ca06444 | 2019-11-14 13:52:21 +0800 | [diff] [blame] | 13 | imply SPL_OPENSBI |
| 14 | imply SPL_LOAD_FIT |
| Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 15 | help |
| Bin Meng | 44fe795 | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 16 | Run U-Boot on AndeStar V5 platforms and use some specific features |
| 17 | which are provided by Andes Technology AndeStar V5 families. |