Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 8870e45 | 2013-04-09 21:06:08 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2013 Stefan Roese <sr@denx.de> |
Stefan Roese | 8870e45 | 2013-04-09 21:06:08 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 4d72caa | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 7 | #include <lmb.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Jeroen Hofstee | 5624c6b | 2014-10-08 22:57:52 +0200 | [diff] [blame] | 9 | #include <asm/arch/sys_proto.h> |
Simon Glass | c05ed00 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 10 | #include <linux/delay.h> |
Masahiro Yamada | 1221ce4 | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 11 | #include <linux/errno.h> |
Stefan Roese | 8870e45 | 2013-04-09 21:06:08 +0000 | [diff] [blame] | 12 | #include <asm/io.h> |
Stefano Babic | 552a848 | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 13 | #include <asm/mach-imx/regs-common.h> |
Stefan Roese | 8870e45 | 2013-04-09 21:06:08 +0000 | [diff] [blame] | 14 | |
Ye Li | 528915c | 2019-01-04 09:10:20 +0000 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
Stefan Roese | 8870e45 | 2013-04-09 21:06:08 +0000 | [diff] [blame] | 17 | /* 1 second delay should be plenty of time for block reset. */ |
| 18 | #define RESET_MAX_TIMEOUT 1000000 |
| 19 | |
| 20 | #define MXS_BLOCK_SFTRST (1 << 31) |
| 21 | #define MXS_BLOCK_CLKGATE (1 << 30) |
| 22 | |
| 23 | int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned |
| 24 | int timeout) |
| 25 | { |
| 26 | while (--timeout) { |
| 27 | if ((readl(®->reg) & mask) == mask) |
| 28 | break; |
| 29 | udelay(1); |
| 30 | } |
| 31 | |
| 32 | return !timeout; |
| 33 | } |
| 34 | |
| 35 | int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned |
| 36 | int timeout) |
| 37 | { |
| 38 | while (--timeout) { |
| 39 | if ((readl(®->reg) & mask) == 0) |
| 40 | break; |
| 41 | udelay(1); |
| 42 | } |
| 43 | |
| 44 | return !timeout; |
| 45 | } |
| 46 | |
| 47 | int mxs_reset_block(struct mxs_register_32 *reg) |
| 48 | { |
| 49 | /* Clear SFTRST */ |
| 50 | writel(MXS_BLOCK_SFTRST, ®->reg_clr); |
| 51 | |
| 52 | if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) |
| 53 | return 1; |
| 54 | |
| 55 | /* Clear CLKGATE */ |
| 56 | writel(MXS_BLOCK_CLKGATE, ®->reg_clr); |
| 57 | |
| 58 | /* Set SFTRST */ |
| 59 | writel(MXS_BLOCK_SFTRST, ®->reg_set); |
| 60 | |
| 61 | /* Wait for CLKGATE being set */ |
| 62 | if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) |
| 63 | return 1; |
| 64 | |
| 65 | /* Clear SFTRST */ |
| 66 | writel(MXS_BLOCK_SFTRST, ®->reg_clr); |
| 67 | |
| 68 | if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) |
| 69 | return 1; |
| 70 | |
| 71 | /* Clear CLKGATE */ |
| 72 | writel(MXS_BLOCK_CLKGATE, ®->reg_clr); |
| 73 | |
| 74 | if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) |
| 75 | return 1; |
| 76 | |
| 77 | return 0; |
| 78 | } |
Ye Li | 528915c | 2019-01-04 09:10:20 +0000 | [diff] [blame] | 79 | |
| 80 | static ulong get_sp(void) |
| 81 | { |
| 82 | ulong ret; |
| 83 | |
| 84 | asm("mov %0, sp" : "=r"(ret) : ); |
| 85 | return ret; |
| 86 | } |
| 87 | |
| 88 | void board_lmb_reserve(struct lmb *lmb) |
| 89 | { |
| 90 | ulong sp, bank_end; |
| 91 | int bank; |
| 92 | |
| 93 | sp = get_sp(); |
| 94 | debug("## Current stack ends at 0x%08lx ", sp); |
| 95 | |
| 96 | /* adjust sp by 16K to be safe */ |
| 97 | sp -= 4096 << 2; |
| 98 | for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { |
| 99 | if (sp < gd->bd->bi_dram[bank].start) |
| 100 | continue; |
| 101 | bank_end = gd->bd->bi_dram[bank].start + |
| 102 | gd->bd->bi_dram[bank].size; |
| 103 | if (sp >= bank_end) |
| 104 | continue; |
| 105 | lmb_reserve(lmb, sp, bank_end - sp); |
| 106 | break; |
| 107 | } |
| 108 | } |