Poonam Aggrwal | 0e87098 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 1 | /* |
Kumar Gala | acf3f8d | 2011-07-21 00:20:21 -0500 | [diff] [blame] | 2 | * Copyright 2008-2011 Freescale Semiconductor, Inc. |
Poonam Aggrwal | 0e87098 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 3 | * Kumar Gala <kumar.gala@freescale.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 24 | #include <asm-offsets.h> |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 25 | #include <config.h> |
| 26 | #include <mpc85xx.h> |
| 27 | #include <version.h> |
| 28 | |
| 29 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ |
| 30 | |
| 31 | #include <ppc_asm.tmpl> |
| 32 | #include <ppc_defs.h> |
| 33 | |
| 34 | #include <asm/cache.h> |
| 35 | #include <asm/mmu.h> |
| 36 | |
| 37 | /* To boot secondary cpus, we need a place for them to start up. |
| 38 | * Normally, they start at 0xfffffffc, but that's usually the |
| 39 | * firmware, and we don't want to have to run the firmware again. |
| 40 | * Instead, the primary cpu will set the BPTR to point here to |
| 41 | * this page. We then set up the core, and head to |
| 42 | * start_secondary. Note that this means that the code below |
| 43 | * must never exceed 1023 instructions (the branch at the end |
| 44 | * would then be the 1024th). |
| 45 | */ |
| 46 | .globl __secondary_start_page |
| 47 | .align 12 |
| 48 | __secondary_start_page: |
| 49 | /* First do some preliminary setup */ |
| 50 | lis r3, HID0_EMCP@h /* enable machine check */ |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 51 | #ifndef CONFIG_E500MC |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 52 | ori r3,r3,HID0_TBEN@l /* enable Timebase */ |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 53 | #endif |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 54 | #ifdef CONFIG_PHYS_64BIT |
| 55 | ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ |
| 56 | #endif |
| 57 | mtspr SPRN_HID0,r3 |
| 58 | |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 59 | #ifndef CONFIG_E500MC |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 60 | li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ |
Sandeep Gopalpet | ff8473e | 2010-03-12 10:45:02 +0530 | [diff] [blame] | 61 | mfspr r0,PVR |
| 62 | andi. r0,r0,0xff |
| 63 | cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ |
| 64 | blt 1f |
| 65 | /* Set MBDD bit also */ |
| 66 | ori r3, r3, HID1_MBDD@l |
| 67 | 1: |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 68 | mtspr SPRN_HID1,r3 |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 69 | #endif |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 70 | |
Kumar Gala | 43f082b | 2011-11-22 06:51:15 -0600 | [diff] [blame] | 71 | #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
| 72 | mfspr r3,977 |
| 73 | oris r3,r3,0x0100 |
| 74 | mtspr 977,r3 |
| 75 | #endif |
| 76 | |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 77 | /* Enable branch prediction */ |
Kumar Gala | 69bcf5b | 2010-03-29 13:50:31 -0500 | [diff] [blame] | 78 | lis r3,BUCSR_ENABLE@h |
| 79 | ori r3,r3,BUCSR_ENABLE@l |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 80 | mtspr SPRN_BUCSR,r3 |
| 81 | |
Kumar Gala | e0ff3d3 | 2008-09-08 08:51:29 -0500 | [diff] [blame] | 82 | /* Ensure TB is 0 */ |
| 83 | li r3,0 |
| 84 | mttbl r3 |
| 85 | mttbu r3 |
| 86 | |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 87 | /* Enable/invalidate the I-Cache */ |
Kumar Gala | 33f57bd | 2010-03-26 15:14:43 -0500 | [diff] [blame] | 88 | lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h |
| 89 | ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l |
| 90 | mtspr SPRN_L1CSR1,r2 |
| 91 | 1: |
| 92 | mfspr r3,SPRN_L1CSR1 |
| 93 | and. r1,r3,r2 |
| 94 | bne 1b |
| 95 | |
| 96 | lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h |
| 97 | ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l |
| 98 | mtspr SPRN_L1CSR1,r3 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 99 | isync |
Kumar Gala | 33f57bd | 2010-03-26 15:14:43 -0500 | [diff] [blame] | 100 | 2: |
| 101 | mfspr r3,SPRN_L1CSR1 |
| 102 | andi. r1,r3,L1CSR1_ICE@l |
| 103 | beq 2b |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 104 | |
| 105 | /* Enable/invalidate the D-Cache */ |
Kumar Gala | 33f57bd | 2010-03-26 15:14:43 -0500 | [diff] [blame] | 106 | lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h |
| 107 | ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l |
| 108 | mtspr SPRN_L1CSR0,r2 |
| 109 | 1: |
| 110 | mfspr r3,SPRN_L1CSR0 |
| 111 | and. r1,r3,r2 |
| 112 | bne 1b |
| 113 | |
| 114 | lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h |
| 115 | ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l |
| 116 | mtspr SPRN_L1CSR0,r3 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 117 | isync |
Kumar Gala | 33f57bd | 2010-03-26 15:14:43 -0500 | [diff] [blame] | 118 | 2: |
| 119 | mfspr r3,SPRN_L1CSR0 |
| 120 | andi. r1,r3,L1CSR0_DCE@l |
| 121 | beq 2b |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 122 | |
| 123 | #define toreset(x) (x - __secondary_start_page + 0xfffff000) |
| 124 | |
| 125 | /* get our PIR to figure out our table entry */ |
| 126 | lis r3,toreset(__spin_table)@h |
| 127 | ori r3,r3,toreset(__spin_table)@l |
| 128 | |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 129 | /* r10 has the base address for the entry */ |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 130 | mfspr r0,SPRN_PIR |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 131 | #ifdef CONFIG_E500MC |
| 132 | rlwinm r4,r0,27,27,31 |
| 133 | #else |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 134 | mr r4,r0 |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 135 | #endif |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 136 | slwi r8,r4,5 |
| 137 | add r10,r3,r8 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 138 | |
Kumar Gala | 82fd1f8 | 2009-03-19 02:53:01 -0500 | [diff] [blame] | 139 | #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) |
| 140 | /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ |
| 141 | slwi r8,r4,1 |
| 142 | addi r8,r8,32 |
| 143 | mtspr L1CSR2,r8 |
| 144 | #endif |
| 145 | |
York Sun | 5e23ab0 | 2012-05-07 07:26:47 +0000 | [diff] [blame^] | 146 | #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ |
| 147 | defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) |
| 148 | /* |
| 149 | * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 |
| 150 | * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 |
| 151 | * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 |
| 152 | */ |
York Sun | 1e9ea85 | 2012-05-07 07:26:45 +0000 | [diff] [blame] | 153 | mfspr r3,SPRN_SVR |
York Sun | 5e23ab0 | 2012-05-07 07:26:47 +0000 | [diff] [blame^] | 154 | rlwinm r6,r3,24,~0x800 /* clear E bit */ |
York Sun | 1e9ea85 | 2012-05-07 07:26:45 +0000 | [diff] [blame] | 155 | |
York Sun | 5e23ab0 | 2012-05-07 07:26:47 +0000 | [diff] [blame^] | 156 | lis r5,SVR_P4080@h |
| 157 | ori r5,r5,SVR_P4080@l |
| 158 | cmpw r6,r5 |
| 159 | bne 1f |
| 160 | |
| 161 | rlwinm r3,r3,0,0xf0 |
| 162 | li r5,0x30 |
| 163 | cmpw r3,r5 |
| 164 | bge 2f |
| 165 | 1: |
| 166 | mfspr r3,L1CSR2 |
| 167 | oris r3,r3,(L1CSR2_DCWS)@h |
| 168 | mtspr L1CSR2,r3 |
York Sun | 1e9ea85 | 2012-05-07 07:26:45 +0000 | [diff] [blame] | 169 | 2: |
Kumar Gala | fd3c9be | 2010-05-05 22:35:27 -0500 | [diff] [blame] | 170 | #endif |
| 171 | |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 172 | #ifdef CONFIG_BACKSIDE_L2_CACHE |
Kumar Gala | acf3f8d | 2011-07-21 00:20:21 -0500 | [diff] [blame] | 173 | /* skip L2 setup on P2040/P2040E as they have no L2 */ |
| 174 | mfspr r2,SPRN_SVR |
| 175 | lis r3,SVR_P2040@h |
| 176 | ori r3,r3,SVR_P2040@l |
| 177 | cmpw r2,r3 |
| 178 | beq 3f |
| 179 | |
| 180 | lis r3,SVR_P2040_E@h |
| 181 | ori r3,r3,SVR_P2040_E@l |
| 182 | cmpw r2,r3 |
| 183 | beq 3f |
| 184 | |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 185 | /* Enable/invalidate the L2 cache */ |
| 186 | msync |
Dave Liu | ff882295 | 2009-10-31 07:59:55 +0800 | [diff] [blame] | 187 | lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h |
| 188 | ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l |
| 189 | mtspr SPRN_L2CSR0,r2 |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 190 | 1: |
| 191 | mfspr r3,SPRN_L2CSR0 |
Dave Liu | ff882295 | 2009-10-31 07:59:55 +0800 | [diff] [blame] | 192 | and. r1,r3,r2 |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 193 | bne 1b |
| 194 | |
Kumar Gala | 82fd1f8 | 2009-03-19 02:53:01 -0500 | [diff] [blame] | 195 | #ifdef CONFIG_SYS_CACHE_STASHING |
| 196 | /* set stash id to (coreID) * 2 + 32 + L2 (1) */ |
| 197 | addi r3,r8,1 |
| 198 | mtspr SPRN_L2CSR1,r3 |
| 199 | #endif |
| 200 | |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 201 | lis r3,CONFIG_SYS_INIT_L2CSR0@h |
| 202 | ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l |
| 203 | mtspr SPRN_L2CSR0,r3 |
| 204 | isync |
Dave Liu | ff882295 | 2009-10-31 07:59:55 +0800 | [diff] [blame] | 205 | 2: |
| 206 | mfspr r3,SPRN_L2CSR0 |
| 207 | andis. r1,r3,L2CSR0_L2E@h |
| 208 | beq 2b |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 209 | #endif |
Kumar Gala | acf3f8d | 2011-07-21 00:20:21 -0500 | [diff] [blame] | 210 | 3: |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 211 | |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 212 | #define EPAPR_MAGIC (0x45504150) |
| 213 | #define ENTRY_ADDR_UPPER 0 |
| 214 | #define ENTRY_ADDR_LOWER 4 |
| 215 | #define ENTRY_R3_UPPER 8 |
| 216 | #define ENTRY_R3_LOWER 12 |
| 217 | #define ENTRY_RESV 16 |
| 218 | #define ENTRY_PIR 20 |
| 219 | #define ENTRY_R6_UPPER 24 |
| 220 | #define ENTRY_R6_LOWER 28 |
| 221 | #define ENTRY_SIZE 32 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 222 | |
| 223 | /* setup the entry */ |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 224 | li r3,0 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 225 | li r8,1 |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 226 | stw r0,ENTRY_PIR(r10) |
| 227 | stw r3,ENTRY_ADDR_UPPER(r10) |
| 228 | stw r8,ENTRY_ADDR_LOWER(r10) |
| 229 | stw r3,ENTRY_R3_UPPER(r10) |
| 230 | stw r4,ENTRY_R3_LOWER(r10) |
| 231 | stw r3,ENTRY_R6_UPPER(r10) |
| 232 | stw r3,ENTRY_R6_LOWER(r10) |
| 233 | |
Peter Tyser | 5ccd29c | 2009-10-23 15:55:47 -0500 | [diff] [blame] | 234 | /* load r13 with the address of the 'bootpg' in SDRAM */ |
| 235 | lis r13,toreset(__bootpg_addr)@h |
| 236 | ori r13,r13,toreset(__bootpg_addr)@l |
| 237 | lwz r13,0(r13) |
| 238 | |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 239 | /* setup mapping for AS = 1, and jump there */ |
| 240 | lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h |
| 241 | mtspr SPRN_MAS0,r11 |
| 242 | lis r11,(MAS1_VALID|MAS1_IPROT)@h |
| 243 | ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l |
| 244 | mtspr SPRN_MAS1,r11 |
Kumar Gala | abc76eb | 2009-11-17 20:21:20 -0600 | [diff] [blame] | 245 | oris r11,r13,(MAS2_I|MAS2_G)@h |
| 246 | ori r11,r13,(MAS2_I|MAS2_G)@l |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 247 | mtspr SPRN_MAS2,r11 |
Peter Tyser | 5ccd29c | 2009-10-23 15:55:47 -0500 | [diff] [blame] | 248 | oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h |
| 249 | ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 250 | mtspr SPRN_MAS3,r11 |
| 251 | tlbwe |
| 252 | |
| 253 | bl 1f |
| 254 | 1: mflr r11 |
Peter Tyser | 5ccd29c | 2009-10-23 15:55:47 -0500 | [diff] [blame] | 255 | /* |
| 256 | * OR in 0xfff to create a mask of the bootpg SDRAM address. We use |
| 257 | * this mask to fixup the cpu spin table and the address that we want |
| 258 | * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the |
| 259 | * bootpg is at 0x7ffff000 in SDRAM. |
| 260 | */ |
| 261 | ori r13,r13,0xfff |
| 262 | and r11, r11, r13 |
| 263 | and r10, r10, r13 |
| 264 | |
| 265 | addi r11,r11,(2f-1b) |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 266 | mfmsr r13 |
| 267 | ori r12,r13,MSR_IS|MSR_DS@l |
| 268 | |
| 269 | mtspr SPRN_SRR0,r11 |
| 270 | mtspr SPRN_SRR1,r12 |
| 271 | rfi |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 272 | |
| 273 | /* spin waiting for addr */ |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 274 | 2: |
| 275 | lwz r4,ENTRY_ADDR_LOWER(r10) |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 276 | andi. r11,r4,1 |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 277 | bne 2b |
Kumar Gala | cf6cc01 | 2008-04-28 02:24:04 -0500 | [diff] [blame] | 278 | isync |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 279 | |
Kumar Gala | 26f4cdba | 2009-08-14 13:37:54 -0500 | [diff] [blame] | 280 | /* setup IVORs to match fixed offsets */ |
| 281 | #include "fixed_ivor.S" |
| 282 | |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 283 | /* get the upper bits of the addr */ |
| 284 | lwz r11,ENTRY_ADDR_UPPER(r10) |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 285 | |
| 286 | /* setup branch addr */ |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 287 | mtspr SPRN_SRR0,r4 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 288 | |
| 289 | /* mark the entry as released */ |
| 290 | li r8,3 |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 291 | stw r8,ENTRY_ADDR_LOWER(r10) |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 292 | |
| 293 | /* mask by ~64M to setup our tlb we will jump to */ |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 294 | rlwinm r12,r4,0,0,5 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 295 | |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 296 | /* setup r3, r4, r5, r6, r7, r8, r9 */ |
| 297 | lwz r3,ENTRY_R3_LOWER(r10) |
| 298 | li r4,0 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 299 | li r5,0 |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 300 | lwz r6,ENTRY_R6_LOWER(r10) |
| 301 | lis r7,(64*1024*1024)@h |
| 302 | li r8,0 |
| 303 | li r9,0 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 304 | |
| 305 | /* load up the pir */ |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 306 | lwz r0,ENTRY_PIR(r10) |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 307 | mtspr SPRN_PIR,r0 |
| 308 | mfspr r0,SPRN_PIR |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 309 | stw r0,ENTRY_PIR(r10) |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 310 | |
Haiying Wang | 181a365 | 2008-12-03 10:08:19 -0500 | [diff] [blame] | 311 | mtspr IVPR,r12 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 312 | /* |
| 313 | * Coming here, we know the cpu has one TLB mapping in TLB1[0] |
| 314 | * which maps 0xfffff000-0xffffffff one-to-one. We set up a |
| 315 | * second mapping that maps addr 1:1 for 64M, and then we jump to |
| 316 | * addr |
| 317 | */ |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 318 | lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h |
| 319 | mtspr SPRN_MAS0,r10 |
| 320 | lis r10,(MAS1_VALID|MAS1_IPROT)@h |
| 321 | ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l |
| 322 | mtspr SPRN_MAS1,r10 |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 323 | /* WIMGE = 0b00000 for now */ |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 324 | mtspr SPRN_MAS2,r12 |
| 325 | ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) |
| 326 | mtspr SPRN_MAS3,r12 |
| 327 | #ifdef CONFIG_ENABLE_36BIT_PHYS |
| 328 | mtspr SPRN_MAS7,r11 |
| 329 | #endif |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 330 | tlbwe |
| 331 | |
| 332 | /* Now we have another mapping for this page, so we jump to that |
| 333 | * mapping |
| 334 | */ |
Kumar Gala | 79679d8 | 2008-03-26 08:34:25 -0500 | [diff] [blame] | 335 | mtspr SPRN_SRR1,r13 |
| 336 | rfi |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 337 | |
Peter Tyser | 5ccd29c | 2009-10-23 15:55:47 -0500 | [diff] [blame] | 338 | /* |
| 339 | * Allocate some space for the SDRAM address of the bootpg. |
| 340 | * This variable has to be in the boot page so that it can |
| 341 | * be accessed by secondary cores when they come out of reset. |
| 342 | */ |
| 343 | .globl __bootpg_addr |
| 344 | __bootpg_addr: |
| 345 | .long 0 |
| 346 | |
Kumar Gala | cf6cc01 | 2008-04-28 02:24:04 -0500 | [diff] [blame] | 347 | .align L1_CACHE_SHIFT |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 348 | .globl __spin_table |
| 349 | __spin_table: |
Poonam Aggrwal | 0e87098 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 350 | .space CONFIG_MAX_CPUS*ENTRY_SIZE |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 351 | |
| 352 | /* Fill in the empty space. The actual reset vector is |
| 353 | * the last word of the page */ |
| 354 | __secondary_start_code_end: |
| 355 | .space 4092 - (__secondary_start_code_end - __secondary_start_page) |
| 356 | __secondary_reset_vector: |
| 357 | b __secondary_start_page |