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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 2c04d6ede41404aec0562365cfcb4b06eb6a9734 / arch / riscv / cpu
  1. 2b8dc36 andes: Unify naming policy for Andes related source by Leo Yu-Chi Liang · 7 months ago
  2. 19b762c board: starfive: Rename spl_soc_init() to spl_dram_init() by Lukas Funke · 7 months ago
  3. d6c81b8 board: sifive: Rename spl_soc_init() to spl_dram_init() by Lukas Funke · 7 months ago
  4. fd55792 riscv: andesv5: Set default cache line size to 64-bytes by Yu Chien Peter Lin · 8 months ago
  5. f39b1b7 riscv: support extension probing using riscv, isa-extensions by Conor Dooley · 9 months ago
  6. b90edde riscv: don't read riscv, isa in the riscv cpu's get_desc() by Conor Dooley · 9 months ago
  7. c21dfcb riscv: cache: Implement dcache for cv1800b by Kongyang Liu · 9 months ago
  8. ae800aa riscv: cpu: cv1800b: Add support for cv1800b SoC by Kongyang Liu · 9 months ago
  9. e4f6949 riscv: add backtrace support by Ben Dooks · 1 year, 3 months ago
  10. 0d95add riscv: cpu: improve multi-letter extension detection in supports_extension() by Conor Dooley · 9 months ago
  11. 61d5c54 andes: cpu: Enable cache and TLB ECC support by Leo Yu-Chi Liang · 11 months ago
  12. bf12bb9 andes: cpu: Enable memboost feature by Leo Yu-Chi Liang · 11 months ago
  13. b046904 andes: ae350: Implement cache switch via Kconfig by Leo Yu-Chi Liang · 11 months ago
  14. c35bfd0 riscv: Add a reset_cpu() function by Simon Glass · 12 months ago
  15. 3b00fab riscv: Align the trap handler to 64 bytes by Samuel Holland · 1 year, 1 month ago
  16. 0b9441a riscv: Remove common.h usage by Tom Rini · 1 year, 2 months ago
  17. 9385c9b riscv: remove dram_init_banksize() by Heinrich Schuchardt · 1 year, 2 months ago
  18. 8a0d5f2 riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode by Yu Chien Peter Lin · 1 year, 2 months ago
  19. ac89738 Merge branch 'next' by Tom Rini · 1 year, 2 months ago
  20. 59d2a7d riscv: Correct event usage for riscv_cpu_probe/setup by Tom Rini · 1 year, 3 months ago
  21. 68f446f riscv: Rework riscv_cpu_probe for current event macros by Tom Rini · 1 year, 3 months ago
  22. 64339bc riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT by Shengyu Qu · 1 year, 3 months ago
  23. ddec4ca Merge tag 'v2023.10-rc4' into next by Tom Rini · 1 year, 3 months ago
  24. f72d0d4 event: Convert existing spy records to simple by Simon Glass · 1 year, 3 months ago
  25. 1c55d62 riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback by Chanho Park · 1 year, 4 months ago
  26. d768dd8 common: return type board_get_usable_ram_top by Heinrich Schuchardt · 1 year, 4 months ago
  27. 47ed151 riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE by Shengyu Qu · 1 year, 4 months ago
  28. 6419f8e riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation by Shengyu Qu · 1 year, 4 months ago
  29. eca2d41 riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE by Minda Chen · 1 year, 4 months ago
  30. 6aabe22 riscv: define a cache line size for the generic CPU by Heinrich Schuchardt · 1 year, 4 months ago
  31. 28ff3f1 riscv: setup per-hart stack earlier by Bo Gan · 1 year, 6 months ago
  32. 9675d92 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · 1 year, 5 months ago
  33. 38d900b ram: starfive: Read memory size information from EEPROM by Yanhong Wang · 1 year, 6 months ago
  34. 4a3efd7 riscv: Fix alignment of RELA sections in the linker scripts by Bin Meng · 1 year, 5 months ago
  35. 55171ae dm: Emit the arch_cpu_init_dm() even only before relocation by Simon Glass · 1 year, 7 months ago
  36. 9a6569a riscv: Update alignment for some sections in linker scripts by Bin Meng · 1 year, 8 months ago
  37. 3f37baa riscv: spl: Remove relocation sections by Bin Meng · 1 year, 8 months ago
  38. 3c09ac2 riscv: Avoid updating the link register by Bin Meng · 1 year, 8 months ago
  39. 485f593 riscv: Change to use positive offset to access relocation entries by Bin Meng · 1 year, 8 months ago
  40. 0b1a3a2 riscv: Optimize loading relocation type by Bin Meng · 1 year, 8 months ago
  41. 883f553 riscv: Optimize source end address calculation in start.S by Bin Meng · 1 year, 8 months ago
  42. 2f5fad0 riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC by Yanhong Wang · 1 year, 8 months ago
  43. 2185341 riscv: cpu: jh7110: Add support for jh7110 SoC by Yanhong Wang · 1 year, 8 months ago
  44. 8900e2b riscv: Rename Andes cpu and board names by Leo Yu-Chi Liang · 1 year, 10 months ago
  45. 487c211 configs: ae350: Enable v5l2 cache for AE350 platforms in SPL by Yu Chien Peter Lin · 1 year, 10 months ago
  46. 600a708 riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL by Yu Chien Peter Lin · 1 year, 10 months ago
  47. d8a146d riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() by Yu Chien Peter Lin · 1 year, 10 months ago
  48. 55ca747 riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" by Leo Yu-Chi Liang · 1 year, 10 months ago
  49. 5b71b7b riscv: ax25: bypass malloc when spl fit boots from ram by Rick Chen · 1 year, 11 months ago
  50. c83f64b riscv: ae350: Enable CCTL_SUEN by Rick Chen · 1 year, 11 months ago
  51. 81b56a5 riscv: cpu: check U-Mode before counteren write by Nikita Shubin · 2 years ago
  52. c277c78 riscv: Fix detecting FPU support in standard extension by Yu Chien Peter Lin · 2 years, 1 month ago
  53. a5dfa3b riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · 2 years, 1 month ago
  54. ffa2c88 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next by Tom Rini · 2 years, 2 months ago
  55. e0465f8 riscv: Introduce AVAILABLE_HARTS by Rick Chen · 2 years, 2 months ago
  56. c2bdf02 spl: introduce SPL_XIP to config by Nikita Shubin · 2 years, 3 months ago
  57. 049704f board_f: Fix types for board_get_usable_ram_top() by Pali Rohár · 2 years, 3 months ago
  58. f451261 riscv: ae350: Fix XIP config boot failure by Leo Yu-Chi Liang · 2 years, 6 months ago
  59. a5041e3 riscv: cpu: set gp before board_init_f_init_reserve by Nikita Shubin · 2 years, 7 months ago
  60. 99e2fbc linker_lists: Rename sections to remove . prefix by Andrew Scull · 2 years, 6 months ago
  61. eaf6ea6 Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h by Tom Rini · 2 years, 6 months ago
  62. 7fe32b3 event: Convert arch_cpu_init_dm() to use events by Simon Glass · 2 years, 9 months ago
  63. c0ffc12 riscv: Enable SPI flash env for SiFive Unmatched. by Thomas Skibo · 3 years ago
  64. 2e8d2f8 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · 3 years, 2 months ago
  65. 1b2b52f riscv: ae350: enable Coherence Manager for ae350 by Leo Yu-Chi Liang · 3 years, 2 months ago
  66. 24ed531 sysreset: provide SBI based sysreset driver by Heinrich Schuchardt · 3 years, 3 months ago
  67. 835210a board: sifive: use ccache driver instead of helper function by Zong Li · 3 years, 3 months ago
  68. 662e300 riscv: cpu: fu740: Fix typo of date by Zong Li · 3 years, 4 months ago
  69. 975e7cf i2c: Rename SPL/TPL_I2C_SUPPORT to I2C by Simon Glass · 3 years, 5 months ago
  70. 564d630 riscv: sifive: fu740: Support i2c in spl by Zong Li · 3 years, 5 months ago
  71. e2172aa riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller by Zong Li · 3 years, 5 months ago
  72. c552deb riscv: cpu: fu740: clear feature disable CSR by Green Wan · 3 years, 6 months ago
  73. d56d79e drivers: clk: add fu740 support by Green Wan · 3 years, 6 months ago
  74. a74e9d8 riscv: cpu: fu740: Add support for cpu fu740 by Green Wan · 3 years, 6 months ago
  75. 236f2ec treewide: Convert macro and uses of __section(foo) to __section("foo") by Marek Behún · 3 years, 7 months ago
  76. 756eeba riscv: qemu: Switch to use binman to generate u-boot.itb by Bin Meng · 3 years, 7 months ago
  77. a6d7e8c riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · 3 years, 7 months ago
  78. ffdc71b Revert "riscv: cpu: fu740: clear feature disable CSR" by Bin Meng · 3 years, 7 months ago
  79. bc8bbb7 riscv: cpu: fu740: clear feature disable CSR by Green Wan · 3 years, 7 months ago
  80. edd9ad8 riscv: cpu: Add callback to init each core by Green Wan · 3 years, 7 months ago
  81. 529d5f9 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · 3 years, 9 months ago
  82. 2ae8043 Merge branch '2021-02-02-drop-asm_global_data-when-unused' by Tom Rini · 3 years, 10 months ago
  83. 85c714d riscv: Adjust board_get_usable_ram_top() for 32-bit by Bin Meng · 3 years, 10 months ago
  84. 401d1c4 common: Drop asm/global_data.h from common header by Simon Glass · 4 years, 1 month ago
  85. fb33eaa riscv: fix the wrong swap value register by Brad Kim · 4 years, 1 month ago
  86. f517e5f riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller by Pragnesh Patel · 4 years, 1 month ago
  87. 7dbebeb timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · 4 years, 1 month ago
  88. 924de32 riscv: Add some comments to start.S by Sean Anderson · 4 years, 2 months ago
  89. 8576813 riscv: Ensure gp is NULL or points to valid data by Sean Anderson · 4 years, 2 months ago
  90. 309995b riscv: Consolidate fences into AMOs for available_harts_lock by Sean Anderson · 4 years, 2 months ago
  91. 768502e riscv: Clear pending IPIs on initialization by Sean Anderson · 4 years, 2 months ago
  92. c410454 Revert "riscv: Clear pending interrupts before enabling IPIs" by Sean Anderson · 4 years, 2 months ago
  93. c33efaf riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · 4 years, 2 months ago
  94. 52dc7ae riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · 4 years, 4 months ago
  95. 6a43e3a riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · 4 years, 4 months ago
  96. ff8e88a riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · 4 years, 4 months ago
  97. d6a0170 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · 4 years, 4 months ago
  98. e491e15 riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · 4 years, 5 months ago
  99. ff7d25e env: Enable SPI flash env for SiFive FU540 by Jagan Teki · 4 years, 5 months ago
  100. a0018fc riscv: Make SiFive HiFive Unleashed board boot again by Bin Meng · 4 years, 5 months ago