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Wang Huan550e3dc2014-09-05 13:52:44 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <asm/io.h>
10#include <asm/arch/immap_ls102xa.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
Xiubo Li660673a2014-11-21 17:40:59 +080013#include <asm/arch/ls102xa_stream_id.h>
Yao Yuan7ba02612015-12-05 14:59:10 +080014#include <asm/arch/ls102xa_soc.h>
Zhuoyu Zhang03c22442015-08-17 18:55:12 +080015#include <asm/arch/ls102xa_devdis.h>
tang yuantian4632ad72015-10-16 16:06:05 +080016#include <asm/arch/ls102xa_sata.h>
Yao Yuanbca11bd2014-11-26 14:54:33 +080017#include <hwconfig.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080018#include <mmc.h>
Mingkai Hu435acd82015-10-26 19:47:41 +080019#include <fsl_csu.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080020#include <fsl_esdhc.h>
21#include <fsl_ifc.h>
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053022#include <fsl_sec.h>
Alison Wang86949c22014-12-03 15:00:47 +080023#include <spl.h>
Zhuoyu Zhang03c22442015-08-17 18:55:12 +080024#include <fsl_devdis.h>
Aneesh Bansald0412882016-01-22 16:37:26 +053025#include <fsl_validate.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080026
tang yuantian41ba57d2014-12-17 12:58:05 +080027#include "../common/sleep.h"
Wang Huan550e3dc2014-09-05 13:52:44 +080028#include "../common/qixis.h"
29#include "ls1021aqds_qixis.h"
Zhao Qiang63e75fd2014-09-26 16:25:32 +080030#ifdef CONFIG_U_QE
31#include "../../../drivers/qe/qe.h"
32#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080033
Yao Yuanbca11bd2014-11-26 14:54:33 +080034#define PIN_MUX_SEL_CAN 0x03
35#define PIN_MUX_SEL_IIC2 0xa0
36#define PIN_MUX_SEL_RGMII 0x00
37#define PIN_MUX_SEL_SAI 0x0c
38#define PIN_MUX_SEL_SDHC 0x00
39
40#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
41#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
Wang Huan550e3dc2014-09-05 13:52:44 +080042DECLARE_GLOBAL_DATA_PTR;
43
44enum {
Yao Yuanbca11bd2014-11-26 14:54:33 +080045 MUX_TYPE_CAN,
46 MUX_TYPE_IIC2,
47 MUX_TYPE_RGMII,
48 MUX_TYPE_SAI,
49 MUX_TYPE_SDHC,
Wang Huan550e3dc2014-09-05 13:52:44 +080050 MUX_TYPE_SD_PCI4,
51 MUX_TYPE_SD_PC_SA_SG_SG,
52 MUX_TYPE_SD_PC_SA_PC_SG,
53 MUX_TYPE_SD_PC_SG_SG,
54};
55
Alison Wang0f5e5572014-12-09 17:38:23 +080056enum {
57 GE0_CLK125,
58 GE2_CLK125,
59 GE1_CLK125,
60};
61
Wang Huan550e3dc2014-09-05 13:52:44 +080062int checkboard(void)
63{
Alison Wangd612f0a2014-12-09 17:38:02 +080064#ifndef CONFIG_QSPI_BOOT
Wang Huan550e3dc2014-09-05 13:52:44 +080065 char buf[64];
Alison Wangd612f0a2014-12-09 17:38:02 +080066#endif
Alison Wang86949c22014-12-03 15:00:47 +080067#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
Wang Huan550e3dc2014-09-05 13:52:44 +080068 u8 sw;
Alison Wang86949c22014-12-03 15:00:47 +080069#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080070
71 puts("Board: LS1021AQDS\n");
72
Alison Wang86949c22014-12-03 15:00:47 +080073#ifdef CONFIG_SD_BOOT
74 puts("SD\n");
75#elif CONFIG_QSPI_BOOT
76 puts("QSPI\n");
77#else
Wang Huan550e3dc2014-09-05 13:52:44 +080078 sw = QIXIS_READ(brdcfg[0]);
79 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
80
81 if (sw < 0x8)
82 printf("vBank: %d\n", sw);
83 else if (sw == 0x8)
84 puts("PromJet\n");
85 else if (sw == 0x9)
86 puts("NAND\n");
87 else if (sw == 0x15)
88 printf("IFCCard\n");
89 else
90 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
Alison Wang86949c22014-12-03 15:00:47 +080091#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080092
Alison Wangd612f0a2014-12-09 17:38:02 +080093#ifndef CONFIG_QSPI_BOOT
Wang Huan550e3dc2014-09-05 13:52:44 +080094 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
95 QIXIS_READ(id), QIXIS_READ(arch));
96
97 printf("FPGA: v%d (%s), build %d\n",
98 (int)QIXIS_READ(scver), qixis_read_tag(buf),
99 (int)qixis_read_minor());
Alison Wangd612f0a2014-12-09 17:38:02 +0800100#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800101
102 return 0;
103}
104
105unsigned long get_board_sys_clk(void)
106{
107 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
108
109 switch (sysclk_conf & 0x0f) {
110 case QIXIS_SYSCLK_64:
111 return 64000000;
112 case QIXIS_SYSCLK_83:
113 return 83333333;
114 case QIXIS_SYSCLK_100:
115 return 100000000;
116 case QIXIS_SYSCLK_125:
117 return 125000000;
118 case QIXIS_SYSCLK_133:
119 return 133333333;
120 case QIXIS_SYSCLK_150:
121 return 150000000;
122 case QIXIS_SYSCLK_160:
123 return 160000000;
124 case QIXIS_SYSCLK_166:
125 return 166666666;
126 }
127 return 66666666;
128}
129
130unsigned long get_board_ddr_clk(void)
131{
132 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
133
134 switch ((ddrclk_conf & 0x30) >> 4) {
135 case QIXIS_DDRCLK_100:
136 return 100000000;
137 case QIXIS_DDRCLK_125:
138 return 125000000;
139 case QIXIS_DDRCLK_133:
140 return 133333333;
141 }
142 return 66666666;
143}
144
Chenhui Zhaoafff1372014-11-06 10:51:59 +0800145int select_i2c_ch_pca9547(u8 ch)
146{
147 int ret;
148
149 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
150 if (ret) {
151 puts("PCA: failed to select proper channel\n");
152 return ret;
153 }
154
155 return 0;
156}
157
Wang Huan550e3dc2014-09-05 13:52:44 +0800158int dram_init(void)
159{
Chenhui Zhaoafff1372014-11-06 10:51:59 +0800160 /*
161 * When resuming from deep sleep, the I2C channel may not be
162 * in the default channel. So, switch to the default channel
163 * before accessing DDR SPD.
164 */
165 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
Wang Huan550e3dc2014-09-05 13:52:44 +0800166 gd->ram_size = initdram(0);
167
168 return 0;
169}
170
171#ifdef CONFIG_FSL_ESDHC
172struct fsl_esdhc_cfg esdhc_cfg[1] = {
173 {CONFIG_SYS_FSL_ESDHC_ADDR},
174};
175
176int board_mmc_init(bd_t *bis)
177{
178 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
179
180 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
181}
182#endif
183
Wang Huan550e3dc2014-09-05 13:52:44 +0800184int board_early_init_f(void)
185{
186 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
Wang Huan550e3dc2014-09-05 13:52:44 +0800187
188#ifdef CONFIG_TSEC_ENET
Claudiu Manoilebe4c1e2015-08-12 13:29:14 +0300189 /* clear BD & FR bits for BE BD's and frame data */
190 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
Wang Huan550e3dc2014-09-05 13:52:44 +0800191#endif
192
193#ifdef CONFIG_FSL_IFC
194 init_early_memctl_regs();
195#endif
196
Yao Yuan7ba02612015-12-05 14:59:10 +0800197 arch_soc_init();
Wang Huan550e3dc2014-09-05 13:52:44 +0800198
tang yuantian41ba57d2014-12-17 12:58:05 +0800199#if defined(CONFIG_DEEP_SLEEP)
200 if (is_warm_boot())
201 fsl_dp_disable_console();
202#endif
203
Wang Huan550e3dc2014-09-05 13:52:44 +0800204 return 0;
205}
206
Alison Wang86949c22014-12-03 15:00:47 +0800207#ifdef CONFIG_SPL_BUILD
208void board_init_f(ulong dummy)
209{
210 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
Alison Wang036f3f32015-03-12 11:31:44 +0800211 unsigned int major;
Alison Wang86949c22014-12-03 15:00:47 +0800212
Alison Wang8ab967b2014-12-09 17:38:14 +0800213#ifdef CONFIG_NAND_BOOT
214 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
215 u32 porsr1, pinctl;
216
217 /*
218 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
219 * NAND boot because IFC signals > IFC_AD7 are not enabled.
220 * This workaround changes RCW source to make all signals enabled.
221 */
222 porsr1 = in_be32(&gur->porsr1);
223 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
224 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
225 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
226 pinctl);
227#endif
228
Alison Wang86949c22014-12-03 15:00:47 +0800229 /* Clear the BSS */
230 memset(__bss_start, 0, __bss_end - __bss_start);
231
232#ifdef CONFIG_FSL_IFC
233 init_early_memctl_regs();
234#endif
235
236 get_clocks();
237
tang yuantian41ba57d2014-12-17 12:58:05 +0800238#if defined(CONFIG_DEEP_SLEEP)
239 if (is_warm_boot())
240 fsl_dp_disable_console();
241#endif
242
Alison Wang86949c22014-12-03 15:00:47 +0800243 preloader_console_init();
244
245#ifdef CONFIG_SPL_I2C_SUPPORT
246 i2c_init_all();
247#endif
Alison Wang036f3f32015-03-12 11:31:44 +0800248
249 major = get_soc_major_rev();
250 if (major == SOC_MAJOR_VER_1_0)
251 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
Alison Wang86949c22014-12-03 15:00:47 +0800252
253 dram_init();
254
Alison Wang8f0c7cb2015-07-09 10:50:07 +0800255 /* Allow OCRAM access permission as R/W */
Mingkai Hu435acd82015-10-26 19:47:41 +0800256#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
257 enable_layerscape_ns_access();
Alison Wang8f0c7cb2015-07-09 10:50:07 +0800258#endif
259
Alison Wang86949c22014-12-03 15:00:47 +0800260 board_init_r(NULL, 0);
261}
262#endif
263
Alison Wang0f5e5572014-12-09 17:38:23 +0800264void config_etseccm_source(int etsec_gtx_125_mux)
265{
266 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
267
268 switch (etsec_gtx_125_mux) {
269 case GE0_CLK125:
270 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
271 debug("etseccm set to GE0_CLK125\n");
272 break;
273
274 case GE2_CLK125:
275 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
276 debug("etseccm set to GE2_CLK125\n");
277 break;
278
279 case GE1_CLK125:
280 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
281 debug("etseccm set to GE1_CLK125\n");
282 break;
283
284 default:
285 printf("Error! trying to set etseccm to invalid value\n");
286 break;
287 }
288}
289
Wang Huan550e3dc2014-09-05 13:52:44 +0800290int config_board_mux(int ctrl_type)
291{
Yao Yuanbca11bd2014-11-26 14:54:33 +0800292 u8 reg12, reg14;
Wang Huan550e3dc2014-09-05 13:52:44 +0800293
294 reg12 = QIXIS_READ(brdcfg[12]);
Yao Yuanbca11bd2014-11-26 14:54:33 +0800295 reg14 = QIXIS_READ(brdcfg[14]);
Wang Huan550e3dc2014-09-05 13:52:44 +0800296
297 switch (ctrl_type) {
Yao Yuanbca11bd2014-11-26 14:54:33 +0800298 case MUX_TYPE_CAN:
Alison Wang0f5e5572014-12-09 17:38:23 +0800299 config_etseccm_source(GE2_CLK125);
Yao Yuanbca11bd2014-11-26 14:54:33 +0800300 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
301 break;
302 case MUX_TYPE_IIC2:
303 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
304 break;
305 case MUX_TYPE_RGMII:
306 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
307 break;
308 case MUX_TYPE_SAI:
Alison Wang0f5e5572014-12-09 17:38:23 +0800309 config_etseccm_source(GE2_CLK125);
Yao Yuanbca11bd2014-11-26 14:54:33 +0800310 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
311 break;
312 case MUX_TYPE_SDHC:
313 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
314 break;
Wang Huan550e3dc2014-09-05 13:52:44 +0800315 case MUX_TYPE_SD_PCI4:
316 reg12 = 0x38;
317 break;
318 case MUX_TYPE_SD_PC_SA_SG_SG:
319 reg12 = 0x01;
320 break;
321 case MUX_TYPE_SD_PC_SA_PC_SG:
322 reg12 = 0x01;
323 break;
324 case MUX_TYPE_SD_PC_SG_SG:
325 reg12 = 0x21;
326 break;
327 default:
328 printf("Wrong mux interface type\n");
329 return -1;
330 }
331
332 QIXIS_WRITE(brdcfg[12], reg12);
Yao Yuanbca11bd2014-11-26 14:54:33 +0800333 QIXIS_WRITE(brdcfg[14], reg14);
Wang Huan550e3dc2014-09-05 13:52:44 +0800334
335 return 0;
336}
337
338int config_serdes_mux(void)
339{
340 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
341 u32 cfg;
342
343 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
344 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
345
346 switch (cfg) {
347 case 0x0:
348 config_board_mux(MUX_TYPE_SD_PCI4);
349 break;
350 case 0x30:
351 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
352 break;
353 case 0x60:
354 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
355 break;
356 case 0x70:
357 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
358 break;
359 default:
360 printf("SRDS1 prtcl:0x%x\n", cfg);
361 break;
362 }
363
364 return 0;
365}
366
tang yuantian4632ad72015-10-16 16:06:05 +0800367#ifdef CONFIG_BOARD_LATE_INIT
368int board_late_init(void)
369{
370#ifdef CONFIG_SCSI_AHCI_PLAT
371 ls1021a_sata_init();
372#endif
Aneesh Bansald0412882016-01-22 16:37:26 +0530373#ifdef CONFIG_CHAIN_OF_TRUST
374 fsl_setenv_chain_of_trust();
375#endif
tang yuantian4632ad72015-10-16 16:06:05 +0800376
377 return 0;
378}
379#endif
380
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530381int misc_init_r(void)
382{
Yao Yuanbca11bd2014-11-26 14:54:33 +0800383 int conflict_flag;
384
385 /* some signals can not enable simultaneous*/
386 conflict_flag = 0;
387 if (hwconfig("sdhc"))
388 conflict_flag++;
389 if (hwconfig("iic2"))
390 conflict_flag++;
391 if (conflict_flag > 1) {
392 printf("WARNING: pin conflict !\n");
393 return 0;
394 }
395
396 conflict_flag = 0;
397 if (hwconfig("rgmii"))
398 conflict_flag++;
399 if (hwconfig("can"))
400 conflict_flag++;
401 if (hwconfig("sai"))
402 conflict_flag++;
403 if (conflict_flag > 1) {
404 printf("WARNING: pin conflict !\n");
405 return 0;
406 }
407
408 if (hwconfig("can"))
409 config_board_mux(MUX_TYPE_CAN);
410 else if (hwconfig("rgmii"))
411 config_board_mux(MUX_TYPE_RGMII);
412 else if (hwconfig("sai"))
413 config_board_mux(MUX_TYPE_SAI);
414
415 if (hwconfig("iic2"))
416 config_board_mux(MUX_TYPE_IIC2);
417 else if (hwconfig("sdhc"))
418 config_board_mux(MUX_TYPE_SDHC);
419
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800420#ifdef CONFIG_FSL_DEVICE_DISABLE
421 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
422#endif
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530423#ifdef CONFIG_FSL_CAAM
424 return sec_init();
425#endif
Yao Yuanbca11bd2014-11-26 14:54:33 +0800426 return 0;
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530427}
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530428
Alison Wang81335742015-01-16 17:21:34 +0800429struct liodn_id_table sec_liodn_tbl[] = {
430 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
431 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
432 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
433 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
434 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
435 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
436 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
437 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
438 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
439 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
440 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
441 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
442 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
443 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
444 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
445 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
446};
447
Xiubo Li660673a2014-11-21 17:40:59 +0800448struct smmu_stream_id dev_stream_id[] = {
449 { 0x100, 0x01, "ETSEC MAC1" },
450 { 0x104, 0x02, "ETSEC MAC2" },
451 { 0x108, 0x03, "ETSEC MAC3" },
452 { 0x10c, 0x04, "PEX1" },
453 { 0x110, 0x05, "PEX2" },
454 { 0x114, 0x06, "qDMA" },
455 { 0x118, 0x07, "SATA" },
456 { 0x11c, 0x08, "USB3" },
457 { 0x120, 0x09, "QE" },
458 { 0x124, 0x0a, "eSDHC" },
459 { 0x128, 0x0b, "eMA" },
460 { 0x14c, 0x0c, "2D-ACE" },
461 { 0x150, 0x0d, "USB2" },
462 { 0x18c, 0x0e, "DEBUG" },
463};
464
Wang Huan550e3dc2014-09-05 13:52:44 +0800465int board_init(void)
466{
467 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
Alison Wang036f3f32015-03-12 11:31:44 +0800468 unsigned int major;
Wang Huan550e3dc2014-09-05 13:52:44 +0800469
Alison Wang036f3f32015-03-12 11:31:44 +0800470 major = get_soc_major_rev();
471 if (major == SOC_MAJOR_VER_1_0) {
472 /* Set CCI-400 control override register to
473 * enable barrier transaction */
474 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
475 }
Wang Huan550e3dc2014-09-05 13:52:44 +0800476
477 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
478
479#ifndef CONFIG_SYS_FSL_NO_SERDES
480 fsl_serdes_init();
481 config_serdes_mux();
482#endif
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800483
Alison Wang81335742015-01-16 17:21:34 +0800484 ls1021x_config_caam_stream_id(sec_liodn_tbl,
485 ARRAY_SIZE(sec_liodn_tbl));
Xiubo Li660673a2014-11-21 17:40:59 +0800486 ls102xa_config_smmu_stream_id(dev_stream_id,
487 ARRAY_SIZE(dev_stream_id));
488
Mingkai Hu435acd82015-10-26 19:47:41 +0800489#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
490 enable_layerscape_ns_access();
Xiubo Lie87f3b32014-11-21 17:40:58 +0800491#endif
492
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800493#ifdef CONFIG_U_QE
494 u_qe_init();
495#endif
496
Wang Huan550e3dc2014-09-05 13:52:44 +0800497 return 0;
498}
499
tang yuantian41ba57d2014-12-17 12:58:05 +0800500#if defined(CONFIG_DEEP_SLEEP)
501void board_sleep_prepare(void)
502{
503 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
Alison Wang036f3f32015-03-12 11:31:44 +0800504 unsigned int major;
tang yuantian41ba57d2014-12-17 12:58:05 +0800505
Alison Wang036f3f32015-03-12 11:31:44 +0800506 major = get_soc_major_rev();
507 if (major == SOC_MAJOR_VER_1_0) {
508 /* Set CCI-400 control override register to
509 * enable barrier transaction */
510 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
511 }
512
tang yuantian41ba57d2014-12-17 12:58:05 +0800513
Mingkai Hu435acd82015-10-26 19:47:41 +0800514#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
515 enable_layerscape_ns_access();
tang yuantian41ba57d2014-12-17 12:58:05 +0800516#endif
517}
518#endif
519
Simon Glasse895a4b2014-10-23 18:58:47 -0600520int ft_board_setup(void *blob, bd_t *bd)
Wang Huan550e3dc2014-09-05 13:52:44 +0800521{
522 ft_cpu_setup(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600523
Minghuan Liand42bd342015-03-12 10:58:48 +0800524#ifdef CONFIG_PCI
525 ft_pci_setup(blob, bd);
Minghuan Lianda419022014-10-31 13:43:44 +0800526#endif
527
Simon Glasse895a4b2014-10-23 18:58:47 -0600528 return 0;
Wang Huan550e3dc2014-09-05 13:52:44 +0800529}
530
531u8 flash_read8(void *addr)
532{
533 return __raw_readb(addr + 1);
534}
535
536void flash_write16(u16 val, void *addr)
537{
538 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
539
540 __raw_writew(shftval, addr);
541}
542
543u16 flash_read16(void *addr)
544{
545 u16 val = __raw_readw(addr);
546
547 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
548}