Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Marvell SheevaPlug: Convert Ethernet and SATA to Driver Model (Tony)
- Zyxel NSA310S NAS: Convert to Driver Model (Tony)
- Turris_omnia: Add `u-boot-env` NOR partition (Marek)
- Turris_omnia: Fixup MTD partitions in Linux' DTB (Marek)
- Espressobin: Enable 'mtd' command and define SPI NOR partitions (Pali)
diff --git a/MAINTAINERS b/MAINTAINERS
index 34ed880..a6b49b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -513,6 +513,7 @@
F: drivers/phy/ti-pipe3-phy.c
F: drivers/ram/k3*
F: drivers/remoteproc/k3_system_controller.c
+F: drivers/remoteproc/pruc_rpoc.c
F: drivers/remoteproc/ti*
F: drivers/reset/reset-ti-sci.c
F: drivers/rtc/davinci.c
@@ -522,6 +523,7 @@
F: drivers/thermal/ti-bandgap.c
F: drivers/timer/omap-timer.c
F: drivers/watchdog/omap_wdt.c
+F: include/linux/pruss_driver.h
F: include/linux/soc/ti/
ARM U8500
diff --git a/Makefile b/Makefile
index bc404c8..ca2432c 100644
--- a/Makefile
+++ b/Makefile
@@ -1125,13 +1125,6 @@
@echo >&2 "See doc/driver-model/migration.rst for more info."
@echo >&2 "===================================================="
endif
- $(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\
- USB,v2019.07,$(CONFIG_USB))
- $(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI))
- $(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\
- $(CONFIG_LCD)$(CONFIG_VIDEO))
- $(call deprecated,CONFIG_DM_SPI_FLASH,SPI flash,v2019.07,\
- $(CONFIG_SPI_FLASH))
$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
$(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7f493a8..9de97cc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -984,7 +984,7 @@
select BINMAN
select CMD_GPIO
select CMD_MMC if MMC
- select CMD_USB if DISTRO_DEFAULTS
+ select CMD_USB if DISTRO_DEFAULTS && USB_HOST
select CLK
select DM
select DM_ETH
@@ -993,7 +993,6 @@
select DM_MMC if MMC
select DM_SCSI if SCSI
select DM_SERIAL
- select DM_USB if DISTRO_DEFAULTS
select GPIO_EXTRA_HEADER
select OF_BOARD_SETUP
select OF_CONTROL
@@ -1006,8 +1005,8 @@
select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
- select USB_KEYBOARD if DISTRO_DEFAULTS
- select USB_STORAGE if DISTRO_DEFAULTS
+ select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
+ select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
select SPL_USE_TINY_PRINTF
select USE_PREBOOT
select SYS_RELOC_GD_ENV_ADDR
@@ -1035,7 +1034,6 @@
select DM_GPIO
select DM_MMC if MMC
select DM_SERIAL
- select DM_USB if USB
select OF_CONTROL
select SYSRESET
select TIMER
@@ -1078,7 +1076,6 @@
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
- select DM_USB if USB
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPI
@@ -1122,7 +1119,6 @@
select DM_SERIAL
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
- select DM_USB if USB
select FIRMWARE
select GPIO_EXTRA_HEADER
select OF_CONTROL
@@ -1177,7 +1173,6 @@
select DM_ETH
select BLK
select USB
- select DM_USB
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
@@ -1343,7 +1338,6 @@
select ARM64
select DM
select DM_SERIAL
- select DM_USB
select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
@@ -1681,7 +1675,6 @@
select DM_SCSI
select DM_SERIAL
select DM_SPI
- select DM_USB
select GPIO_EXTRA_HEADER
select SPL_DM if SPL
select SPL_DM_SPI if SPL
@@ -1708,7 +1701,6 @@
select DM_MTD
select DM_RESET
select DM_SERIAL
- select DM_USB
select OF_BOARD_SETUP
select OF_CONTROL
select OF_LIBFDT
@@ -1809,7 +1801,6 @@
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
- select DM_USB if USB
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select SPI
diff --git a/arch/arm/dts/am335x-guardian-u-boot.dtsi b/arch/arm/dts/am335x-guardian-u-boot.dtsi
index 986f58e..a1a7913 100644
--- a/arch/arm/dts/am335x-guardian-u-boot.dtsi
+++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi
@@ -42,6 +42,17 @@
u-boot,dm-pre-reloc;
};
+&spi0 {
+ lcd0: display@0 {
+ compatible = "himax,hx8238d";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd0_pins>;
+ reg = <0>;
+ label = "lcd";
+ spi-max-frequency = <100000>;
+ };
+};
+
&uart0 {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts
index 7e70a96..69bee45 100644
--- a/arch/arm/dts/am335x-guardian.dts
+++ b/arch/arm/dts/am335x-guardian.dts
@@ -87,7 +87,7 @@
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
- bpp = <24>;
+ bpp = <16>;
bus-width = <16>;
fdd = <0x80>;
sync-edge = <0>;
@@ -247,6 +247,12 @@
&lcdc {
blue-and-red-wiring = "crossed";
status = "okay";
+
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <0>;
+ };
+ };
};
&mmc1 {
@@ -401,12 +407,12 @@
guardian_interface_pins: pinmux_guardian_interface_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
- AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7)
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 6b5ebec..c5af2ff 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -13,8 +13,16 @@
#size-cells = <1>;
ranges = <0x0 0x00 0x70000000 0x200000>;
- atf-sram@0 {
- reg = <0x1a0000 0x1c000>;
+ tfa-sram@1c0000 {
+ reg = <0x1c0000 0x20000>;
+ };
+
+ dmsc-sram@1e0000 {
+ reg = <0x1e0000 0x1c000>;
+ };
+
+ sproxy-sram@1fc000 {
+ reg = <0x1fc000 0x4000>;
};
};
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index cabdba8..669484b 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -926,4 +926,467 @@
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
clock-names = "tbclk", "fck";
};
+
+ icssg0: icssg@b000000 {
+ compatible = "ti,am654-icssg";
+ reg = <0x00 0xb000000 0x00 0x80000>;
+ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0xb000000 0x80000>;
+
+ icssg0_mem: memories@0 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x10000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ icssg0_cfg: cfg@26000 {
+ compatible = "ti,pruss-cfg", "syscon";
+ reg = <0x26000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg0_coreclk_mux: coreclk-mux@3c {
+ reg = <0x3c>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
+ <&k3_clks 62 3>; /* icssg0_iclk */
+ assigned-clocks = <&icssg0_coreclk_mux>;
+ assigned-clock-parents = <&k3_clks 62 3>;
+ };
+
+ icssg0_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
+ <&icssg0_coreclk_mux>; /* core_clk */
+ assigned-clocks = <&icssg0_iepclk_mux>;
+ assigned-clock-parents = <&icssg0_coreclk_mux>;
+ };
+ };
+ };
+
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_mii_rt: mii-rt@32000 {
+ compatible = "ti,pruss-mii", "syscon";
+ reg = <0x32000 0x100>;
+ };
+
+ icssg0_mii_g_rt: mii-g-rt@33000 {
+ compatible = "ti,pruss-mii-g", "syscon";
+ reg = <0x33000 0x1000>;
+ };
+
+ icssg0_intc: interrupt-controller@20000 {
+ compatible = "ti,icssg-intc";
+ reg = <0x20000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5",
+ "host_intr6", "host_intr7";
+ };
+
+ pru0_0: pru@34000 {
+ compatible = "ti,am654-pru";
+ reg = <0x34000 0x4000>,
+ <0x22000 0x100>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-pru0_0-fw";
+ };
+
+ rtu0_0: rtu@4000 {
+ compatible = "ti,am654-rtu";
+ reg = <0x4000 0x2000>,
+ <0x23000 0x100>,
+ <0x23400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-rtu0_0-fw";
+ };
+
+ tx_pru0_0: txpru@a000 {
+ compatible = "ti,am654-tx-pru";
+ reg = <0xa000 0x1800>,
+ <0x25000 0x100>,
+ <0x25400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-txpru0_0-fw";
+ };
+
+ pru0_1: pru@38000 {
+ compatible = "ti,am654-pru";
+ reg = <0x38000 0x4000>,
+ <0x24000 0x100>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-pru0_1-fw";
+ };
+
+ rtu0_1: rtu@6000 {
+ compatible = "ti,am654-rtu";
+ reg = <0x6000 0x2000>,
+ <0x23800 0x100>,
+ <0x23c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-rtu0_1-fw";
+ };
+
+ tx_pru0_1: txpru@c000 {
+ compatible = "ti,am654-tx-pru";
+ reg = <0xc000 0x1800>,
+ <0x25800 0x100>,
+ <0x25c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-txpru0_1-fw";
+ };
+
+ icssg0_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 62 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+ };
+
+ icssg1: icssg@b100000 {
+ compatible = "ti,am654-icssg";
+ reg = <0x00 0xb100000 0x00 0x80000>;
+ power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0xb100000 0x80000>;
+
+ icssg1_mem: memories@0 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x10000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ icssg1_cfg: cfg@26000 {
+ compatible = "ti,pruss-cfg", "syscon";
+ reg = <0x26000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg1_coreclk_mux: coreclk-mux@3c {
+ reg = <0x3c>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
+ <&k3_clks 63 3>; /* icssg1_iclk */
+ assigned-clocks = <&icssg1_coreclk_mux>;
+ assigned-clock-parents = <&k3_clks 63 3>;
+ };
+
+ icssg1_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
+ <&icssg1_coreclk_mux>; /* core_clk */
+ assigned-clocks = <&icssg1_iepclk_mux>;
+ assigned-clock-parents = <&icssg1_coreclk_mux>;
+ };
+ };
+ };
+
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_mii_rt: mii-rt@32000 {
+ compatible = "ti,pruss-mii", "syscon";
+ reg = <0x32000 0x100>;
+ };
+
+ icssg1_mii_g_rt: mii-g-rt@33000 {
+ compatible = "ti,pruss-mii-g", "syscon";
+ reg = <0x33000 0x1000>;
+ };
+
+ icssg1_intc: interrupt-controller@20000 {
+ compatible = "ti,icssg-intc";
+ reg = <0x20000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5",
+ "host_intr6", "host_intr7";
+ };
+
+ pru1_0: pru@34000 {
+ compatible = "ti,am654-pru";
+ reg = <0x34000 0x4000>,
+ <0x22000 0x100>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-pru1_0-fw";
+ };
+
+ rtu1_0: rtu@4000 {
+ compatible = "ti,am654-rtu";
+ reg = <0x4000 0x2000>,
+ <0x23000 0x100>,
+ <0x23400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-rtu1_0-fw";
+ };
+
+ tx_pru1_0: txpru@a000 {
+ compatible = "ti,am654-tx-pru";
+ reg = <0xa000 0x1800>,
+ <0x25000 0x100>,
+ <0x25400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-txpru1_0-fw";
+ };
+
+ pru1_1: pru@38000 {
+ compatible = "ti,am654-pru";
+ reg = <0x38000 0x4000>,
+ <0x24000 0x100>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-pru1_1-fw";
+ };
+
+ rtu1_1: rtu@6000 {
+ compatible = "ti,am654-rtu";
+ reg = <0x6000 0x2000>,
+ <0x23800 0x100>,
+ <0x23c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-rtu1_1-fw";
+ };
+
+ tx_pru1_1: txpru@c000 {
+ compatible = "ti,am654-tx-pru";
+ reg = <0xc000 0x1800>,
+ <0x25800 0x100>,
+ <0x25c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-txpru1_1-fw";
+ };
+
+ icssg1_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 63 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+ };
+
+ icssg2: icssg@b200000 {
+ compatible = "ti,am654-icssg";
+ reg = <0x00 0xb200000 0x00 0x80000>;
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0xb200000 0x80000>;
+
+ icssg2_mem: memories@0 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x10000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ icssg2_cfg: cfg@26000 {
+ compatible = "ti,pruss-cfg", "syscon";
+ reg = <0x26000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg2_coreclk_mux: coreclk-mux@3c {
+ reg = <0x3c>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
+ <&k3_clks 64 3>; /* icssg1_iclk */
+ assigned-clocks = <&icssg2_coreclk_mux>;
+ assigned-clock-parents = <&k3_clks 64 3>;
+ };
+
+ icssg2_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
+ <&icssg2_coreclk_mux>; /* core_clk */
+ assigned-clocks = <&icssg2_iepclk_mux>;
+ assigned-clock-parents = <&icssg2_coreclk_mux>;
+ };
+ };
+ };
+
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_mii_rt: mii-rt@32000 {
+ compatible = "ti,pruss-mii", "syscon";
+ reg = <0x32000 0x100>;
+ };
+
+ icssg2_mii_g_rt: mii-g-rt@33000 {
+ compatible = "ti,pruss-mii-g", "syscon";
+ reg = <0x33000 0x1000>;
+ };
+
+ icssg2_intc: interrupt-controller@20000 {
+ compatible = "ti,icssg-intc";
+ reg = <0x20000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5",
+ "host_intr6", "host_intr7";
+ };
+
+ pru2_0: pru@34000 {
+ compatible = "ti,am654-pru";
+ reg = <0x34000 0x4000>,
+ <0x22000 0x100>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-pru2_0-fw";
+ };
+
+ rtu2_0: rtu@4000 {
+ compatible = "ti,am654-rtu";
+ reg = <0x4000 0x2000>,
+ <0x23000 0x100>,
+ <0x23400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-rtu2_0-fw";
+ };
+
+ tx_pru2_0: txpru@a000 {
+ compatible = "ti,am654-tx-pru";
+ reg = <0xa000 0x1800>,
+ <0x25000 0x100>,
+ <0x25400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-txpru2_0-fw";
+ };
+
+ pru2_1: pru@38000 {
+ compatible = "ti,am654-pru";
+ reg = <0x38000 0x4000>,
+ <0x24000 0x100>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-pru2_1-fw";
+ };
+
+ rtu2_1: rtu@6000 {
+ compatible = "ti,am654-rtu";
+ reg = <0x6000 0x2000>,
+ <0x23800 0x100>,
+ <0x23c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-rtu2_1-fw";
+ };
+
+ tx_pru2_1: txpru@c000 {
+ compatible = "ti,am654-tx-pru";
+ reg = <0xc000 0x1800>,
+ <0x25800 0x100>,
+ <0x25c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-txpru2_1-fw";
+ };
+
+ icssg2_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 64 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+ };
+
};
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 2840258..df850a2 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -1,207 +1,78 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
*/
-#include <dt-bindings/pinctrl/k3.h>
-#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am654-r5-base-board-u-boot.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- aliases {
- serial2 = &main_uart0;
- ethernet0 = &cpsw_port1;
- usb0 = &usb0;
- usb1 = &usb1;
- spi0 = &ospi0;
- spi1 = &ospi1;
- };
+&pru0_0 {
+ remoteproc-name = "pru0_0";
};
-&cbass_main{
- u-boot,dm-spl;
- main-navss {
- u-boot,dm-spl;
- };
+&rtu0_0 {
+ remoteproc-name = "rtu0_0";
};
-&cbass_mcu {
- u-boot,dm-spl;
-
- mcu-navss {
- u-boot,dm-spl;
-
- ringacc@2b800000 {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- u-boot,dm-spl;
- ti,dma-ring-reset-quirk;
- };
-
- dma-controller@285c0000 {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- u-boot,dm-spl;
- };
- };
+&tx_pru0_0 {
+ remoteproc-name = "tx_pru0_0";
};
-&cbass_wakeup {
- u-boot,dm-spl;
-
- chipid@43000014 {
- u-boot,dm-spl;
- };
+&pru0_1 {
+ remoteproc-name = "pru0_1";
};
-&secure_proxy_main {
- u-boot,dm-spl;
+&rtu0_1 {
+ remoteproc-name = "rtu0_1";
};
-&dmsc {
- u-boot,dm-spl;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
- };
+&tx_pru0_1 {
+ remoteproc-name = "tx_pru0_1";
};
-&k3_pds {
- u-boot,dm-spl;
+&pru1_0 {
+ remoteproc-name = "pru1_0";
};
-&k3_clks {
- u-boot,dm-spl;
+&rtu1_0 {
+ remoteproc-name = "rtu1_0";
};
-&k3_reset {
- u-boot,dm-spl;
+&tx_pru1_0 {
+ remoteproc-name = "tx_pru1_0";
};
-&wkup_pmx0 {
- u-boot,dm-spl;
-
- wkup_i2c0_pins_default {
- u-boot,dm-spl;
- };
+&pru1_1 {
+ remoteproc-name = "pru1_1";
};
-&main_pmx0 {
- u-boot,dm-spl;
- usb0_pins_default: usb0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- u-boot,dm-spl;
- };
+&rtu1_1 {
+ remoteproc-name = "rtu1_1";
};
-&main_uart0_pins_default {
- u-boot,dm-spl;
+&tx_pru1_1 {
+ remoteproc-name = "tx_pru1_1";
};
-&main_pmx1 {
- u-boot,dm-spl;
+&pru2_0 {
+ remoteproc-name = "pru2_0";
};
-&wkup_pmx0 {
- mcu-fss0-ospi0-pins-default {
- u-boot,dm-spl;
- };
+&rtu2_0 {
+ remoteproc-name = "rtu2_0";
};
-&main_uart0 {
- u-boot,dm-spl;
+&tx_pru2_0 {
+ remoteproc-name = "tx_pru2_0";
};
-&main_mmc0_pins_default {
- u-boot,dm-spl;
+&pru2_1 {
+ remoteproc-name = "pru2_1";
};
-&main_mmc1_pins_default {
- u-boot,dm-spl;
+&rtu2_1 {
+ remoteproc-name = "rtu2_1";
};
-&sdhci0 {
- u-boot,dm-spl;
-};
-
-&sdhci1 {
- u-boot,dm-spl;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x2>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
-
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
-};
-
-&wkup_i2c0 {
- u-boot,dm-spl;
-};
-
-&usb1 {
- dr_mode = "peripheral";
-};
-
-&fss {
- u-boot,dm-spl;
-};
-
-&ospi0 {
- u-boot,dm-spl;
-
- flash@0{
- u-boot,dm-spl;
- };
-};
-
-&dwc3_0 {
- status = "okay";
- u-boot,dm-spl;
-};
-
-&usb0_phy {
- status = "okay";
- u-boot,dm-spl;
-};
-
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "host";
- u-boot,dm-spl;
-};
-
-&scm_conf {
- u-boot,dm-spl;
+&tx_pru2_1 {
+ remoteproc-name = "tx_pru2_1";
};
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
new file mode 100644
index 0000000..0f6df5b
--- /dev/null
+++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ aliases {
+ serial2 = &main_uart0;
+ ethernet0 = &cpsw_port1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ spi0 = &ospi0;
+ spi1 = &ospi1;
+ };
+};
+
+&cbass_main{
+ u-boot,dm-spl;
+ main-navss {
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu {
+ u-boot,dm-spl;
+
+ mcu-navss {
+ u-boot,dm-spl;
+
+ ringacc@2b800000 {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ u-boot,dm-spl;
+ ti,dma-ring-reset-quirk;
+ };
+
+ dma-controller@285c0000 {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&cbass_wakeup {
+ u-boot,dm-spl;
+
+ chipid@43000014 {
+ u-boot,dm-spl;
+ };
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&dmsc {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+
+ wkup_i2c0_pins_default {
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ usb0_pins_default: usb0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
+ >;
+ u-boot,dm-spl;
+ };
+};
+
+&main_uart0_pins_default {
+ u-boot,dm-spl;
+};
+
+&main_pmx1 {
+ u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+ mcu-fss0-ospi0-pins-default {
+ u-boot,dm-spl;
+ };
+};
+
+&main_uart0 {
+ u-boot,dm-spl;
+};
+
+&main_mmc0_pins_default {
+ u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+ u-boot,dm-spl;
+};
+
+&sdhci0 {
+ u-boot,dm-spl;
+};
+
+&sdhci1 {
+ u-boot,dm-spl;
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&mcu_cpsw {
+ reg = <0x0 0x46000000 0x0 0x200000>,
+ <0x0 0x40f00200 0x0 0x2>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@40f04040 {
+ compatible = "ti,am654-cpsw-phy-sel";
+ reg= <0x0 0x40f04040 0x0 0x4>;
+ reg-names = "gmii-sel";
+ };
+};
+
+&wkup_i2c0 {
+ u-boot,dm-spl;
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+};
+
+&fss {
+ u-boot,dm-spl;
+};
+
+&ospi0 {
+ u-boot,dm-spl;
+
+ flash@0{
+ u-boot,dm-spl;
+ };
+};
+
+&dwc3_0 {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+&usb0_phy {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_default>;
+ dr_mode = "host";
+ u-boot,dm-spl;
+};
+
+&scm_conf {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 087a3bb..24881c8 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -330,5 +330,3 @@
&scm_conf {
u-boot,dm-spl;
};
-
-#include "k3-am654-base-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 8dc1809..b1f9e71 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -89,6 +89,13 @@
<&mcu_secproxy 23>;
u-boot,dm-spl;
};
+
+ wkup_vtm0: vtm@42040000 {
+ compatible = "ti,am654-vtm", "ti,j721e-avs";
+ reg = <0x0 0x42040000 0x0 0x330>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
&dmsc {
@@ -239,6 +246,37 @@
ti,driver-strength-ohm = <50>;
};
+&wkup_i2c0 {
+ u-boot,dm-spl;
+ lp876441: lp876441@4c {
+ compatible = "ti,lp876441";
+ reg = <0x4c>;
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ regulators: regulators {
+ u-boot,dm-spl;
+ buck1_reg: buck1 {
+ /*VDD_CPU_AVS_REG*/
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+};
+
+&wkup_vtm0 {
+ vdd-supply-2 = <&buck1_reg>;
+ u-boot,dm-spl;
+};
+
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
diff --git a/arch/arm/include/asm/arch-am33xx/mem-guardian.h b/arch/arm/include/asm/arch-am33xx/mem-guardian.h
new file mode 100644
index 0000000..e864a0f
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mem-guardian.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * (C) Copyright 2020
+ * Robert Bosch Power Tools GmbH
+ *
+ * Author
+ * Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
+ *
+ * Copied from:
+ * arch/arm/include/asm/arch-am33xx/mem.h
+ *
+ * Initial Code from:
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ */
+
+#ifndef _MEM_GUARDIAN_H_
+#define _MEM_GUARDIAN_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. M_NAND - Micron Nand Flash
+ * x is GPMC config registers from 1 to 7 (there will be 7 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same.
+ *
+ * The following values are optimized for improving the NAND Read speed
+ * They are applicable and tested for Bosch Guardian Board.
+ * Read Speeds rose from 1.5MiBs to over 7.6MiBs
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ */
+#define GPMC_SIZE_256M 0x0
+#define GPMC_SIZE_128M 0x8
+#define GPMC_SIZE_64M 0xC
+#define GPMC_SIZE_32M 0xE
+#define GPMC_SIZE_16M 0xF
+
+#define M_NAND_GPMC_CONFIG1 0x00000800
+#define M_NAND_GPMC_CONFIG2 0x00030300
+#define M_NAND_GPMC_CONFIG3 0x00030300
+#define M_NAND_GPMC_CONFIG4 0x02000201
+#define M_NAND_GPMC_CONFIG5 0x00030303
+#define M_NAND_GPMC_CONFIG6 0x000000C0
+#define M_NAND_GPMC_CONFIG7 0x00000008
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS 8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG 7
+
+#define DBG_MPDB 6
+
+#endif /* endif _MEM_GUARDIAN_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 32ac033..a6e9ff8 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -59,8 +59,6 @@
u32 is_running_in_sram(void);
u32 is_running_in_flash(void);
u32 get_device_type(void);
-void secureworld_exit(void);
-void try_unlock_memory(void);
u32 get_boot_type(void);
void invalidate_dcache(u32);
u32 wait_on_value(u32, u32, void *, u32);
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 580b458..494e213 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -29,7 +29,6 @@
select DM_SERIAL
select DM_MMC
select BLK
- select DM_USB
select DM_REGULATOR
select MX53
imply CMD_DM
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 23cab39..a03eca8 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -239,7 +239,6 @@
select DM_MMC
select DM_PCI
select DM_SCSI
- select DM_USB
select DM_VIDEO
select OF_CONTROL
select SUPPORT_SPL
@@ -556,7 +555,6 @@
select DM_SERIAL
select DM_I2C
select DM_GPIO
- select DM_USB
select SUPPORT_SPL
select SPL_SEPARATE_BSS if SPL
imply CMD_DM
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 579dbac..0e46d70 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -141,7 +141,7 @@
void board_init_f(ulong dummy)
{
-#if defined(CONFIG_K3_LOAD_SYSFW)
+#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS)
struct udevice *dev;
int ret;
#endif
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 11e54cd..88cb957 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -94,7 +94,8 @@
select DM
select DM_SERIAL
select DM_GPIO
- select DM_USB
+ select DM_VIDEO
+ select DM_PANEL_HX8238D
config TARGET_AM335X_SL50
bool "Support am335x_sl50"
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 62178f1..4bf0535 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -23,7 +23,11 @@
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/i2c.h>
+#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
+#include <asm/arch/mem-guardian.h>
+#else
#include <asm/arch/mem.h>
+#endif
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c
index 50d5f3e..2dcf0cf 100644
--- a/arch/arm/mach-omap2/mem-common.c
+++ b/arch/arm/mach-omap2/mem-common.c
@@ -15,7 +15,11 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
+#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
+#include <asm/arch/mem-guardian.h>
+#else
#include <asm/arch/mem.h>
+#endif
#include <asm/arch/sys_proto.h>
#include <command.h>
#include <linux/mtd/omap_gpmc.h>
diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c
index 029bd54..363af52 100644
--- a/arch/arm/mach-omap2/omap3/board.c
+++ b/arch/arm/mach-omap2/omap3/board.c
@@ -71,12 +71,20 @@
#endif
+void early_system_init(void)
+{
+ hw_data_init();
+}
+
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+
/******************************************************************************
* Routine: secure_unlock
* Description: Setup security registers for access
* (GP Device only)
*****************************************************************************/
-void secure_unlock_mem(void)
+static void secure_unlock_mem(void)
{
struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
@@ -114,7 +122,7 @@
* configure secure registers and exit secure world
* general use.
*****************************************************************************/
-void secureworld_exit(void)
+static void secureworld_exit(void)
{
unsigned long i;
@@ -145,7 +153,7 @@
* Description: If chip is GP/EMU(special) type, unlock the SRAM for
* general use.
*****************************************************************************/
-void try_unlock_memory(void)
+static void try_unlock_memory(void)
{
int mode;
int in_sdram = is_running_in_sdram();
@@ -174,13 +182,6 @@
return;
}
-void early_system_init(void)
-{
- hw_data_init();
-}
-
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index cf45d78..1ab37cc 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -53,12 +53,6 @@
select DM_SERIAL
bool
-config MCF5445x
- select OF_CONTROL
- select DM
- select DM_SERIAL
- bool
-
config MCF5227x
select OF_CONTROL
select DM
@@ -119,26 +113,10 @@
bool
select MCF5441x
-config M54451
- bool
- select MCF5445x
-
-config M54455
- bool
- select MCF5445x
-
-config M52277
- bool
- select MCF5227x
-
choice
prompt "Target select"
optional
-config TARGET_M52277EVB
- bool "Support M52277EVB"
- select M52277
-
config TARGET_M5235EVB
bool "Support M5235EVB"
select M5235
@@ -191,18 +169,6 @@
bool "Support M5373EVB"
select M5373
-config TARGET_M54418TWR
- bool "Support M54418TWR"
- select M54418
-
-config TARGET_M54451EVB
- bool "Support M54451EVB"
- select M54451
-
-config TARGET_M54455EVB
- bool "Support M54455EVB"
- select M54455
-
config TARGET_AMCORE
bool "Support AMCORE"
select M5307
@@ -217,7 +183,6 @@
source "board/astro/mcf5373l/Kconfig"
source "board/cobra5272/Kconfig"
source "board/freescale/m5208evbe/Kconfig"
-source "board/freescale/m52277evb/Kconfig"
source "board/freescale/m5235evb/Kconfig"
source "board/freescale/m5249evb/Kconfig"
source "board/freescale/m5253demo/Kconfig"
@@ -227,9 +192,6 @@
source "board/freescale/m53017evb/Kconfig"
source "board/freescale/m5329evb/Kconfig"
source "board/freescale/m5373evb/Kconfig"
-source "board/freescale/m54418twr/Kconfig"
-source "board/freescale/m54451evb/Kconfig"
-source "board/freescale/m54455evb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 86b36e1..63f1810 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -18,13 +18,11 @@
cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC
cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC
cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC
-cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC
PLATFORM_CPPFLAGS += $(cpuflags-y)
ldflags-$(CONFIG_MCF5441x) := --got=single
-ldflags-$(CONFIG_MCF5445x) := --got=single
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 9deab51..9b3f9f0 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -73,13 +73,6 @@
{
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN |
- GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *)MMAP_PM;
@@ -212,36 +205,6 @@
#endif
#endif /* CONFIG_MCF5441x */
-#ifdef CONFIG_MCF5445x
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-
- out_be32(&scm1->mpr, 0x77777777);
- out_be32(&scm1->pacra, 0);
- out_be32(&scm1->pacrb, 0);
- out_be32(&scm1->pacrc, 0);
- out_be32(&scm1->pacrd, 0);
- out_be32(&scm1->pacre, 0);
- out_be32(&scm1->pacrf, 0);
- out_be32(&scm1->pacrg, 0);
-
- /* FlexBus */
- out_8(&gpio->par_be,
- GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
- GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
- out_8(&gpio->par_fbctl,
- GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
- GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#ifdef CONFIG_CF_SPI
- cfspi_port_conf();
-#endif
-
-#ifdef CONFIG_SYS_FSL_I2C
- out_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-#endif /* CONFIG_MCF5445x */
-
/* FlexBus Chipselect */
init_fbcs();
@@ -365,40 +328,6 @@
GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
break;
#endif
-#ifdef CONFIG_MCF5445x
- case 0:
- clrbits_8(&gpio->par_uart,
- GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
- setbits_8(&gpio->par_uart,
- GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
- break;
- case 1:
-#ifdef CONFIG_SYS_UART1_PRI_GPIO
- clrbits_8(&gpio->par_uart,
- GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
- setbits_8(&gpio->par_uart,
- GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
- clrbits_be16(&gpio->par_ssi,
- ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
- setbits_be16(&gpio->par_ssi,
- GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
-#endif
- break;
- case 2:
-#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
- clrbits_8(&gpio->par_timer,
- ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
- setbits_8(&gpio->par_timer,
- GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
-#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
- clrbits_8(&gpio->par_timer,
- ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
- setbits_8(&gpio->par_timer,
- GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
-#endif
- break;
-#endif /* CONFIG_MCF5445x */
}
}
@@ -411,46 +340,6 @@
if (fec_get_base_addr(0, &fec0_base))
return -1;
-#ifdef CONFIG_MCF5445x
- if (setclear) {
-#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
- if (info->iobase == fec0_base)
- setbits_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_MDC0_MDC0 |
- GPIO_PAR_FECI2C_MDIO0_MDIO0);
- else
- setbits_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_MDC1_MDC1 |
- GPIO_PAR_FECI2C_MDIO1_MDIO1);
-#else
- setbits_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-#endif
-
- if (info->iobase == fec0_base)
- setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
- else
- setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
- } else {
- clrbits_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-
- if (info->iobase == fec0_base) {
-#ifdef CONFIG_SYS_FEC_FULL_MII
- setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
-#else
- clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
-#endif
- } else {
-#ifdef CONFIG_SYS_FEC_FULL_MII
- setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
-#else
- clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
-#endif
- }
- }
-#endif /* CONFIG_MCF5445x */
-
#ifdef CONFIG_MCF5441x
if (setclear) {
out_8(&gpio->par_fec, 0x03);
diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c
index b0e2f2c..456af17 100644
--- a/arch/m68k/cpu/mcf5445x/dspi.c
+++ b/arch/m68k/cpu/mcf5445x/dspi.c
@@ -15,30 +15,6 @@
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
#ifdef CONFIG_MCF5441x
switch (cs) {
case 0:
@@ -61,25 +37,6 @@
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
#ifdef CONFIG_MCF5441x
if (cs == 1)
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index a0b9af8..eb73da6 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -42,11 +42,6 @@
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
-#ifdef CONFIG_MCF5445x
- /* Apply the divider to the system clock */
- clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
-#endif
-
/* Enable Limp Mode */
setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}
@@ -127,154 +122,12 @@
}
#endif
-#ifdef CONFIG_MCF5445x
-void setup_5445x_clocks(void)
-{
- ccm_t *ccm = (ccm_t *)MMAP_CCM;
- pll_t *pll = (pll_t *)MMAP_PLL;
- int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
- int pllmult_pci[] = { 12, 6, 16, 8 };
- int vco = 0, temp, fbtemp, pcrvalue;
- int *pPllmult = NULL;
- u16 fbpll_mask;
-#ifdef CONFIG_PCI
- int bPci;
-#endif
-
-#ifdef CONFIG_M54455EVB
- u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
-#endif
- u8 bootmode;
-
- /* To determine PCI is present or not */
- if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
- ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
- pPllmult = &pllmult_pci[0];
- fbpll_mask = 3; /* 11b */
-#ifdef CONFIG_PCI
- bPci = 1;
-#endif
- } else {
- pPllmult = &pllmult_nopci[0];
- fbpll_mask = 7; /* 111b */
-#ifdef CONFIG_PCI
- gd->pci_clk = 0;
- bPci = 0;
-#endif
- }
-
-#ifdef CONFIG_M54455EVB
- bootmode = (in_8(cpld) & 0x03);
-
- if (bootmode != 3) {
- /* Temporary read from CCR- fixed fb issue, must be the same clock
- as pci or input clock, causing cpld/fpga read inconsistancy */
- fbtemp = pPllmult[ccm->ccr & fbpll_mask];
-
- /* Break down into small pieces, code still in flex bus */
- pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
- temp = fbtemp - 1;
- pcrvalue |= PLL_PCR_OUTDIV3(temp);
-
- out_be32(&pll->pcr, pcrvalue);
- }
-#endif
-#ifdef CONFIG_M54451EVB
- /* No external logic to read the bootmode, hard coded from built */
-#ifdef CONFIG_CF_SBF
- bootmode = 3;
-#else
- bootmode = 2;
-
- /* default value is 16 mul, set to 20 mul */
- pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
- out_be32(&pll->pcr, pcrvalue);
- while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
- ;
-#endif
-#endif
-
- if (bootmode == 0) {
- /* RCON mode */
- vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
-
- if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
- /* invaild range, re-set in PCR */
- int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
- int i, j, bus;
-
- j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
- for (i = j; i < 0xFF; i++) {
- vco = i * CONFIG_SYS_INPUT_CLKSRC;
- if (vco >= CLOCK_PLL_FVCO_MIN) {
- bus = vco / temp;
- if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
- continue;
- else
- break;
- }
- }
- pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
- fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
- pcrvalue |= ((i << 24) | fbtemp);
-
- out_be32(&pll->pcr, pcrvalue);
- }
- gd->arch.vco_clk = vco; /* Vco clock */
- } else if (bootmode == 2) {
- /* Normal mode */
- vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
- /* Default value */
- pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
- pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
- out_be32(&pll->pcr, pcrvalue);
- vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- }
- gd->arch.vco_clk = vco; /* Vco clock */
- } else if (bootmode == 3) {
- /* serial mode */
- vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- gd->arch.vco_clk = vco; /* Vco clock */
- }
-
- if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
- /* Limp mode */
- } else {
- gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
-
- temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
- gd->cpu_clk = vco / temp; /* cpu clock */
-
- temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
- gd->bus_clk = vco / temp; /* bus clock */
-
- temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
- gd->arch.flb_clk = vco / temp; /* FlexBus clock */
-
-#ifdef CONFIG_PCI
- if (bPci) {
- temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
- gd->pci_clk = vco / temp; /* PCI clock */
- }
-#endif
- }
-
-#ifdef CONFIG_SYS_I2C_FSL
- gd->arch.i2c1_clk = gd->bus_clk;
-#endif
-}
-#endif
-
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
#ifdef CONFIG_MCF5441x
setup_5441x_clocks();
#endif
-#ifdef CONFIG_MCF5445x
- setup_5445x_clocks();
-#endif
#ifdef CONFIG_SYS_FSL_I2C
gd->arch.i2c1_clk = gd->bus_clk;
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index 80eb287..7007d78 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -202,10 +202,6 @@
move.b #0x80, (%a2)
#endif
-#ifdef CONFIG_MCF5445x
- move.l #0xFC0A4063, %a0
- move.b #0x7F, (%a0)
-#endif
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
@@ -214,9 +210,6 @@
#ifdef CONFIG_MCF5441x
move.l #0x3E000016, (%a0)
#endif
-#ifdef CONFIG_MCF5445x
- move.l #0x3E000011, (%a0)
-#endif
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
diff --git a/arch/m68k/dts/M52277EVB.dts b/arch/m68k/dts/M52277EVB.dts
deleted file mode 100644
index a2210c8..0000000
--- a/arch/m68k/dts/M52277EVB.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5227x.dtsi"
-
-/ {
- model = "Freescale M52277EVB";
- compatible = "fsl,M52277EVB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
diff --git a/arch/m68k/dts/M52277EVB_stmicro.dts b/arch/m68k/dts/M52277EVB_stmicro.dts
deleted file mode 100644
index 5fd3ca5..0000000
--- a/arch/m68k/dts/M52277EVB_stmicro.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5227x.dtsi"
-
-/ {
- model = "Freescale M52277_stmicro";
- compatible = "fsl,M52277_stmicro";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
diff --git a/arch/m68k/dts/M54418TWR.dts b/arch/m68k/dts/M54418TWR.dts
deleted file mode 100644
index 058707f..0000000
--- a/arch/m68k/dts/M54418TWR.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR";
- compatible = "fsl,M54418TWR";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_nand_mii.dts b/arch/m68k/dts/M54418TWR_nand_mii.dts
deleted file mode 100644
index 8afcb0f..0000000
--- a/arch/m68k/dts/M54418TWR_nand_mii.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_nand_mii";
- compatible = "fsl,M54418TWR_nand_mii";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_nand_rmii.dts b/arch/m68k/dts/M54418TWR_nand_rmii.dts
deleted file mode 100644
index fc2eb5b..0000000
--- a/arch/m68k/dts/M54418TWR_nand_rmii.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_nand_rmii";
- compatible = "fsl,M54418TWR_nand_rmii";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
deleted file mode 100644
index a39d102..0000000
--- a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_nand_rmii_lowfreq";
- compatible = "fsl,M54418TWR_nand_rmii_lowfreq";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_serial_mii.dts b/arch/m68k/dts/M54418TWR_serial_mii.dts
deleted file mode 100644
index edf98db..0000000
--- a/arch/m68k/dts/M54418TWR_serial_mii.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_serial_mii";
- compatible = "fsl,M54418TWR_serial_mii";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_serial_rmii.dts b/arch/m68k/dts/M54418TWR_serial_rmii.dts
deleted file mode 100644
index e4639fe..0000000
--- a/arch/m68k/dts/M54418TWR_serial_rmii.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_serial_rmii";
- compatible = "fsl,M54418TWR_serial_rmii";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts
deleted file mode 100644
index b81d37a..0000000
--- a/arch/m68k/dts/M54451EVB.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54451EVB";
- compatible = "fsl,M54451EVB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
-};
diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts
deleted file mode 100644
index 6645b58..0000000
--- a/arch/m68k/dts/M54451EVB_stmicro.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54451EVB_stmicro";
- compatible = "fsl,M54451EVB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
-};
diff --git a/arch/m68k/dts/M54455EVB.dts b/arch/m68k/dts/M54455EVB.dts
deleted file mode 100644
index b0ffb51..0000000
--- a/arch/m68k/dts/M54455EVB.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB";
- compatible = "fsl,M54455EVB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54455EVB_a66.dts b/arch/m68k/dts/M54455EVB_a66.dts
deleted file mode 100644
index c2557bd..0000000
--- a/arch/m68k/dts/M54455EVB_a66.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB_a66";
- compatible = "fsl,M54455EVB_a66";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54455EVB_i66.dts b/arch/m68k/dts/M54455EVB_i66.dts
deleted file mode 100644
index 3c9161b..0000000
--- a/arch/m68k/dts/M54455EVB_i66.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB_i66";
- compatible = "fsl,M54455EVB_i66";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54455EVB_intel.dts b/arch/m68k/dts/M54455EVB_intel.dts
deleted file mode 100644
index 54209d2..0000000
--- a/arch/m68k/dts/M54455EVB_intel.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB_intel";
- compatible = "fsl,M5275EVB_intel";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54455EVB_stm33.dts b/arch/m68k/dts/M54455EVB_stm33.dts
deleted file mode 100644
index 701b9a7..0000000
--- a/arch/m68k/dts/M54455EVB_stm33.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB_stm33";
- compatible = "fsl,M5275EVB_stm33";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile
index 47260a1..fdd435b 100644
--- a/arch/m68k/dts/Makefile
+++ b/arch/m68k/dts/Makefile
@@ -1,7 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \
- M52277EVB_stmicro.dtb
dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \
M5235EVB_Flash32.dtb
dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb
@@ -17,19 +15,6 @@
dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb
dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
-dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \
- M54418TWR_nand_mii.dtb \
- M54418TWR_nand_rmii.dtb \
- M54418TWR_serial_mii.dtb \
- M54418TWR_serial_rmii.dtb \
- M54418TWR_nand_rmii_lowfreq.dtb
-dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
- M54451EVB_stmicro.dtb
-dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
- M54455EVB_intel.dtb \
- M54455EVB_stm33.dtb \
- M54455EVB_a66.dtb \
- M54455EVB_i66.dtb
dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi
deleted file mode 100644
index 8c95edd..0000000
--- a/arch/m68k/dts/mcf5227x.dtsi
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/ {
- compatible = "fsl,mcf5227x";
-
- aliases {
- serial0 = &uart0;
- spi0 = &dspi0;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
-
- uart0: uart@fc060000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc060000 0x40>;
- status = "disabled";
- };
-
- uart1: uart@fc064000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc064000 0x40>;
- status = "disabled";
- };
-
- uart2: uart@fc068000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc068000 0x40>;
- status = "disabled";
- };
-
- dspi0: dspi@fc05c000 {
- compatible = "fsl,mcf-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfc05c000 0x100>;
- spi-max-frequency = <50000000>;
- num-cs = <4>;
- spi-mode = <0>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi
deleted file mode 100644
index b7ecc99..0000000
--- a/arch/m68k/dts/mcf5445x.dtsi
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/ {
- compatible = "fsl,mcf5445x";
-
- aliases {
- serial0 = &uart0;
- spi0 = &dspi0;
- fec0 = &fec0;
- fec1 = &fec1;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
-
- uart0: uart@fc060000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc060000 0x40>;
- status = "disabled";
- };
-
- uart1: uart@fc064000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc064000 0x40>;
- status = "disabled";
- };
-
- uart2: uart@fc068000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc068000 0x40>;
- status = "disabled";
- };
-
- dspi0: dspi@fc05c000 {
- compatible = "fsl,mcf-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfc05c000 0x100>;
- spi-max-frequency = <50000000>;
- num-cs = <4>;
- spi-mode = <0>;
- status = "disabled";
- };
-
- fec0: ethernet@fc030000 {
- compatible = "fsl,mcf-fec";
- reg = <0xfc030000 0x4000>;
- mii-base = <0>;
- max-speed = <100>;
- timeout-loop = <50000>;
- status = "disabled";
- };
-
- fec1: ethernet@fc034000 {
- compatible = "fsl,mcf-fec";
- reg = <0xfc034000 0x4000>;
- mii-base = <1>;
- max-speed = <100>;
- timeout-loop = <50000>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index fabec0a..ceb462f 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -10,7 +10,7 @@
#define __CACHE_H
#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
- defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
+ defined(CONFIG_MCF52x2)
#define CONFIG_CF_V2
#endif
@@ -19,9 +19,7 @@
#define CONFIG_CF_V3
#endif
-#if defined(CONFIG_MCF5445x)
-#define CONFIG_CF_V4
-#elif defined(CONFIG_MCF5441x)
+#if defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
#endif
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index cabdb0f..02aa95a 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -32,34 +32,6 @@
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M520x */
-#ifdef CONFIG_M52277
-#include <asm/immap_5227x.h>
-#include <asm/m5227x.h>
-
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
-
-#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
-
-#ifdef CONFIG_LCD
-#define CONFIG_SYS_LCD_BASE (MMAP_LCD)
-#endif
-
-/* Timer */
-#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (6)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
-#endif
-
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
-#endif /* CONFIG_M52277 */
-
#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>
@@ -330,42 +302,6 @@
#endif /* CONFIG_M54418 */
-#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
-#include <asm/immap_5445x.h>
-#include <asm/m5445x.h>
-
-#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
-#if defined(CONFIG_M54455EVB)
-#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#endif
-
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
-
-#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
-
-/* Timer */
-#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (6)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
-#endif
-
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
-
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
-#endif
-#endif /* CONFIG_M54451 || CONFIG_M54455 */
-
#ifdef CONFIG_M547x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
diff --git a/arch/m68k/include/asm/immap_5227x.h b/arch/m68k/include/asm/immap_5227x.h
deleted file mode 100644
index 710d6f5..0000000
--- a/arch/m68k/include/asm/immap_5227x.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5227x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __IMMAP_5227X__
-#define __IMMAP_5227X__
-
-/* Module Base Addresses */
-#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000)
-#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000)
-#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010)
-#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070)
-#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
-#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000)
-#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000)
-#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000)
-#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800)
-#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00)
-#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000)
-#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100)
-#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140)
-#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
-#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
-
-#include <asm/coldfire/crossbar.h>
-#include <asm/coldfire/dspi.h>
-#include <asm/coldfire/edma.h>
-#include <asm/coldfire/eport.h>
-#include <asm/coldfire/flexbus.h>
-#include <asm/coldfire/flexcan.h>
-#include <asm/coldfire/intctrl.h>
-#include <asm/coldfire/lcd.h>
-#include <asm/coldfire/pwm.h>
-#include <asm/coldfire/ssi.h>
-
-/* Reset Controller Module (RCM) */
-typedef struct rcm {
- u8 rcr;
- u8 rsr;
-} rcm_t;
-
-/* Chip Configuration Module (CCM) */
-typedef struct ccm {
- u16 ccr; /* Chip Configuration (Rd-only) */
- u16 resv1;
- u16 rcon; /* Reset Configuration (Rd-only) */
- u16 cir; /* Chip Identification (Rd-only) */
- u32 resv2;
- u16 misccr; /* Miscellaneous Control */
- u16 cdr; /* Clock Divider */
- u16 uocsr; /* USB On-the-Go Controller Status */
- u16 resv4;
- u16 sbfsr; /* Serial Boot Status */
- u16 sbfcr; /* Serial Boot Control */
-} ccm_t;
-
-typedef struct canex_ctrl {
- can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
- u32 res0[0x700]; /* 0x100 */
- can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
-} canex_t;
-
-/* General Purpose I/O Module (GPIO) */
-typedef struct gpio {
- /* Port Output Data Registers */
- u8 podr_be; /* 0x00 */
- u8 podr_cs; /* 0x01 */
- u8 podr_fbctl; /* 0x02 */
- u8 podr_i2c; /* 0x03 */
- u8 rsvd1; /* 0x04 */
- u8 podr_uart; /* 0x05 */
- u8 podr_dspi; /* 0x06 */
- u8 podr_timer; /* 0x07 */
- u8 podr_lcdctl; /* 0x08 */
- u8 podr_lcddatah; /* 0x09 */
- u8 podr_lcddatam; /* 0x0A */
- u8 podr_lcddatal; /* 0x0B */
-
- /* Port Data Direction Registers */
- u8 pddr_be; /* 0x0C */
- u8 pddr_cs; /* 0x0D */
- u8 pddr_fbctl; /* 0x0E */
- u8 pddr_i2c; /* 0x0F */
- u8 rsvd2; /* 0x10 */
- u8 pddr_uart; /* 0x11 */
- u8 pddr_dspi; /* 0x12 */
- u8 pddr_timer; /* 0x13 */
- u8 pddr_lcdctl; /* 0x14 */
- u8 pddr_lcddatah; /* 0x15 */
- u8 pddr_lcddatam; /* 0x16 */
- u8 pddr_lcddatal; /* 0x17 */
-
- /* Port Pin Data/Set Data Registers */
- u8 ppdsdr_be; /* 0x18 */
- u8 ppdsdr_cs; /* 0x19 */
- u8 ppdsdr_fbctl; /* 0x1A */
- u8 ppdsdr_i2c; /* 0x1B */
- u8 rsvd3; /* 0x1C */
- u8 ppdsdr_uart; /* 0x1D */
- u8 ppdsdr_dspi; /* 0x1E */
- u8 ppdsdr_timer; /* 0x1F */
- u8 ppdsdr_lcdctl; /* 0x20 */
- u8 ppdsdr_lcddatah; /* 0x21 */
- u8 ppdsdr_lcddatam; /* 0x22 */
- u8 ppdsdr_lcddatal; /* 0x23 */
-
- /* Port Clear Output Data Registers */
- u8 pclrr_be; /* 0x24 */
- u8 pclrr_cs; /* 0x25 */
- u8 pclrr_fbctl; /* 0x26 */
- u8 pclrr_i2c; /* 0x27 */
- u8 rsvd4; /* 0x28 */
- u8 pclrr_uart; /* 0x29 */
- u8 pclrr_dspi; /* 0x2A */
- u8 pclrr_timer; /* 0x2B */
- u8 pclrr_lcdctl; /* 0x2C */
- u8 pclrr_lcddatah; /* 0x2D */
- u8 pclrr_lcddatam; /* 0x2E */
- u8 pclrr_lcddatal; /* 0x2F */
-
- /* Pin Assignment Registers */
- u8 par_be; /* 0x30 */
- u8 par_cs; /* 0x31 */
- u8 par_fbctl; /* 0x32 */
- u8 par_i2c; /* 0x33 */
- u16 par_uart; /* 0x34 */
- u8 par_dspi; /* 0x36 */
- u8 par_timer; /* 0x37 */
- u8 par_lcdctl; /* 0x38 */
- u8 par_irq; /* 0x39 */
- u16 rsvd6; /* 0x3A - 0x3B */
- u32 par_lcdh; /* 0x3C */
- u32 par_lcdl; /* 0x40 */
-
- /* Mode select control registers */
- u8 mscr_fb; /* 0x44 */
- u8 mscr_sdram; /* 0x45 */
-
- u16 rsvd7; /* 0x46 - 0x47 */
- u8 dscr_dspi; /* 0x48 */
- u8 dscr_timer; /* 0x49 */
- u8 dscr_i2c; /* 0x4A */
- u8 dscr_lcd; /* 0x4B */
- u8 dscr_debug; /* 0x4C */
- u8 dscr_clkrst; /* 0x4D */
- u8 dscr_irq; /* 0x4E */
- u8 dscr_uart; /* 0x4F */
-} gpio_t;
-
-/* SDRAM Controller (SDRAMC) */
-typedef struct sdramc {
- u32 sdmr; /* Mode/Extended Mode */
- u32 sdcr; /* Control */
- u32 sdcfg1; /* Configuration 1 */
- u32 sdcfg2; /* Chip Select */
- u8 resv0[0x100];
- u32 sdcs0; /* Mode/Extended Mode */
- u32 sdcs1; /* Mode/Extended Mode */
-} sdramc_t;
-
-/* Phase Locked Loop (PLL) */
-typedef struct pll {
- u32 pcr; /* PLL Control */
- u32 psr; /* PLL Status */
-} pll_t;
-
-/* System Control Module register */
-typedef struct scm1 {
- u32 mpr; /* 0x00 Master Privilege */
- u32 rsvd1[7];
- u32 pacra; /* 0x20 */
- u32 pacrb; /* 0x24 */
- u32 pacrc; /* 0x28 */
- u32 pacrd; /* 0x2C */
- u32 rsvd2[4];
- u32 pacre; /* 0x40 */
- u32 pacrf; /* 0x44 */
- u32 pacrg; /* 0x48 */
- u32 rsvd3;
- u32 pacri; /* 0x50 */
-} scm1_t;
-
-typedef struct scm2_ctrl {
- u8 res1[3]; /* 0x00 - 0x02 */
- u8 wcr; /* 0x03 wakeup control */
- u16 res2; /* 0x04 - 0x05 */
- u16 cwcr; /* 0x06 Core Watchdog Control */
- u8 res3[3]; /* 0x08 - 0x0A */
- u8 cwsr; /* 0x0B Core Watchdog Service */
- u8 res4[2]; /* 0x0C - 0x0D */
- u8 scmisr; /* 0x0F Interrupt Status */
- u32 res5; /* 0x20 */
- u32 bcr; /* 0x24 Burst Configuration */
-} scm2_t;
-
-typedef struct scm3_ctrl {
- u32 cfadr; /* 0x00 Core Fault Address */
- u8 res7; /* 0x04 */
- u8 cfier; /* 0x05 Core Fault Interrupt Enable */
- u8 cfloc; /* 0x06 Core Fault Location */
- u8 cfatr; /* 0x07 Core Fault Attributes */
- u32 cfdtr; /* 0x08 Core Fault Data */
-} scm3_t;
-
-typedef struct rtcex {
- u32 rsvd1[3];
- u32 gocu;
- u32 gocl;
-} rtcex_t;
-#endif /* __IMMAP_5227X__ */
diff --git a/arch/m68k/include/asm/immap_5445x.h b/arch/m68k/include/asm/immap_5445x.h
deleted file mode 100644
index 3111d00..0000000
--- a/arch/m68k/include/asm/immap_5445x.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5445x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __IMMAP_5445X__
-#define __IMMAP_5445X__
-
-/* Module Base Addresses */
-#define MMAP_SCM1 0xFC000000
-#define MMAP_XBS 0xFC004000
-#define MMAP_FBCS 0xFC008000
-#define MMAP_FEC0 0xFC030000
-#define MMAP_FEC1 0xFC034000
-#define MMAP_RTC 0xFC03C000
-#define MMAP_SCM2 0xFC040000
-#define MMAP_EDMA 0xFC044000
-#define MMAP_INTC0 0xFC048000
-#define MMAP_INTC1 0xFC04C000
-#define MMAP_IACK 0xFC054000
-#define MMAP_I2C 0xFC058000
-#define MMAP_DSPI 0xFC05C000
-#define MMAP_UART0 0xFC060000
-#define MMAP_UART1 0xFC064000
-#define MMAP_UART2 0xFC068000
-#define MMAP_DTMR0 0xFC070000
-#define MMAP_DTMR1 0xFC074000
-#define MMAP_DTMR2 0xFC078000
-#define MMAP_DTMR3 0xFC07C000
-#define MMAP_PIT0 0xFC080000
-#define MMAP_PIT1 0xFC084000
-#define MMAP_PIT2 0xFC088000
-#define MMAP_PIT3 0xFC08C000
-#define MMAP_EPORT 0xFC094000
-#define MMAP_WTM 0xFC098000
-#define MMAP_SBF 0xFC0A0000
-#define MMAP_RCM 0xFC0A0000
-#define MMAP_CCM 0xFC0A0000
-#define MMAP_GPIO 0xFC0A4000
-#define MMAP_PCI 0xFC0A8000
-#define MMAP_PCIARB 0xFC0AC000
-#define MMAP_RNG 0xFC0B4000
-#define MMAP_SDRAM 0xFC0B8000
-#define MMAP_SSI 0xFC0BC000
-#define MMAP_PLL 0xFC0C4000
-#define MMAP_ATA 0x90000000
-#define MMAP_USBHW 0xFC0B0000
-#define MMAP_USBCAPS 0xFC0B0100
-#define MMAP_USBEHCI 0xFC0B0140
-#define MMAP_USBOTG 0xFC0B01A0
-
-#include <asm/coldfire/ata.h>
-#include <asm/coldfire/crossbar.h>
-#include <asm/coldfire/dspi.h>
-#include <asm/coldfire/edma.h>
-#include <asm/coldfire/eport.h>
-#include <asm/coldfire/flexbus.h>
-#include <asm/coldfire/intctrl.h>
-#include <asm/coldfire/ssi.h>
-
-/* Watchdog Timer Modules (WTM) */
-typedef struct wtm {
- u16 wcr;
- u16 wmr;
- u16 wcntr;
- u16 wsr;
-} wtm_t;
-
-/* Serial Boot Facility (SBF) */
-typedef struct sbf {
- u8 resv0[0x18];
- u16 sbfsr; /* Serial Boot Facility Status Register */
- u8 resv1[0x6];
- u16 sbfcr; /* Serial Boot Facility Control Register */
-} sbf_t;
-
-/* Reset Controller Module (RCM) */
-typedef struct rcm {
- u8 rcr;
- u8 rsr;
-} rcm_t;
-
-/* Chip Configuration Module (CCM) */
-typedef struct ccm {
- u8 ccm_resv0[0x4];
- u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
- u8 resv1[0x2];
- u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
- u16 cir; /* Chip Identification Register (Read-only) */
- u8 resv2[0x4];
- u16 misccr; /* Miscellaneous Control Register */
- u16 cdr; /* Clock Divider Register */
- u16 uocsr; /* USB On-the-Go Controller Status Register */
-} ccm_t;
-
-/* General Purpose I/O Module (GPIO) */
-typedef struct gpio {
- u8 podr_fec0h; /* FEC0 High Port Output Data Register */
- u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
- u8 podr_ssi; /* SSI Port Output Data Register */
- u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
- u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
- u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
- u8 podr_dma; /* DMA Port Output Data Register */
- u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
- u8 resv0[0x1];
- u8 podr_uart; /* UART Port Output Data Register */
- u8 podr_dspi; /* DSPI Port Output Data Register */
- u8 podr_timer; /* Timer Port Output Data Register */
- u8 podr_pci; /* PCI Port Output Data Register */
- u8 podr_usb; /* USB Port Output Data Register */
- u8 podr_atah; /* ATA High Port Output Data Register */
- u8 podr_atal; /* ATA Low Port Output Data Register */
- u8 podr_fec1h; /* FEC1 High Port Output Data Register */
- u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
- u8 resv1[0x2];
- u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
- u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
- u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
- u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
- u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
- u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
- u8 pddr_ssi; /* SSI Port Data Direction Register */
- u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
- u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
- u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
- u8 pddr_dma; /* DMA Port Data Direction Register */
- u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
- u8 resv2[0x1];
- u8 pddr_uart; /* UART Port Data Direction Register */
- u8 pddr_dspi; /* DSPI Port Data Direction Register */
- u8 pddr_timer; /* Timer Port Data Direction Register */
- u8 pddr_pci; /* PCI Port Data Direction Register */
- u8 pddr_usb; /* USB Port Data Direction Register */
- u8 pddr_atah; /* ATA High Port Data Direction Register */
- u8 pddr_atal; /* ATA Low Port Data Direction Register */
- u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
- u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
- u8 resv3[0x2];
- u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
- u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
- u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
- u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
- u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
- u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
- u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
- u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
- u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
- u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
- u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
- u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
- u8 resv4[0x1];
- u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
- u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
- u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
- u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
- u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
- u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
- u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
- u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
- u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
- u8 resv5[0x2];
- u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
- u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
- u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
- u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
- u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
- u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
- u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
- u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
- u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
- u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
- u8 pclrr_dma; /* DMA Port Clear Output Data Register */
- u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
- u8 resv6[0x1];
- u8 pclrr_uart; /* UART Port Clear Output Data Register */
- u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
- u8 pclrr_timer; /* Timer Port Clear Output Data Register */
- u8 pclrr_pci; /* PCI Port Clear Output Data Register */
- u8 pclrr_usb; /* USB Port Clear Output Data Register */
- u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
- u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
- u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
- u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
- u8 resv7[0x2];
- u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
- u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
- u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
- u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
- u8 par_fec; /* FEC Pin Assignment Register */
- u8 par_dma; /* DMA Pin Assignment Register */
- u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
- u8 par_dspi; /* DSPI Pin Assignment Register */
- u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
- u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
- u8 par_timer; /* Time Pin Assignment Register */
- u8 par_usb; /* USB Pin Assignment Register */
- u8 resv8[0x1];
- u8 par_uart; /* UART Pin Assignment Register */
- u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
- u16 par_ssi; /* SSI Pin Assignment Register */
- u16 par_ata; /* ATA Pin Assignment Register */
- u8 par_irq; /* IRQ Pin Assignment Register */
- u8 resv9[0x1];
- u16 par_pci; /* PCI Pin Assignment Register */
- u8 mscr_sdram; /* SDRAM Mode Select Control Register */
- u8 mscr_pci; /* PCI Mode Select Control Register */
- u8 resv10[0x2];
- u8 dscr_i2c; /* I2C Drive Strength Control Register */
- u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
- u8 dscr_fec; /* FEC Drive Strength Control Register */
- u8 dscr_uart; /* UART Drive Strength Control Register */
- u8 dscr_dspi; /* DSPI Drive Strength Control Register */
- u8 dscr_timer; /* TIMER Drive Strength Control Register */
- u8 dscr_ssi; /* SSI Drive Strength Control Register */
- u8 dscr_dma; /* DMA Drive Strength Control Register */
- u8 dscr_debug; /* DEBUG Drive Strength Control Register */
- u8 dscr_reset; /* RESET Drive Strength Control Register */
- u8 dscr_irq; /* IRQ Drive Strength Control Register */
- u8 dscr_usb; /* USB Drive Strength Control Register */
- u8 dscr_ata; /* ATA Drive Strength Control Register */
-} gpio_t;
-
-/* SDRAM Controller (SDRAMC) */
-typedef struct sdramc {
- u32 sdmr; /* SDRAM Mode/Extended Mode Register */
- u32 sdcr; /* SDRAM Control Register */
- u32 sdcfg1; /* SDRAM Configuration Register 1 */
- u32 sdcfg2; /* SDRAM Chip Select Register */
- u8 resv0[0x100];
- u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
- u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
-} sdramc_t;
-
-/* Phase Locked Loop (PLL) */
-typedef struct pll {
- u32 pcr; /* PLL Control Register */
- u32 psr; /* PLL Status Register */
-} pll_t;
-
-typedef struct pci {
- u32 idr; /* 0x00 Device Id / Vendor Id Register */
- u32 scr; /* 0x04 Status / command Register */
- u32 ccrir; /* 0x08 Class Code / Revision Id Register */
- u32 cr1; /* 0x0c Configuration 1 Register */
- u32 bar0; /* 0x10 Base address register 0 Register */
- u32 bar1; /* 0x14 Base address register 1 Register */
- u32 bar2; /* 0x18 Base address register 2 Register */
- u32 bar3; /* 0x1c Base address register 3 Register */
- u32 bar4; /* 0x20 Base address register 4 Register */
- u32 bar5; /* 0x24 Base address register 5 Register */
- u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
- u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
- u32 erbar; /* 0x30 Expansion ROM Base Address Register */
- u32 cpr; /* 0x34 Capabilities Pointer Register */
- u32 rsvd1; /* 0x38 */
- u32 cr2; /* 0x3c Configuration Register 2 */
- u32 rsvd2[8]; /* 0x40 - 0x5f */
-
- /* General control / status registers */
- u32 gscr; /* 0x60 Global Status / Control Register */
- u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
- u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
- u32 tcr1; /* 0x6c Target Control 1 Register */
- u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
- u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
- u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
- u32 rsvd3; /* 0x7c */
- u32 iwcr; /* 0x80 Initiator Window Configuration Register */
- u32 icr; /* 0x84 Initiator Control Register */
- u32 isr; /* 0x88 Initiator Status Register */
- u32 tcr2; /* 0x8c Target Control 2 Register */
- u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
- u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
- u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
- u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
- u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
- u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
- u32 intr; /* 0xa8 Interrupt Register */
- u32 rsvd4[19]; /* 0xac - 0xf7 */
- u32 car; /* 0xf8 Configuration Address Register */
-} pci_t;
-
-typedef struct pci_arbiter {
- /* Pci Arbiter Registers */
- union {
- u32 acr; /* Arbiter Control Register */
- u32 asr; /* Arbiter Status Register */
- };
-} pciarb_t;
-
-/* Register read/write struct */
-typedef struct scm1 {
- u32 mpr; /* 0x00 Master Privilege Register */
- u32 rsvd1[7];
- u32 pacra; /* 0x20 Peripheral Access Control Register A */
- u32 pacrb; /* 0x24 Peripheral Access Control Register B */
- u32 pacrc; /* 0x28 Peripheral Access Control Register C */
- u32 pacrd; /* 0x2C Peripheral Access Control Register D */
- u32 rsvd2[4];
- u32 pacre; /* 0x40 Peripheral Access Control Register E */
- u32 pacrf; /* 0x44 Peripheral Access Control Register F */
- u32 pacrg; /* 0x48 Peripheral Access Control Register G */
-} scm1_t;
-
-typedef struct scm2 {
- u8 rsvd1[19]; /* 0x00 - 0x12 */
- u8 wcr; /* 0x13 */
- u16 rsvd2; /* 0x14 - 0x15 */
- u16 cwcr; /* 0x16 */
- u8 rsvd3[3]; /* 0x18 - 0x1A */
- u8 cwsr; /* 0x1B */
- u8 rsvd4[3]; /* 0x1C - 0x1E */
- u8 scmisr; /* 0x1F */
- u32 rsvd5; /* 0x20 - 0x23 */
- u8 bcr; /* 0x24 */
- u8 rsvd6[74]; /* 0x25 - 0x6F */
- u32 cfadr; /* 0x70 */
- u8 rsvd7; /* 0x74 */
- u8 cfier; /* 0x75 */
- u8 cfloc; /* 0x76 */
- u8 cfatr; /* 0x77 */
- u32 rsvd8; /* 0x78 - 0x7B */
- u32 cfdtr; /* 0x7C */
-} scm2_t;
-
-typedef struct rtcex {
- u32 rsvd1[3];
- u32 gocu;
- u32 gocl;
-} rtcex_t;
-#endif /* __IMMAP_5445X__ */
diff --git a/arch/m68k/include/asm/m5227x.h b/arch/m68k/include/asm/m5227x.h
deleted file mode 100644
index 67c16e0..0000000
--- a/arch/m68k/include/asm/m5227x.h
+++ /dev/null
@@ -1,546 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5227x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __MCF5227X__
-#define __MCF5227X__
-
-/* Interrupt Controller (INTC) */
-#define INT0_LO_RSVD0 (0)
-#define INT0_LO_EPORT1 (1)
-#define INT0_LO_EPORT4 (4)
-#define INT0_LO_EPORT7 (7)
-#define INT0_LO_EDMA_00 (8)
-#define INT0_LO_EDMA_01 (9)
-#define INT0_LO_EDMA_02 (10)
-#define INT0_LO_EDMA_03 (11)
-#define INT0_LO_EDMA_04 (12)
-#define INT0_LO_EDMA_05 (13)
-#define INT0_LO_EDMA_06 (14)
-#define INT0_LO_EDMA_07 (15)
-#define INT0_LO_EDMA_08 (16)
-#define INT0_LO_EDMA_09 (17)
-#define INT0_LO_EDMA_10 (18)
-#define INT0_LO_EDMA_11 (19)
-#define INT0_LO_EDMA_12 (20)
-#define INT0_LO_EDMA_13 (21)
-#define INT0_LO_EDMA_14 (22)
-#define INT0_LO_EDMA_15 (23)
-#define INT0_LO_EDMA_ERR (24)
-#define INT0_LO_SCM_CWIC (25)
-#define INT0_LO_UART0 (26)
-#define INT0_LO_UART1 (27)
-#define INT0_LO_UART2 (28)
-#define INT0_LO_I2C (30)
-#define INT0_LO_DSPI (31)
-#define INT0_HI_DTMR0 (32)
-#define INT0_HI_DTMR1 (33)
-#define INT0_HI_DTMR2 (34)
-#define INT0_HI_DTMR3 (35)
-#define INT0_HI_SCMIR (62)
-#define INT0_HI_RTC_ISR (63)
-
-#define INT1_HI_CAN_BOFFINT (1)
-#define INT1_HI_CAN_ERRINT (3)
-#define INT1_HI_CAN_BUF0I (4)
-#define INT1_HI_CAN_BUF1I (5)
-#define INT1_HI_CAN_BUF2I (6)
-#define INT1_HI_CAN_BUF3I (7)
-#define INT1_HI_CAN_BUF4I (8)
-#define INT1_HI_CAN_BUF5I (9)
-#define INT1_HI_CAN_BUF6I (10)
-#define INT1_HI_CAN_BUF7I (11)
-#define INT1_HI_CAN_BUF8I (12)
-#define INT1_HI_CAN_BUF9I (13)
-#define INT1_HI_CAN_BUF10I (14)
-#define INT1_HI_CAN_BUF11I (15)
-#define INT1_HI_CAN_BUF12I (16)
-#define INT1_HI_CAN_BUF13I (17)
-#define INT1_HI_CAN_BUF14I (18)
-#define INT1_HI_CAN_BUF15I (19)
-#define INT1_HI_PIT0_PIF (43)
-#define INT1_HI_PIT1_PIF (44)
-#define INT1_HI_USBOTG_STS (47)
-#define INT1_HI_SSI_ISR (49)
-#define INT1_HI_PWM_INT (50)
-#define INT1_HI_LCDC_ISR (51)
-#define INT1_HI_CCM_UOCSR (53)
-#define INT1_HI_DSPI_EOQF (54)
-#define INT1_HI_DSPI_TFFF (55)
-#define INT1_HI_DSPI_TCF (56)
-#define INT1_HI_DSPI_TFUF (57)
-#define INT1_HI_DSPI_RFDF (58)
-#define INT1_HI_DSPI_RFOF (59)
-#define INT1_HI_DSPI_RFOF_TFUF (60)
-#define INT1_HI_TOUCH_ADC (61)
-#define INT1_HI_PLL_LOCKS (62)
-
-/*********************************************************************
-* Reset Controller Module (RCM)
-*********************************************************************/
-
-/* Bit definitions and macros for RCR */
-#define RCM_RCR_FRCRSTOUT (0x40)
-#define RCM_RCR_SOFTRST (0x80)
-
-/* Bit definitions and macros for RSR */
-#define RCM_RSR_LOL (0x01)
-#define RCM_RSR_WDR_CORE (0x02)
-#define RCM_RSR_EXT (0x04)
-#define RCM_RSR_POR (0x08)
-#define RCM_RSR_SOFT (0x20)
-
-/*********************************************************************
-* Chip Configuration Module (CCM)
-*********************************************************************/
-
-/* Bit definitions and macros for CCR */
-#define CCM_CCR_DRAMSEL (0x0100)
-#define CCM_CCR_CSC_UNMASK (0xFF3F)
-#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
-#define CCM_CCR_CSC_FBCS5_A22 (0x0080)
-#define CCM_CCR_CSC_FB_A23_A22 (0x0040)
-#define CCM_CCR_LIMP (0x0020)
-#define CCM_CCR_LOAD (0x0010)
-#define CCM_CCR_BOOTPS_UNMASK (0xFFF3)
-#define CCM_CCR_BOOTPS_PS16 (0x0008)
-#define CCM_CCR_BOOTPS_PS8 (0x0004)
-#define CCM_CCR_BOOTPS_PS32 (0x0000)
-#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
-
-/* Bit definitions and macros for RCON */
-#define CCM_RCON_CSC_UNMASK (0xFF3F)
-#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
-#define CCM_RCON_CSC_FBCS5_A22 (0x0080)
-#define CCM_RCON_CSC_FB_A23_A22 (0x0040)
-#define CCM_RCON_LIMP (0x0020)
-#define CCM_RCON_LOAD (0x0010)
-#define CCM_RCON_BOOTPS_UNMASK (0xFFF3)
-#define CCM_RCON_BOOTPS_PS16 (0x0008)
-#define CCM_RCON_BOOTPS_PS8 (0x0004)
-#define CCM_RCON_BOOTPS_PS32 (0x0000)
-#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
-
-/* Bit definitions and macros for CIR */
-#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
-#define CCM_CIR_PRN(x) ((x) & 0x003F)
-#define CCM_CIR_PIN_MCF52277 (0x0000)
-
-/* Bit definitions and macros for MISCCR */
-#define CCM_MISCCR_RTCSRC (0x4000)
-#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
-#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
-
-#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */
-#define CCM_MISCCR_BMT_65536 (0)
-#define CCM_MISCCR_BMT_32768 (1)
-#define CCM_MISCCR_BMT_16384 (2)
-#define CCM_MISCCR_BMT_8192 (3)
-#define CCM_MISCCR_BMT_4096 (4)
-#define CCM_MISCCR_BMT_2048 (5)
-#define CCM_MISCCR_BMT_1024 (6)
-#define CCM_MISCCR_BMT_512 (7)
-
-#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
-#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
-#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
-#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
-#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */
-#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
-#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
-
-/* Bit definitions and macros for CDR */
-#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12)
-#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
-#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */
-
-/* Bit definitions and macros for UOCSR */
-#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
-#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
-#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */
-#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */
-#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */
-#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
-#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
-#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
-#define CCM_UOCSR_SEND (0x0010) /* Session end */
-#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
-#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */
-#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */
-
-/*********************************************************************
-* General Purpose I/O Module (GPIO)
-*********************************************************************/
-/* Bit definitions and macros for PAR_BE */
-#define GPIO_PAR_BE_UNMASK (0x0F)
-#define GPIO_PAR_BE_BE3_BE3 (0x08)
-#define GPIO_PAR_BE_BE3_GPIO (0x00)
-#define GPIO_PAR_BE_BE2_BE2 (0x04)
-#define GPIO_PAR_BE_BE2_GPIO (0x00)
-#define GPIO_PAR_BE_BE1_BE1 (0x02)
-#define GPIO_PAR_BE_BE1_GPIO (0x00)
-#define GPIO_PAR_BE_BE0_BE0 (0x01)
-#define GPIO_PAR_BE_BE0_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_CS */
-#define GPIO_PAR_CS_CS3 (0x10)
-#define GPIO_PAR_CS_CS2 (0x08)
-#define GPIO_PAR_CS_CS1_FBCS1 (0x06)
-#define GPIO_PAR_CS_CS1_SDCS1 (0x04)
-#define GPIO_PAR_CS_CS1_GPIO (0x00)
-#define GPIO_PAR_CS_CS0 (0x01)
-
-/* Bit definitions and macros for PAR_FBCTL */
-#define GPIO_PAR_FBCTL_OE (0x80)
-#define GPIO_PAR_FBCTL_TA (0x40)
-#define GPIO_PAR_FBCTL_RW (0x20)
-#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
-#define GPIO_PAR_FBCTL_TS_FBTS (0x18)
-#define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
-#define GPIO_PAR_FBCTL_TS_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_FECI2C */
-#define GPIO_PAR_I2C_SCL_UNMASK (0xF3)
-#define GPIO_PAR_I2C_SCL_SCL (0x0C)
-#define GPIO_PAR_I2C_SCL_CANTXD (0x08)
-#define GPIO_PAR_I2C_SCL_U2TXD (0x04)
-#define GPIO_PAR_I2C_SCL_GPIO (0x00)
-
-#define GPIO_PAR_I2C_SDA_UNMASK (0xFC)
-#define GPIO_PAR_I2C_SDA_SDA (0x03)
-#define GPIO_PAR_I2C_SDA_CANRXD (0x02)
-#define GPIO_PAR_I2C_SDA_U2RXD (0x01)
-#define GPIO_PAR_I2C_SDA_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_UART */
-#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF)
-#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
-#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
-#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
-#define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF)
-#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
-#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
-#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
-#define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF)
-#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
-#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
-#define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF)
-#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
-#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
-#define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F)
-#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
-#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
-#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
-#define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF)
-#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
-#define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
-#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
-#define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3)
-#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
-#define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
-#define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC)
-#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
-#define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
-#define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
-
-/* Bit definitions and macros for PAR_DSPI */
-#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F)
-#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
-#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
-#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
-#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF)
-#define GPIO_PAR_DSPI_SIN_SIN (0x30)
-#define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
-#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
-#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3)
-#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
-#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
-#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
-#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC)
-#define GPIO_PAR_DSPI_SCK_SCK (0x03)
-#define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
-#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_TIMER */
-#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
-#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
-#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
-#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
-#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
-#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
-#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
-#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
-#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
-#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
-#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
-#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
-#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
-#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
-#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
-#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
-#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
-
-/* Bit definitions and macros for GPIO_PAR_LCDCTL */
-#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7)
-#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
-#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
-#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
-#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04)
-#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02)
-#define GPIO_PAR_LCDCTL_LSCLK (0x01)
-
-/* Bit definitions and macros for PAR_IRQ */
-#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3)
-#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
-#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
-#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
-#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC)
-#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
-#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
-#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
-#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
-
-/* Bit definitions and macros for GPIO_PAR_LCDH */
-#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF)
-#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
-#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
-#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF)
-#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
-#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
-#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F)
-#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
-#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
-#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF)
-#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
-#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
-#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3)
-#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
-#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
-#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC)
-#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
-#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
-#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
-
-/* Bit definitions and macros for GPIO_PAR_LCDL */
-#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF)
-#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
-#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
-#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF)
-#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
-#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
-#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF)
-#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
-#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
-#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF)
-#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
-#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
-#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF)
-#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
-#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
-#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF)
-#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
-#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
-#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF)
-#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
-#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
-#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF)
-#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
-#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
-#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF)
-#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
-#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
-#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF)
-#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
-#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
-#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF)
-#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
-#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
-#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF)
-#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
-#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
-#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
-
-/* Bit definitions and macros for MSCR_FB */
-#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF)
-#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
-#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
-#define GPIO_MSCR_FB_DUPPER_OD (0x10)
-#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
-
-#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3)
-#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
-#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
-#define GPIO_MSCR_FB_DLOWER_OD (0x04)
-#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
-
-#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC)
-#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
-#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
-#define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
-#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
-
-/* Bit definitions and macros for MSCR_SDRAM */
-#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF)
-#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
-#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
-#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
-#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
-
-#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
-#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
-#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
-#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
-#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
-
-#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
-#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
-#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
-#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
-#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00)
-
-/* Bit definitions and macros for Drive Strength Control */
-#define DSCR_LOAD_50PF (0x03)
-#define DSCR_LOAD_30PF (0x02)
-#define DSCR_LOAD_20PF (0x01)
-#define DSCR_LOAD_10PF (0x00)
-
-/*********************************************************************
-* SDRAM Controller (SDRAMC)
-*********************************************************************/
-
-/* Bit definitions and macros for SDMR */
-#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
-#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
-#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
-#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
-#define SDRAMC_SDMR_BK_LMR (0x00000000)
-#define SDRAMC_SDMR_BK_LEMR (0x40000000)
-
-/* Bit definitions and macros for SDCR */
-#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
-#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
-#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
-#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
-#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
-#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
-#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
-#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
-#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
-#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
-#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
-#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
-#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
-#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
-
-/* Bit definitions and macros for SDCFG1 */
-#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
-#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
-#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
-#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
-#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
-#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
-#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
-
-/* Bit definitions and macros for SDCFG2 */
-#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
-#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
-#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
-#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
-
-/* Bit definitions and macros for SDCS group */
-#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
-#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
-#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
-#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
-#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
-#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
-#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
-#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
-#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
-#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
-#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
-#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
-#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
-#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
-#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
-#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
-#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
-
-/*********************************************************************
-* Phase Locked Loop (PLL)
-*********************************************************************/
-
-/* Bit definitions and macros for PCR */
-#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
-#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */
-#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */
-#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
-#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
-#define PLL_PCR_PFDR_MASK (0x000F0000)
-#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
-#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
-#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
-#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
-
-/* Bit definitions and macros for PSR */
-#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
-#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
-#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
-#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
-
-/********************************************************************/
-
-#endif /* __MCF5227X__ */
diff --git a/arch/m68k/include/asm/m5445x.h b/arch/m68k/include/asm/m5445x.h
deleted file mode 100644
index 498c225..0000000
--- a/arch/m68k/include/asm/m5445x.h
+++ /dev/null
@@ -1,888 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5445x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __MCF5445X__
-#define __MCF5445X__
-
-/*********************************************************************
-* Interrupt Controller (INTC)
-*********************************************************************/
-#define INT0_LO_RSVD0 (0)
-#define INT0_LO_EPORT1 (1)
-#define INT0_LO_EPORT2 (2)
-#define INT0_LO_EPORT3 (3)
-#define INT0_LO_EPORT4 (4)
-#define INT0_LO_EPORT5 (5)
-#define INT0_LO_EPORT6 (6)
-#define INT0_LO_EPORT7 (7)
-#define INT0_LO_EDMA_00 (8)
-#define INT0_LO_EDMA_01 (9)
-#define INT0_LO_EDMA_02 (10)
-#define INT0_LO_EDMA_03 (11)
-#define INT0_LO_EDMA_04 (12)
-#define INT0_LO_EDMA_05 (13)
-#define INT0_LO_EDMA_06 (14)
-#define INT0_LO_EDMA_07 (15)
-#define INT0_LO_EDMA_08 (16)
-#define INT0_LO_EDMA_09 (17)
-#define INT0_LO_EDMA_10 (18)
-#define INT0_LO_EDMA_11 (19)
-#define INT0_LO_EDMA_12 (20)
-#define INT0_LO_EDMA_13 (21)
-#define INT0_LO_EDMA_14 (22)
-#define INT0_LO_EDMA_15 (23)
-#define INT0_LO_EDMA_ERR (24)
-#define INT0_LO_SCM (25)
-#define INT0_LO_UART0 (26)
-#define INT0_LO_UART1 (27)
-#define INT0_LO_UART2 (28)
-#define INT0_LO_RSVD1 (29)
-#define INT0_LO_I2C (30)
-#define INT0_LO_QSPI (31)
-#define INT0_HI_DTMR0 (32)
-#define INT0_HI_DTMR1 (33)
-#define INT0_HI_DTMR2 (34)
-#define INT0_HI_DTMR3 (35)
-#define INT0_HI_FEC0_TXF (36)
-#define INT0_HI_FEC0_TXB (37)
-#define INT0_HI_FEC0_UN (38)
-#define INT0_HI_FEC0_RL (39)
-#define INT0_HI_FEC0_RXF (40)
-#define INT0_HI_FEC0_RXB (41)
-#define INT0_HI_FEC0_MII (42)
-#define INT0_HI_FEC0_LC (43)
-#define INT0_HI_FEC0_HBERR (44)
-#define INT0_HI_FEC0_GRA (45)
-#define INT0_HI_FEC0_EBERR (46)
-#define INT0_HI_FEC0_BABT (47)
-#define INT0_HI_FEC0_BABR (48)
-#define INT0_HI_FEC1_TXF (49)
-#define INT0_HI_FEC1_TXB (50)
-#define INT0_HI_FEC1_UN (51)
-#define INT0_HI_FEC1_RL (52)
-#define INT0_HI_FEC1_RXF (53)
-#define INT0_HI_FEC1_RXB (54)
-#define INT0_HI_FEC1_MII (55)
-#define INT0_HI_FEC1_LC (56)
-#define INT0_HI_FEC1_HBERR (57)
-#define INT0_HI_FEC1_GRA (58)
-#define INT0_HI_FEC1_EBERR (59)
-#define INT0_HI_FEC1_BABT (60)
-#define INT0_HI_FEC1_BABR (61)
-#define INT0_HI_SCMIR (62)
-#define INT0_HI_RTC_ISR (63)
-
-#define INT1_HI_DSPI_EOQF (33)
-#define INT1_HI_DSPI_TFFF (34)
-#define INT1_HI_DSPI_TCF (35)
-#define INT1_HI_DSPI_TFUF (36)
-#define INT1_HI_DSPI_RFDF (37)
-#define INT1_HI_DSPI_RFOF (38)
-#define INT1_HI_DSPI_RFOF_TFUF (39)
-#define INT1_HI_RNG_EI (40)
-#define INT1_HI_PIT0_PIF (43)
-#define INT1_HI_PIT1_PIF (44)
-#define INT1_HI_PIT2_PIF (45)
-#define INT1_HI_PIT3_PIF (46)
-#define INT1_HI_USBOTG_USBSTS (47)
-#define INT1_HI_SSI_ISR (49)
-#define INT1_HI_CCM_UOCSR (53)
-#define INT1_HI_ATA_ISR (54)
-#define INT1_HI_PCI_SCR (55)
-#define INT1_HI_PCI_ASR (56)
-#define INT1_HI_PLL_LOCKS (57)
-
-/*********************************************************************
-* Watchdog Timer Modules (WTM)
-*********************************************************************/
-
-/* Bit definitions and macros for WCR */
-#define WTM_WCR_EN (0x0001)
-#define WTM_WCR_HALTED (0x0002)
-#define WTM_WCR_DOZE (0x0004)
-#define WTM_WCR_WAIT (0x0008)
-
-/*********************************************************************
-* Serial Boot Facility (SBF)
-*********************************************************************/
-
-/* Bit definitions and macros for SBFCR */
-#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */
-#define SBF_SBFCR_FR (0x0010) /* Fast read */
-
-/*********************************************************************
-* Reset Controller Module (RCM)
-*********************************************************************/
-
-/* Bit definitions and macros for RCR */
-#define RCM_RCR_FRCRSTOUT (0x40)
-#define RCM_RCR_SOFTRST (0x80)
-
-/* Bit definitions and macros for RSR */
-#define RCM_RSR_LOL (0x01)
-#define RCM_RSR_WDR_CORE (0x02)
-#define RCM_RSR_EXT (0x04)
-#define RCM_RSR_POR (0x08)
-#define RCM_RSR_SOFT (0x20)
-
-/*********************************************************************
-* Chip Configuration Module (CCM)
-*********************************************************************/
-
-/* Bit definitions and macros for CCR_360 */
-#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */
-#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
-#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
-#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
-#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
-#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */
-#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
-#define CCM_CCR_360_FBCONFIG_MASK (0x00E0)
-#define CCM_CCR_360_PLLMULT2_MASK (0x0003)
-#define CCM_CCR_360_PLLMULT3_MASK (0x0007)
-#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
-#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
-#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
-#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
-#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
-#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
-#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
-#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
-#define CCM_CCR_360_PLLMULT2_12X (0x0000)
-#define CCM_CCR_360_PLLMULT2_6X (0x0001)
-#define CCM_CCR_360_PLLMULT2_16X (0x0002)
-#define CCM_CCR_360_PLLMULT2_8X (0x0003)
-#define CCM_CCR_360_PLLMULT3_20X (0x0000)
-#define CCM_CCR_360_PLLMULT3_10X (0x0001)
-#define CCM_CCR_360_PLLMULT3_24X (0x0002)
-#define CCM_CCR_360_PLLMULT3_18X (0x0003)
-#define CCM_CCR_360_PLLMULT3_12X (0x0004)
-#define CCM_CCR_360_PLLMULT3_6X (0x0005)
-#define CCM_CCR_360_PLLMULT3_16X (0x0006)
-#define CCM_CCR_360_PLLMULT3_8X (0x0007)
-
-/* Bit definitions and macros for CCR_256 */
-#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */
-#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
-#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
-#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
-#define CCM_CCR_256_FBCONFIG_MASK (0x00E0)
-#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
-#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
-#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
-#define CCM_CCR_256_FBCONFIG_M_32 (0x0080)
-#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
-#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
-#define CCM_CCR_256_PLLMULT3_MASK (0x0007)
-#define CCM_CCR_256_PLLMULT3_20X (0x0000)
-#define CCM_CCR_256_PLLMULT3_10X (0x0001)
-#define CCM_CCR_256_PLLMULT3_24X (0x0002)
-#define CCM_CCR_256_PLLMULT3_18X (0x0003)
-#define CCM_CCR_256_PLLMULT3_12X (0x0004)
-#define CCM_CCR_256_PLLMULT3_6X (0x0005)
-#define CCM_CCR_256_PLLMULT3_16X (0x0006)
-#define CCM_CCR_256_PLLMULT3_8X (0x0007)
-
-/* Bit definitions and macros for RCON_360 */
-#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
-#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
-#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
-#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
-#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
-
-/* Bit definitions and macros for RCON_256 */
-#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */
-#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
-#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
-#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
-
-/* Bit definitions and macros for CIR */
-#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
-#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
-#define CCM_CIR_PIN_MASK (0xFFC0)
-#define CCM_CIR_PRN_MASK (0x003F)
-#define CCM_CIR_PIN_MCF54450 (0x4F<<6)
-#define CCM_CIR_PIN_MCF54451 (0x4D<<6)
-#define CCM_CIR_PIN_MCF54452 (0x4B<<6)
-#define CCM_CIR_PIN_MCF54453 (0x49<<6)
-#define CCM_CIR_PIN_MCF54454 (0x4A<<6)
-#define CCM_CIR_PIN_MCF54455 (0x48<<6)
-
-/* Bit definitions and macros for MISCCR */
-#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
-#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
-#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
-#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
-#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
-#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
-#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
-#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */
-#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
-#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
-#define CCM_MISCCR_BMT_65536 (0)
-#define CCM_MISCCR_BMT_32768 (1)
-#define CCM_MISCCR_BMT_16384 (2)
-#define CCM_MISCCR_BMT_8192 (3)
-#define CCM_MISCCR_BMT_4096 (4)
-#define CCM_MISCCR_BMT_2048 (5)
-#define CCM_MISCCR_BMT_1024 (6)
-#define CCM_MISCCR_BMT_512 (7)
-#define CCM_MISCCR_SSIPUS_UP (1)
-#define CCM_MISCCR_SSIPUS_DOWN (0)
-#define CCM_MISCCR_TIMDMA_TIM (1)
-#define CCM_MISCCR_TIMDMA_SSI (0)
-#define CCM_MISCCR_SSISRC_CLKIN (0)
-#define CCM_MISCCR_SSISRC_PLL (1)
-#define CCM_MISCCR_USBOC_ACTHI (0)
-#define CCM_MISCCR_USBOV_ACTLO (1)
-#define CCM_MISCCR_USBSRC_CLKIN (0)
-#define CCM_MISCCR_USBSRC_PLL (1)
-
-/* Bit definitions and macros for CDR */
-#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */
-#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */
-
-/* Bit definitions and macros for UOCSR */
-#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
-#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
-#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
-#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
-#define CCM_UOCSR_SEND (0x0010) /* Session end */
-#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
-#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
-#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
-#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
-#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
-#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
-#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
-#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
-
-/*********************************************************************
-* General Purpose I/O Module (GPIO)
-*********************************************************************/
-
-/* Bit definitions and macros for PAR_FEC */
-#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
-#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
-#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F)
-#define GPIO_PAR_FEC_FEC1_MII (0x70)
-#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
-#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
-#define GPIO_PAR_FEC_FEC1_ATA (0x10)
-#define GPIO_PAR_FEC_FEC1_GPIO (0x00)
-#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8)
-#define GPIO_PAR_FEC_FEC0_MII (0x07)
-#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
-#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
-#define GPIO_PAR_FEC_FEC0_ULPI (0x01)
-#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_DMA */
-#define GPIO_PAR_DMA_DREQ0 (0x01)
-#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
-#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
-#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
-#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F)
-#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
-#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
-#define GPIO_PAR_DMA_DACK1_GPIO (0x00)
-#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF)
-#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
-#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
-#define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
-#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3)
-#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
-#define GPIO_PAR_DMA_DACK0_PCS3 (0x08)
-#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
-#define GPIO_PAR_DMA_DACK0_GPIO (0x00)
-#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
-#define GPIO_PAR_DMA_DREQ0_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_FBCTL */
-#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
-#define GPIO_PAR_FBCTL_RW (0x20)
-#define GPIO_PAR_FBCTL_TA (0x40)
-#define GPIO_PAR_FBCTL_OE (0x80)
-#define GPIO_PAR_FBCTL_OE_OE (0x80)
-#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
-#define GPIO_PAR_FBCTL_TA_TA (0x40)
-#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
-#define GPIO_PAR_FBCTL_RW_RW (0x20)
-#define GPIO_PAR_FBCTL_RW_GPIO (0x00)
-#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
-#define GPIO_PAR_FBCTL_TS_TS (0x18)
-#define GPIO_PAR_FBCTL_TS_ALE (0x10)
-#define GPIO_PAR_FBCTL_TS_TBST (0x08)
-#define GPIO_PAR_FBCTL_TS_GPIO (0x80)
-
-/* Bit definitions and macros for PAR_DSPI */
-#define GPIO_PAR_DSPI_SCK (0x01)
-#define GPIO_PAR_DSPI_SOUT (0x02)
-#define GPIO_PAR_DSPI_SIN (0x04)
-#define GPIO_PAR_DSPI_PCS0 (0x08)
-#define GPIO_PAR_DSPI_PCS1 (0x10)
-#define GPIO_PAR_DSPI_PCS2 (0x20)
-#define GPIO_PAR_DSPI_PCS5 (0x40)
-#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
-#define GPIO_PAR_DSPI_PCS5_GPIO (0x00)
-#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
-#define GPIO_PAR_DSPI_PCS2_GPIO (0x00)
-#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
-#define GPIO_PAR_DSPI_PCS1_GPIO (0x00)
-#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
-#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
-#define GPIO_PAR_DSPI_SIN_SIN (0x04)
-#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
-#define GPIO_PAR_DSPI_SOUT_SOUT (0x02)
-#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
-#define GPIO_PAR_DSPI_SCK_SCK (0x01)
-#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_BE */
-#define GPIO_PAR_BE_BS0 (0x01)
-#define GPIO_PAR_BE_BS1 (0x04)
-#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
-#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
-#define GPIO_PAR_BE_BE3_UNMASK (0x3F)
-#define GPIO_PAR_BE_BE3_BE3 (0xC0)
-#define GPIO_PAR_BE_BE3_TSIZ1 (0x80)
-#define GPIO_PAR_BE_BE3_GPIO (0x00)
-#define GPIO_PAR_BE_BE2_UNMASK (0xCF)
-#define GPIO_PAR_BE_BE2_BE2 (0x30)
-#define GPIO_PAR_BE_BE2_TSIZ0 (0x20)
-#define GPIO_PAR_BE_BE2_GPIO (0x00)
-#define GPIO_PAR_BE_BE1_BE1 (0x04)
-#define GPIO_PAR_BE_BE1_GPIO (0x00)
-#define GPIO_PAR_BE_BE0_BE0 (0x01)
-#define GPIO_PAR_BE_BE0_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_CS */
-#define GPIO_PAR_CS_CS1 (0x02)
-#define GPIO_PAR_CS_CS2 (0x04)
-#define GPIO_PAR_CS_CS3 (0x08)
-#define GPIO_PAR_CS_CS3_CS3 (0x08)
-#define GPIO_PAR_CS_CS3_GPIO (0x00)
-#define GPIO_PAR_CS_CS2_CS2 (0x04)
-#define GPIO_PAR_CS_CS2_GPIO (0x00)
-#define GPIO_PAR_CS_CS1_CS1 (0x02)
-#define GPIO_PAR_CS_CS1_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_TIMER */
-#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
-#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
-#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
-#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
-#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
-#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
-#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
-#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
-#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
-#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
-#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
-#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
-#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
-#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
-#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
-#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
-#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
-#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
-#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
-#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
-#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_USB */
-#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
-#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
-#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3)
-#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
-#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
-#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
-#define GPIO_PAR_USB_VBUSEN_GPIO (0x00)
-#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC)
-#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
-#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
-#define GPIO_PAR_USB_VBUSOC_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_UART */
-#define GPIO_PAR_UART_U0TXD (0x01)
-#define GPIO_PAR_UART_U0RXD (0x02)
-#define GPIO_PAR_UART_U0RTS (0x04)
-#define GPIO_PAR_UART_U0CTS (0x08)
-#define GPIO_PAR_UART_U1TXD (0x10)
-#define GPIO_PAR_UART_U1RXD (0x20)
-#define GPIO_PAR_UART_U1RTS (0x40)
-#define GPIO_PAR_UART_U1CTS (0x80)
-#define GPIO_PAR_UART_U1CTS_U1CTS (0x80)
-#define GPIO_PAR_UART_U1CTS_GPIO (0x00)
-#define GPIO_PAR_UART_U1RTS_U1RTS (0x40)
-#define GPIO_PAR_UART_U1RTS_GPIO (0x00)
-#define GPIO_PAR_UART_U1RXD_U1RXD (0x20)
-#define GPIO_PAR_UART_U1RXD_GPIO (0x00)
-#define GPIO_PAR_UART_U1TXD_U1TXD (0x10)
-#define GPIO_PAR_UART_U1TXD_GPIO (0x00)
-#define GPIO_PAR_UART_U0CTS_U0CTS (0x08)
-#define GPIO_PAR_UART_U0CTS_GPIO (0x00)
-#define GPIO_PAR_UART_U0RTS_U0RTS (0x04)
-#define GPIO_PAR_UART_U0RTS_GPIO (0x00)
-#define GPIO_PAR_UART_U0RXD_U0RXD (0x02)
-#define GPIO_PAR_UART_U0RXD_GPIO (0x00)
-#define GPIO_PAR_UART_U0TXD_U0TXD (0x01)
-#define GPIO_PAR_UART_U0TXD_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_FECI2C */
-#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
-#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
-#define GPIO_PAR_FECI2C_MDIO0 (0x0010)
-#define GPIO_PAR_FECI2C_MDC0 (0x0040)
-#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
-#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
-#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF)
-#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
-#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
-#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF)
-#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
-#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
-#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
-#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
-#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3)
-#define GPIO_PAR_FECI2C_SCL_SCL (0x000C)
-#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
-#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC)
-#define GPIO_PAR_FECI2C_SDA_SDA (0x0003)
-#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
-#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
-
-/* Bit definitions and macros for PAR_SSI */
-#define GPIO_PAR_SSI_MCLK (0x0001)
-#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
-#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
-#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
-#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
-#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF)
-#define GPIO_PAR_SSI_BCLK_BCLK (0x0300)
-#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
-#define GPIO_PAR_SSI_BCLK_GPIO (0x0000)
-#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F)
-#define GPIO_PAR_SSI_FS_FS (0x00C0)
-#define GPIO_PAR_SSI_FS_U1RTS (0x0080)
-#define GPIO_PAR_SSI_FS_GPIO (0x0000)
-#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF)
-#define GPIO_PAR_SSI_SRXD_SRXD (0x0030)
-#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
-#define GPIO_PAR_SSI_SRXD_GPIO (0x0000)
-#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3)
-#define GPIO_PAR_SSI_STXD_STXD (0x000C)
-#define GPIO_PAR_SSI_STXD_U1TXD (0x0008)
-#define GPIO_PAR_SSI_STXD_GPIO (0x0000)
-#define GPIO_PAR_SSI_MCLK_MCLK (0x0001)
-#define GPIO_PAR_SSI_MCLK_GPIO (0x0000)
-
-/* Bit definitions and macros for PAR_ATA */
-#define GPIO_PAR_ATA_IORDY (0x0001)
-#define GPIO_PAR_ATA_DMARQ (0x0002)
-#define GPIO_PAR_ATA_RESET (0x0004)
-#define GPIO_PAR_ATA_DA0 (0x0020)
-#define GPIO_PAR_ATA_DA1 (0x0040)
-#define GPIO_PAR_ATA_DA2 (0x0080)
-#define GPIO_PAR_ATA_CS0 (0x0100)
-#define GPIO_PAR_ATA_CS1 (0x0200)
-#define GPIO_PAR_ATA_BUFEN (0x0400)
-#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
-#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
-#define GPIO_PAR_ATA_CS1_CS1 (0x0200)
-#define GPIO_PAR_ATA_CS1_GPIO (0x0000)
-#define GPIO_PAR_ATA_CS0_CS0 (0x0100)
-#define GPIO_PAR_ATA_CS0_GPIO (0x0000)
-#define GPIO_PAR_ATA_DA2_DA2 (0x0080)
-#define GPIO_PAR_ATA_DA2_GPIO (0x0000)
-#define GPIO_PAR_ATA_DA1_DA1 (0x0040)
-#define GPIO_PAR_ATA_DA1_GPIO (0x0000)
-#define GPIO_PAR_ATA_DA0_DA0 (0x0020)
-#define GPIO_PAR_ATA_DA0_GPIO (0x0000)
-#define GPIO_PAR_ATA_RESET_RESET (0x0004)
-#define GPIO_PAR_ATA_RESET_GPIO (0x0000)
-#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
-#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
-#define GPIO_PAR_ATA_IORDY_IORDY (0x0001)
-#define GPIO_PAR_ATA_IORDY_GPIO (0x0000)
-
-/* Bit definitions and macros for PAR_IRQ */
-#define GPIO_PAR_IRQ_IRQ1 (0x02)
-#define GPIO_PAR_IRQ_IRQ4 (0x10)
-#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
-#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
-#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
-#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_PCI */
-#define GPIO_PAR_PCI_REQ0 (0x0001)
-#define GPIO_PAR_PCI_REQ1 (0x0004)
-#define GPIO_PAR_PCI_REQ2 (0x0010)
-#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
-#define GPIO_PAR_PCI_GNT0 (0x0100)
-#define GPIO_PAR_PCI_GNT1 (0x0400)
-#define GPIO_PAR_PCI_GNT2 (0x1000)
-#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
-#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF)
-#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
-#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
-#define GPIO_PAR_PCI_GNT3_GPIO (0x0000)
-#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
-#define GPIO_PAR_PCI_GNT2_GPIO (0x0000)
-#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
-#define GPIO_PAR_PCI_GNT1_GPIO (0x0000)
-#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
-#define GPIO_PAR_PCI_GNT0_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F)
-#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
-#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
-#define GPIO_PAR_PCI_REQ3_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
-#define GPIO_PAR_PCI_REQ2_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
-#define GPIO_PAR_PCI_REQ1_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
-#define GPIO_PAR_PCI_REQ0_GPIO (0x0000)
-
-/* Bit definitions and macros for MSCR_SDRAM */
-#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
-#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
-#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
-#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
-#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F)
-#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
-#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
-#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
-#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF)
-#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
-#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
-#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
-#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
-#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
-#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
-#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
-#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
-#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
-#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
-#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
-#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
-
-/* Bit definitions and macros for MSCR_PCI */
-#define GPIO_MSCR_PCI_PCI (0x01)
-#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
-#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
-
-/* Bit definitions and macros for DSCR_I2C */
-#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
-#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
-#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
-#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
-#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_FLEXBUS */
-#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
-#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
-#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
-#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_FEC */
-#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
-#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
-#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
-#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
-#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
-#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
-#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
-#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
-#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
-#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_UART */
-#define GPIO_DSCR_UART_UART0(x) (((x)&0x03))
-#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
-#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
-#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
-#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
-#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
-#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
-#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
-#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
-#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_DSPI */
-#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
-#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_TIMER */
-#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
-#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_SSI */
-#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
-#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
-#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
-#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
-#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_DMA */
-#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
-#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
-#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
-#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
-#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_DEBUG */
-#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_RESET */
-#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
-#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
-#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
-#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
-#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_IRQ */
-#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
-#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_USB */
-#define GPIO_DSCR_USB_USB(x) (((x)&0x03))
-#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
-#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
-#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
-#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_ATA */
-#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
-#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
-#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
-#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
-#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
-
-/*********************************************************************
-* SDRAM Controller (SDRAMC)
-*********************************************************************/
-
-/* Bit definitions and macros for SDMR */
-#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
-#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
-#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
-#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
-#define SDRAMC_SDMR_BK_LMR (0x00000000)
-#define SDRAMC_SDMR_BK_LEMR (0x40000000)
-
-/* Bit definitions and macros for SDCR */
-#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
-#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
-#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
-#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
-#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
-#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
-#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
-#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
-#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
-#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
-#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
-#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
-#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
-#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
-
-/* Bit definitions and macros for SDCFG1 */
-#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
-#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
-#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
-#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
-#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
-#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
-#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
-
-/* Bit definitions and macros for SDCFG2 */
-#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
-#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
-#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
-#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
-
-/* Bit definitions and macros for SDCS group */
-#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
-#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
-#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
-#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
-#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
-#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
-#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
-#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
-#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
-#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
-#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
-#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
-#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
-#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
-#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
-#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
-#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
-
-/*********************************************************************
-* Phase Locked Loop (PLL)
-*********************************************************************/
-
-/* Bit definitions and macros for PCR */
-#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
-#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */
-#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */
-#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */
-#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
-#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
-#define PLL_PCR_PFDR_MASK (0x000F0000)
-#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
-#define PLL_PCR_OUTDIV4_MASK (0x0000F000)
-#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
-#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
-#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
-
-/* Bit definitions and macros for PSR */
-#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
-#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
-#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
-#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
-
-/*********************************************************************
-* PCI
-*********************************************************************/
-
-/* Bit definitions and macros for SCR */
-#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
-#define PCI_SCR_SE (0x40000000) /* System error signalled */
-#define PCI_SCR_MA (0x20000000) /* Master aboart received */
-#define PCI_SCR_TR (0x10000000) /* Target abort received */
-#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
-#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
-#define PCI_SCR_DP (0x01000000) /* Master data parity err */
-#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
-#define PCI_SCR_R (0x00400000) /* Reserved */
-#define PCI_SCR_66M (0x00200000) /* 66Mhz */
-#define PCI_SCR_C (0x00100000) /* Capabilities list */
-#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
-#define PCI_SCR_S (0x00000100) /* SERR enable */
-#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
-#define PCI_SCR_PER (0x00000040) /* Parity error response */
-#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
-#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
-#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
-#define PCI_SCR_B (0x00000004) /* Bus master enable */
-#define PCI_SCR_M (0x00000002) /* Memory access control */
-#define PCI_SCR_IO (0x00000001) /* I/O access control */
-
-#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
-#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
-#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
-#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
-
-#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
-#define PCI_BAR_BAR1(x) (x & 0xFFF00000)
-#define PCI_BAR_BAR2(x) (x & 0xFFC00000)
-#define PCI_BAR_BAR3(x) (x & 0xFF000000)
-#define PCI_BAR_BAR4(x) (x & 0xF8000000)
-#define PCI_BAR_BAR5(x) (x & 0xE0000000)
-#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
-#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
-#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
-
-#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
-#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
-#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
-#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
-
-#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
-#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
-#define PCI_GSCR_SE (0x10000000) /* SERR detected */
-#define PCI_GSCR_ER (0x08000000) /* Error response detected */
-#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
-#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
-#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
-#define PCI_GSCR_PR (0x00000001) /* PCI reset */
-
-#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
-#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
-#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
-#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
-
-#define PCI_TCR2_B5E (0x00002000) /* */
-#define PCI_TCR2_B4E (0x00001000) /* */
-#define PCI_TCR2_B3E (0x00000800) /* */
-#define PCI_TCR2_B2E (0x00000400) /* */
-#define PCI_TCR2_B1E (0x00000200) /* */
-#define PCI_TCR2_B0E (0x00000100) /* */
-#define PCI_TCR2_CR (0x00000001) /* */
-
-#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
-#define PCI_TBATR_EN (0x00000001) /* Enable */
-
-#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
-#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
-#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
-#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
-#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
-#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
-#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
-#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
-#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
-
-#define PCI_ICR_REE (0x04000000) /* Retry error enable */
-#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
-#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
-#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
-
-/********************************************************************/
-
-#endif /* __MCF5445X__ */
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index 113838f..179511a 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -9,19 +9,15 @@
*/
#include <common.h>
-#include <cpsw.h>
#include <dm.h>
-#include <env.h>
#include <env_internal.h>
#include <errno.h>
#include <i2c.h>
-#include <init.h>
#include <led.h>
-#include <miiphy.h>
#include <panel.h>
+#include <linux/delay.h>
#include <asm/global_data.h>
#include <power/tps65217.h>
-#include <power/tps65910.h>
#include <spl.h>
#include <watchdog.h>
#include <asm/arch/clock.h>
@@ -29,13 +25,17 @@
#include <asm/arch/ddr_defs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem-guardian.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <jffs2/load_kernel.h>
+#include <mtd.h>
+#include <nand.h>
+#include <video.h>
+#include <video_console.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -193,27 +193,11 @@
#ifdef CONFIG_BOARD_LATE_INIT
static void set_bootmode_env(void)
{
- char *boot_device_name = NULL;
char *boot_mode_gpio = "gpio@44e07000_14";
int ret;
- int value;
struct gpio_desc boot_mode_desc;
- switch (gd->arch.omap_boot_device) {
- case BOOT_DEVICE_NAND:
- boot_device_name = "nand";
- break;
- case BOOT_DEVICE_USBETH:
- boot_device_name = "usbeth";
- break;
- default:
- break;
- }
-
- if (boot_device_name)
- env_set("boot_device", boot_device_name);
-
ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
if (ret) {
printf("%s is not found\n", boot_mode_gpio);
@@ -226,20 +210,138 @@
goto err;
}
- value = dm_gpio_get_value(&boot_mode_desc);
- value ? env_set("swi_status", "0") : env_set("swi_status", "1");
+ dm_gpio_set_dir_flags(&boot_mode_desc, GPIOD_IS_IN);
+ udelay(10);
+
+ ret = dm_gpio_get_value(&boot_mode_desc);
+ if (ret == 0) {
+ env_set("swi_status", "1");
+ } else if (ret == 1) {
+ env_set("swi_status", "0");
+ } else {
+ printf("swi status gpio error\n");
+ goto err;
+ }
+
return;
err:
env_set("swi_status", "err");
}
+void lcdbacklight_en(void)
+{
+ unsigned long brightness = env_get_ulong("backlight_brightness", 10, 50);
+
+ if (brightness > 99 || brightness == 0)
+ brightness = 99;
+
+ /*
+ * Brightness range:
+ * WLEDCTRL2 DUTY[6:0]
+ *
+ * 000 0000b = 1%
+ * 000 0001b = 2%
+ * ...
+ * 110 0010b = 99%
+ * 110 0011b = 100%
+ *
+ */
+
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
+ brightness, 0xFF);
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
+ brightness != 0 ? 0x0A : 0x02, 0xFF);
+}
+
+#if IS_ENABLED(CONFIG_AM335X_LCD)
+static void splash_screen(void)
+{
+ struct udevice *video_dev;
+ struct udevice *console_dev;
+ struct video_priv *vid_priv;
+ struct mtd_info *mtd;
+ size_t len;
+ int ret;
+
+ struct mtd_device *mtd_dev;
+ struct part_info *part;
+ u8 pnum;
+
+ ret = uclass_get_device(UCLASS_VIDEO, 0, &video_dev);
+ if (ret != 0) {
+ debug("video device not found\n");
+ goto exit;
+ }
+
+ vid_priv = dev_get_uclass_priv(video_dev);
+ mtdparts_init();
+
+ if (find_dev_and_part(SPLASH_SCREEN_NAND_PART, &mtd_dev, &pnum, &part)) {
+ debug("Could not find nand partition\n");
+ goto splash_screen_text;
+ }
+
+ mtd = get_nand_dev_by_index(mtd_dev->id->num);
+ if (!mtd) {
+ debug("MTD partition is not valid\n");
+ goto splash_screen_text;
+ }
+
+ len = SPLASH_SCREEN_BMP_FILE_SIZE;
+ ret = nand_read_skip_bad(mtd, part->offset, &len, NULL,
+ SPLASH_SCREEN_BMP_FILE_SIZE,
+ (u_char *)SPLASH_SCREEN_BMP_LOAD_ADDR);
+ if (ret != 0) {
+ debug("Reading NAND partition failed\n");
+ goto splash_screen_text;
+ }
+
+ ret = video_bmp_display(video_dev, SPLASH_SCREEN_BMP_LOAD_ADDR, 0, 0, false);
+ if (ret != 0) {
+ debug("No valid bmp image found!!\n");
+ goto splash_screen_text;
+ } else {
+ goto exit;
+ }
+
+splash_screen_text:
+ vid_priv->colour_fg = CONSOLE_COLOR_RED;
+ vid_priv->colour_bg = CONSOLE_COLOR_BLACK;
+
+ if (!uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &console_dev)) {
+ debug("Found console\n");
+ vidconsole_position_cursor(console_dev, 17, 7);
+ vidconsole_put_string(console_dev, SPLASH_SCREEN_TEXT);
+ } else {
+ debug("No console device found\n");
+ }
+
+exit:
+ return;
+}
+#endif /* CONFIG_AM335X_LCD */
+
int board_late_init(void)
{
+ int ret;
+ struct udevice *cdev;
+
#ifdef CONFIG_LED_GPIO
led_default_state();
#endif
set_bootmode_env();
+
+ ret = uclass_get_device(UCLASS_PANEL, 0, &cdev);
+ if (ret) {
+ debug("video panel not found: %d\n", ret);
+ return ret;
+ }
+
+ lcdbacklight_en();
+ if (IS_ENABLED(CONFIG_AM335X_LCD))
+ splash_screen();
+
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c
index 9c81f29..12c3eb6 100644
--- a/board/bosch/guardian/mux.c
+++ b/board/bosch/guardian/mux.c
@@ -28,8 +28,9 @@
static struct module_pin_mux guardian_interfaces_pin_mux[] = {
{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
+ {OFFSET(mii1_txen), (MODE(7) | PULLDOWN_EN)},
{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
- {OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)},
+ {OFFSET(mdio_clk), (MODE(7) | PULLUP_EN)},
{OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
{OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
{OFFSET(mii1_crs), (MODE(7) | PULLDOWN_EN)},
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 47a7024..891bc00 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -781,7 +781,7 @@
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
diff --git a/board/freescale/m52277evb/Kconfig b/board/freescale/m52277evb/Kconfig
deleted file mode 100644
index c427892..0000000
--- a/board/freescale/m52277evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M52277EVB
-
-config SYS_CPU
- default "mcf5227x"
-
-config SYS_BOARD
- default "m52277evb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M52277EVB"
-
-endif
diff --git a/board/freescale/m52277evb/MAINTAINERS b/board/freescale/m52277evb/MAINTAINERS
deleted file mode 100644
index a2a2176..0000000
--- a/board/freescale/m52277evb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-M52277EVB BOARD
-M: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
-S: Maintained
-F: board/freescale/m52277evb/
-F: include/configs/M52277EVB.h
-F: configs/M52277EVB_defconfig
-F: configs/M52277EVB_stmicro_defconfig
diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile
deleted file mode 100644
index f98b0c9..0000000
--- a/board/freescale/m52277evb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = m52277evb.o
diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README
deleted file mode 100644
index 8bfd812..0000000
--- a/board/freescale/m52277evb/README
+++ /dev/null
@@ -1,228 +0,0 @@
-Freescale MCF52277EVB ColdFire Development Board
-================================================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created Jan 8, 2008
-===========================================
-
-
-Changed files:
-==============
-
-- board/freescale/m52277evb/m52277evb.c Dram setup
-- board/freescale/m52277evb/Makefile Makefile
-- board/freescale/m52277evb/config.mk config make
-- board/freescale/m52277evb/u-boot.lds Linker description
-
-- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code
-- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
-- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
-- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock
-- arch/m68k/cpu/mcf5227x/Makefile Makefile
-- arch/m68k/cpu/mcf5227x/config.mk config make
-- arch/m68k/cpu/mcf5227x/start.S start up assembly code
-
-- board/freescale/m52277evb/README This readme file
-
-- drivers/serial/mcfuart.c ColdFire common UART driver
-- drivers/rtc/mcfrtc.c Realtime clock Driver
-
-- include/asm-m68k/bitops.h Bit operation function export
-- include/asm-m68k/byteorder.h Byte order functions
-- include/asm-m68k/crossbar.h CrossBar structure and definition
-- include/asm-m68k/dspi.h DSPI structure and definition
-- include/asm-m68k/edma.h eDMA structure and definition
-- include/asm-m68k/flexbus.h FlexBus structure and definition
-- include/asm-m68k/fsl_i2c.h I2C structure and definition
-- include/asm-m68k/global_data.h Global data structure
-- include/asm-m68k/immap.h ColdFire specific header file and driver macros
-- include/asm-m68k/immap_5227x.h mcf5227x specific header file
-- include/asm-m68k/io.h io functions
-- include/asm-m68k/lcd.h LCD structure and definition
-- include/asm-m68k/m5227x.h mcf5227x specific header file
-- include/asm-m68k/posix_types.h Posix
-- include/asm-m68k/processor.h header file
-- include/asm-m68k/ptrace.h Exception structure
-- include/asm-m68k/rtc.h Realtime clock header file
-- include/asm-m68k/ssi.h SSI structure and definition
-- include/asm-m68k/string.h String function export
-- include/asm-m68k/timer.h Timer structure and definition
-- include/asm-m68k/types.h Data types definition
-- include/asm-m68k/uart.h Uart structure and definition
-- include/asm-m68k/u-boot.h U-Boot structure
-
-- include/configs/M52277EVB.h Board specific configuration file
-
-- arch/m68k/lib/board.c board init function
-- arch/m68k/lib/cache.c
-- arch/m68k/lib/interrupts Coldfire common interrupt functions
-- arch/m68k/lib/m68k_linux.c
-- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
-- arch/m68k/lib/traps.c Exception init code
-
-1 MCF52277 specific Options/Settings
-====================================
-1.1 pre-loader is no longer suppoer in this coldfire family
-
-1.2 Configuration settings for M52277EVB Development Board
-CONFIG_MCF5227x -- define for all MCF5227x CPUs
-CONFIG_M52277 -- define for all Freescale MCF52277 CPUs
-
-CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
-CONFIG_BAUDRATE -- define UART baudrate
-
-CONFIG_MCFRTC -- define to use common CF RTC driver
-CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
-CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
-RTC_DEBUG -- define to show RTC debug message
-CONFIG_CMD_DATE -- enable to use date feature in U-Boot
-
-CONFIG_MCFTMR -- define to use DMA timer
-
-CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
-CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
-CONFIG_SYS_I2C_SPEED -- define for I2C speed
-CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
-CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
-CONFIG_SYS_IMMR -- define for MBAR offset
-
-CONFIG_SYS_MBAR -- define MBAR offset
-
-CONFIG_MONITOR_IS_IN_RAM -- Not support
-
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM
-
-CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
-CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
-CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
-
-CONFIG_LCD and CONFIG_CMD_USB are not supported in this current U-Boot,
-update will be provided at later time
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. System memory map:
- Flash: 0x00000000-0x3FFFFFFF (1024MB)
- DDR: 0x40000000-0x7FFFFFFF (1024MB)
- SRAM: 0x80000000-0x8FFFFFFF (256MB)
- IP: 0xF0000000-0xFFFFFFFF (256MB)
-
-2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
- linux kernel, you can customize it based on your system requirements:
- Flash0: 0x00000000-0x00FFFFFF (16MB)
-
- DDR: 0x40000000-0x4FFFFFFF (64MB)
- SRAM: 0x80000000-0x80007FFF (32KB)
- IP: 0xFC000000-0xFC0FFFFF (64KB)
-
-3. COMPILATION
-==============
-3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
-uClinux version) from codesourcery.com was used. Download it from:
-http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
-
-3.2 Compilation
- export CROSS_COMPILE=cross-compile-prefix
- cd u-boot-1.x.x
- make distclean
- make M52277EVB_config
- make
-
-4. SCREEN DUMP
-==============
-4.1 M52277EVB Development board
- (NOTE: May not show exactly the same)
-
-U-Boot 1.3.1 (Jan 8 2008 - 12:44:08)
-
-CPU: Freescale MCF52277 (Mask:6c Version:0)
- CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
- INP CLK 16 Mhz VCO CLK 480 Mhz
-Board: Freescale 52277 EVB
-I2C: ready
-DRAM: 64 MB
-FLASH: 16 MB
-In: serial
-Out: serial
-Err: serial
--> print
-baudrate=115200
-hostname=M52277EVB
-inpclk=16000000
-loadaddr=(0x40000000 + 0x10000)
-load=tftp ${loadaddr) ${u-boot}
-upd=run load; run prog
-prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
-u-boot=u-boot.bin
-stdin=serial
-stdout=serial
-stderr=serial
-mem=65024k
-
-Environment size: 280/32764 bytes
--> bdinfo
-memstart = 0x40000000
-memsize = 0x04000000
-flashstart = 0x00000000
-flashsize = 0x01000000
-flashoffset = 0x00000000
-sramstart = 0x80000000
-sramsize = 0x00008000
-mbar = 0xFC000000
-busfreq = 80 MHz
-flbfreq = 80 Mhz
-inpfreq = 16 Mhz
-vcofreq = 480 Mhz
-
-baudrate = 115200 bps
-->
--> help
-? - alias for 'help'
-base - print or set address offset
-bdinfo - print Board Info structure
-boot - boot default, i.e., run 'bootcmd'
-bootd - boot default, i.e., run 'bootcmd'
-bootelf - Boot from an ELF image in memory
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-bootvx - Boot vxWorks from an ELF image
-cmp - memory compare
-coninfo - print console devices and information
-cp - memory copy
-crc32 - checksum calculation
-date - get/set/reset date & time
-dcache - enable or disable data cache
-echo - echo args to console
-erase - erase FLASH memory
-flinfo - print FLASH memory information
-go - start application at address 'addr'
-help - print online help
-i2c - I2C sub-system
-icache - enable or disable instruction cache
-iminfo - print header information for application image
-imls - list all images found in flash
-itest - return true/false on integer compare
-loadb - load binary file over serial line (kermit mode)
-loads - load S-Record file over serial line
-loady - load binary file over serial line (ymodem mode)
-loop - infinite loop on address range
-ls - list files in a directory (default /)
-md - memory display
-mm - memory modify (auto-incrementing)
-mtest - simple RAM test
-mw - memory write (fill)
-nm - memory modify (constant address)
-ping - send ICMP ECHO_REQUEST to network host
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sleep - delay execution for some time
-source - run script from memory
-version - print monitor version
-->
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
deleted file mode 100644
index 510af33..0000000
--- a/board/freescale/m52277evb/m52277evb.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("Board: ");
- puts("Freescale M52277 EVB\n");
- return 0;
-};
-
-int dram_init(void)
-{
- u32 dramsize;
-
-#ifdef CONFIG_CF_SBF
- /*
- * Serial Boot: The dram is already initialized in start.S
- * only require to return DRAM size
- */
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-#else
- sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
- gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
- u32 i;
-
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
- i--;
-
- out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
-
- out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
-
- out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
- __asm__("nop");
-
- /* Issue LEMR */
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
- __asm__("nop");
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
- __asm__("nop");
-
- udelay(1000);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
- __asm__("nop");
-
- /* Perform two refresh cycles */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- __asm__("nop");
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- __asm__("nop");
-
- out_be32(&sdram->sdcr,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
-
- udelay(100);
-#endif
- gd->ram_size = dramsize;
-
- return 0;
-};
-
-int testdram(void)
-{
- /* TODO: XXX XXX XXX */
- printf("DRAM test not implemented!\n");
-
- return (0);
-}
diff --git a/board/freescale/m54418twr/Kconfig b/board/freescale/m54418twr/Kconfig
deleted file mode 100644
index 4199a3f..0000000
--- a/board/freescale/m54418twr/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M54418TWR
-
-config SYS_CPU
- default "mcf5445x"
-
-config SYS_BOARD
- default "m54418twr"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M54418TWR"
-
-endif
diff --git a/board/freescale/m54418twr/MAINTAINERS b/board/freescale/m54418twr/MAINTAINERS
deleted file mode 100644
index f88aed9..0000000
--- a/board/freescale/m54418twr/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-M54418TWR BOARD
-#M: -
-S: Maintained
-F: board/freescale/m54418twr/
-F: include/configs/M54418TWR.h
-F: configs/M54418TWR_defconfig
-F: configs/M54418TWR_nand_mii_defconfig
-F: configs/M54418TWR_nand_rmii_defconfig
-F: configs/M54418TWR_nand_rmii_lowfreq_defconfig
-F: configs/M54418TWR_serial_mii_defconfig
-F: configs/M54418TWR_serial_rmii_defconfig
diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile
deleted file mode 100644
index aa53874..0000000
--- a/board/freescale/m54418twr/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright 2010-2012 Freescale Semiconductor, Inc.
-# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
-
-obj-y = m54418twr.o
-extra-y += sbf_dram_init.o
-
diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
deleted file mode 100644
index ca89931..0000000
--- a/board/freescale/m54418twr/m54418twr.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <spi.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/immap.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- /*
- * need to to:
- * Check serial flash size. if 2mb evb, else 8mb demo
- */
- puts("Board: ");
- puts("Freescale MCF54418 Tower System\n");
- return 0;
-};
-
-int dram_init(void)
-{
- u32 dramsize;
-
-#if defined(CONFIG_SERIAL_BOOT)
- /*
- * Serial Boot: The dram is already initialized in start.S
- * only require to return DRAM size
- */
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-#else
- sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
- ccm_t *ccm = (ccm_t *)MMAP_CCM;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- pm_t *pm = (pm_t *) MMAP_PM;
- u32 i;
-
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
-
- out_8(&pm->pmcr0, 0x2E);
- out_8(&gpio->mscr_sdram, 1);
-
- clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
- setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
-
- out_be32(&sdram->rcrcr, 0x40000000);
- out_be32(&sdram->padcr, 0x01030203);
-
- out_be32(&sdram->cr00, 0x01010101);
- out_be32(&sdram->cr01, 0x00000101);
- out_be32(&sdram->cr02, 0x01010100);
- out_be32(&sdram->cr03, 0x01010000);
- out_be32(&sdram->cr04, 0x00010101);
- out_be32(&sdram->cr06, 0x00010100);
- out_be32(&sdram->cr07, 0x00000001);
- out_be32(&sdram->cr08, 0x01000001);
- out_be32(&sdram->cr09, 0x00000100);
- out_be32(&sdram->cr10, 0x00010001);
- out_be32(&sdram->cr11, 0x00000200);
- out_be32(&sdram->cr12, 0x01000002);
- out_be32(&sdram->cr13, 0x00000000);
- out_be32(&sdram->cr14, 0x00000100);
- out_be32(&sdram->cr15, 0x02000100);
- out_be32(&sdram->cr16, 0x02000407);
- out_be32(&sdram->cr17, 0x02030007);
- out_be32(&sdram->cr18, 0x02000100);
- out_be32(&sdram->cr19, 0x0A030203);
- out_be32(&sdram->cr20, 0x00020708);
- out_be32(&sdram->cr21, 0x00050008);
- out_be32(&sdram->cr22, 0x04030002);
- out_be32(&sdram->cr23, 0x00000004);
- out_be32(&sdram->cr24, 0x020A0000);
- out_be32(&sdram->cr25, 0x0C00000E);
- out_be32(&sdram->cr26, 0x00002004);
- out_be32(&sdram->cr28, 0x00100010);
- out_be32(&sdram->cr29, 0x00100010);
- out_be32(&sdram->cr31, 0x07990000);
- out_be32(&sdram->cr40, 0x00000000);
- out_be32(&sdram->cr41, 0x00C80064);
- out_be32(&sdram->cr42, 0x44520002);
- out_be32(&sdram->cr43, 0x00C80023);
- out_be32(&sdram->cr45, 0x0000C350);
- out_be32(&sdram->cr56, 0x04000000);
- out_be32(&sdram->cr57, 0x03000304);
- out_be32(&sdram->cr58, 0x40040000);
- out_be32(&sdram->cr59, 0xC0004004);
- out_be32(&sdram->cr60, 0x0642C000);
- out_be32(&sdram->cr61, 0x00000642);
- asm("tpf");
-
- out_be32(&sdram->cr09, 0x01000100);
-
- udelay(100);
-#endif
- gd->ram_size = dramsize;
-
- return 0;
-};
-
-int testdram(void)
-{
- return 0;
-}
diff --git a/board/freescale/m54418twr/sbf_dram_init.S b/board/freescale/m54418twr/sbf_dram_init.S
deleted file mode 100644
index 5a70fb9..0000000
--- a/board/freescale/m54418twr/sbf_dram_init.S
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Board-specific sbf ddr/sdram init.
- *
- * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
- */
-
-.global sbf_dram_init
-.text
-
-sbf_dram_init:
- move.l #0xFC04002D, %a1
- move.b #46, (%a1) /* DDR */
-
- /* slew settings */
- move.l #0xEC094060, %a1
- move.b #0, (%a1)
-
- /* use vco instead of cpu*2 clock for ddr clock */
- move.l #0xEC09001A, %a1
- move.w #0xE01D, (%a1)
-
- /* DDR settings */
- move.l #0xFC0B8180, %a1
- move.l #0x00000000, (%a1)
- move.l #0x40000000, (%a1)
-
- move.l #0xFC0B81AC, %a1
- move.l #0x01030203, (%a1)
-
- move.l #0xFC0B8000, %a1
- move.l #0x01010101, (%a1)+ /* 0x00 */
- move.l #0x00000101, (%a1)+ /* 0x04 */
- move.l #0x01010100, (%a1)+ /* 0x08 */
- move.l #0x01010000, (%a1)+ /* 0x0C */
- move.l #0x00010101, (%a1)+ /* 0x10 */
- move.l #0xFC0B8018, %a1
- move.l #0x00010100, (%a1)+ /* 0x18 */
- move.l #0x00000001, (%a1)+ /* 0x1C */
- move.l #0x01000001, (%a1)+ /* 0x20 */
- move.l #0x00000100, (%a1)+ /* 0x24 */
- move.l #0x00010001, (%a1)+ /* 0x28 */
- move.l #0x00000200, (%a1)+ /* 0x2C */
- move.l #0x01000002, (%a1)+ /* 0x30 */
- move.l #0x00000000, (%a1)+ /* 0x34 */
- move.l #0x00000100, (%a1)+ /* 0x38 */
- move.l #0x02000100, (%a1)+ /* 0x3C */
- move.l #0x02000407, (%a1)+ /* 0x40 */
- move.l #0x02030007, (%a1)+ /* 0x44 */
- move.l #0x02000100, (%a1)+ /* 0x48 */
- move.l #0x0A030203, (%a1)+ /* 0x4C */
- move.l #0x00020708, (%a1)+ /* 0x50 */
- move.l #0x00050008, (%a1)+ /* 0x54 */
- move.l #0x04030002, (%a1)+ /* 0x58 */
- move.l #0x00000004, (%a1)+ /* 0x5C */
- move.l #0x020A0000, (%a1)+ /* 0x60 */
- move.l #0x0C00000E, (%a1)+ /* 0x64 */
- move.l #0x00002004, (%a1)+ /* 0x68 */
- move.l #0x00000000, (%a1)+ /* 0x6C */
- move.l #0x00100010, (%a1)+ /* 0x70 */
- move.l #0x00100010, (%a1)+ /* 0x74 */
- move.l #0x00000000, (%a1)+ /* 0x78 */
- move.l #0x07990000, (%a1)+ /* 0x7C */
- move.l #0xFC0B80A0, %a1
- move.l #0x00000000, (%a1)+ /* 0xA0 */
- move.l #0x00C80064, (%a1)+ /* 0xA4 */
- move.l #0x44520002, (%a1)+ /* 0xA8 */
- move.l #0x00C80023, (%a1)+ /* 0xAC */
- move.l #0xFC0B80B4, %a1
- move.l #0x0000C350, (%a1) /* 0xB4 */
- move.l #0xFC0B80E0, %a1
- move.l #0x04000000, (%a1)+ /* 0xE0 */
- move.l #0x03000304, (%a1)+ /* 0xE4 */
- move.l #0x40040000, (%a1)+ /* 0xE8 */
- move.l #0xC0004004, (%a1)+ /* 0xEC */
- move.l #0x0642C000, (%a1)+ /* 0xF0 */
- move.l #0x00000642, (%a1)+ /* 0xF4 */
- move.l #0xFC0B8024, %a1
- tpf
- move.l #0x01000100, (%a1) /* 0x24 */
-
- move.l #0x2000, %d1
- bsr asm_delay
-
- rts
diff --git a/board/freescale/m54451evb/Kconfig b/board/freescale/m54451evb/Kconfig
deleted file mode 100644
index f460e51..0000000
--- a/board/freescale/m54451evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M54451EVB
-
-config SYS_CPU
- default "mcf5445x"
-
-config SYS_BOARD
- default "m54451evb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M54451EVB"
-
-endif
diff --git a/board/freescale/m54451evb/MAINTAINERS b/board/freescale/m54451evb/MAINTAINERS
deleted file mode 100644
index 52a2681..0000000
--- a/board/freescale/m54451evb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-M54451EVB BOARD
-#M: -
-S: Maintained
-F: board/freescale/m54451evb/
-F: include/configs/M54451EVB.h
-F: configs/M54451EVB_defconfig
-F: configs/M54451EVB_stmicro_defconfig
diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile
deleted file mode 100644
index 8c2c6a9..0000000
--- a/board/freescale/m54451evb/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = m54451evb.o
-extra-y += sbf_dram_init.o
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
deleted file mode 100644
index a4ddc69..0000000
--- a/board/freescale/m54451evb/m54451evb.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <spi.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- /*
- * need to to:
- * Check serial flash size. if 2mb evb, else 8mb demo
- */
- puts("Board: ");
- puts("Freescale M54451 EVB\n");
- return 0;
-};
-
-int dram_init(void)
-{
- u32 dramsize;
-#ifdef CONFIG_CF_SBF
- /*
- * Serial Boot: The dram is already initialized in start.S
- * only require to return DRAM size
- */
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-#else
- sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
- gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
- u32 i;
-
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-
- if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
- (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
- return dramsize;
-
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
- i--;
-
- out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
-
- out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
-
- out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
-
- udelay(200);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
- __asm__("nop");
-
- /* Perform two refresh cycles */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- __asm__("nop");
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- __asm__("nop");
-
- /* Issue LEMR */
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
- __asm__("nop");
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
- __asm__("nop");
-
- out_be32(&sdram->sdcr,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
-
- udelay(100);
-#endif
- gd->ram_size = dramsize;
-
- return 0;
-};
-
-int testdram(void)
-{
- /* TODO: XXX XXX XXX */
- printf("DRAM test not implemented!\n");
-
- return (0);
-}
diff --git a/board/freescale/m54451evb/sbf_dram_init.S b/board/freescale/m54451evb/sbf_dram_init.S
deleted file mode 100644
index ee08cd1..0000000
--- a/board/freescale/m54451evb/sbf_dram_init.S
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Board-specific sbf ddr/sdram init.
- *
- * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
- */
-
- #include <config.h>
-
-.global sbf_dram_init
-.text
-
-sbf_dram_init:
- /* Dram Initialization a1, a2, and d0 */
- /* mscr sdram */
- move.l #0xFC0A4074, %a1
- move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
- nop
-
- /* SDRAM Chip 0 and 1 */
- move.l #0xFC0B8110, %a1
- move.l #0xFC0B8114, %a2
-
- /* calculate the size */
- move.l #0x13, %d1
- move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
-#ifdef CONFIG_SYS_SDRAM_BASE1
- lsr.l #1, %d2
-#endif
-
-dramsz_loop:
- lsr.l #1, %d2
- add.l #1, %d1
- cmp.l #1, %d2
- bne dramsz_loop
-#ifdef CONFIG_SYS_NAND_BOOT
- beq asm_nand_chk_status
-#endif
- /* SDRAM Chip 0 and 1 */
- move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
- or.l %d1, (%a1)
-#ifdef CONFIG_SYS_SDRAM_BASE1
- move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
- or.l %d1, (%a2)
-#endif
- nop
-
- /* dram cfg1 and cfg2 */
- move.l #0xFC0B8008, %a1
- move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
- nop
- move.l #0xFC0B800C, %a2
- move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
- nop
-
- move.l #0xFC0B8000, %a1 /* Mode */
- move.l #0xFC0B8004, %a2 /* Ctrl */
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- move.l #1000, %d1
- bsr asm_delay
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- /* Perform two refresh cycles */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
- nop
- move.l %d0, (%a2)
- move.l %d0, (%a2)
- nop
-
- /* Issue LEMR */
- move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
- nop
- move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
-
- move.l #500, %d1
- bsr asm_delay
-
- move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
- and.l #0x7FFFFFFF, %d1
-
- or.l #0x10000C00, %d1
-
- move.l %d1, (%a2)
- nop
-
- move.l #2000, %d1
- bsr asm_delay
-
- rts
diff --git a/board/freescale/m54455evb/Kconfig b/board/freescale/m54455evb/Kconfig
deleted file mode 100644
index 096bce8..0000000
--- a/board/freescale/m54455evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M54455EVB
-
-config SYS_CPU
- default "mcf5445x"
-
-config SYS_BOARD
- default "m54455evb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M54455EVB"
-
-endif
diff --git a/board/freescale/m54455evb/MAINTAINERS b/board/freescale/m54455evb/MAINTAINERS
deleted file mode 100644
index 27ced3c..0000000
--- a/board/freescale/m54455evb/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-M54455EVB BOARD
-M: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
-S: Maintained
-F: board/freescale/m54455evb/
-F: include/configs/M54455EVB.h
-F: configs/M54455EVB_defconfig
-F: configs/M54455EVB_a66_defconfig
-F: configs/M54455EVB_i66_defconfig
-F: configs/M54455EVB_intel_defconfig
-F: configs/M54455EVB_stm33_defconfig
diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile
deleted file mode 100644
index eff8ab0..0000000
--- a/board/freescale/m54455evb/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = m54455evb.o
-extra-y += sbf_dram_init.o
diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README
deleted file mode 100644
index 26d3cc8..0000000
--- a/board/freescale/m54455evb/README
+++ /dev/null
@@ -1,407 +0,0 @@
-Freescale MCF54455EVB ColdFire Development Board
-================================================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created 4/08/07
-===========================================
-
-
-Changed files:
-==============
-
-- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
-- board/freescale/m54455evb/flash.c Atmel and INTEL flash support
-- board/freescale/m54455evb/Makefile Makefile
-- board/freescale/m54455evb/config.mk config make
-- board/freescale/m54455evb/u-boot.lds Linker description
-
-- common/cmd_bdinfo.c Clock frequencies output
-- common/cmd_mii.c mii support
-
-- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
-- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
-- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
-- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
-- arch/m68k/cpu/mcf5445x/Makefile Makefile
-- arch/m68k/cpu/mcf5445x/config.mk config make
-- arch/m68k/cpu/mcf5445x/start.S start up assembly code
-
-- board/freescale/m54455evb/README This readme file
-
-- drivers/net/mcffec.c ColdFire common FEC driver
-- drivers/serial/mcfuart.c ColdFire common UART driver
-
-- include/asm-m68k/bitops.h Bit operation function export
-- include/asm-m68k/byteorder.h Byte order functions
-- include/asm-m68k/fec.h FEC structure and definition
-- include/asm-m68k/fsl_i2c.h I2C structure and definition
-- include/asm-m68k/global_data.h Global data structure
-- include/asm-m68k/immap.h ColdFire specific header file and driver macros
-- include/asm-m68k/immap_5445x.h mcf5445x specific header file
-- include/asm-m68k/io.h io functions
-- include/asm-m68k/m5445x.h mcf5445x specific header file
-- include/asm-m68k/posix_types.h Posix
-- include/asm-m68k/processor.h header file
-- include/asm-m68k/ptrace.h Exception structure
-- include/asm-m68k/rtc.h Realtime clock header file
-- include/asm-m68k/string.h String function export
-- include/asm-m68k/timer.h Timer structure and definition
-- include/asm-m68k/types.h Data types definition
-- include/asm-m68k/uart.h Uart structure and definition
-- include/asm-m68k/u-boot.h U-Boot structure
-
-- include/configs/M54455EVB.h Board specific configuration file
-
-- arch/m68k/lib/board.c board init function
-- arch/m68k/lib/cache.c
-- arch/m68k/lib/interrupts Coldfire common interrupt functions
-- arch/m68k/lib/m68k_linux.c
-- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
-- arch/m68k/lib/traps.c Exception init code
-
-- rtc/mcfrtc.c Realtime clock Driver
-
-1 MCF5445x specific Options/Settings
-====================================
-1.1 pre-loader is no longer suppoer in thie coldfire family
-
-1.2 Configuration settings for M54455EVB Development Board
-CONFIG_MCF5445x -- define for all MCF5445x CPUs
-CONFIG_M54455 -- define for all Freescale MCF54455 CPUs
-CONFIG_M54455EVB -- define for M54455EVB board
-
-CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
-CONFIG_BAUDRATE -- define UART baudrate
-
-CONFIG_MCFRTC -- define to use common CF RTC driver
-CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
-CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
-RTC_DEBUG -- define to show RTC debug message
-CONFIG_CMD_DATE -- enable to use date feature in U-Boot
-
-CONFIG_MCFFEC -- define to use common CF FEC driver
-CONFIG_MII -- enable to use MII driver
-CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
-CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
-CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
-CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
-CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
-CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
-CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
-CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
-MCFFEC_TOUT_LOOP -- set FEC timeout loop
-CONFIG_HAS_ETH1 -- define to enable second FEC in U-Boot
-
-CONFIG_ISO_PARTITION -- enable ISO read/write
-CONFIG_DOS_PARTITION -- enable DOS read/write
-CONFIG_IDE_RESET -- define ide_reset()
-CONFIG_IDE_PREINIT -- define ide_preinit()
-CONFIG_ATAPI -- define ATAPI support
-CONFIG_LBA48 -- define LBA48 (larger than 120GB) support
-CONFIG_SYS_IDE_MAXBUS -- define max channel
-CONFIG_SYS_IDE_MAXDEVICE -- define max devices per channel
-CONFIG_SYS_ATA_BASE_ADDR -- define ATA base address
-CONFIG_SYS_ATA_IDE0_OFFSET -- define ATA IDE0 offset
-CONFIG_SYS_ATA_DATA_OFFSET -- define ATA data IO
-CONFIG_SYS_ATA_REG_OFFSET -- define for normal register accesses
-CONFIG_SYS_ATA_ALT_OFFSET -- define for alternate registers
-CONFIG_SYS_ATA_STRIDE -- define for Interval between registers
-_IO_BASE -- define for IO base address
-
-CONFIG_MCFTMR -- define to use DMA timer
-
-CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver
-CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
-CONFIG_SYS_I2C_SPEED -- define for I2C speed
-CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
-CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
-CONFIG_SYS_IMMR -- define for MBAR offset
-
-CONFIG_PCI -- define for PCI support
-CONFIG_PCI_PNP -- define for Plug n play support
-CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset
-CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
-CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
-CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset
-CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset
-CONFIG_SYS_PCI_IO_SIZE -- PCI IO size
-CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset
-CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
-CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
-
-CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
-
-CONFIG_SYS_MBAR -- define MBAR offset
-
-CONFIG_SYS_ATMEL_BOOT -- To determine the U-Boot is booted from Atmel or Intel
-
-CONFIG_MONITOR_IS_IN_RAM -- Not support
-
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
-
-CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
-CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
-CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-
-CONFIG_SYS_ATMEL_BASE -- defines the Atmel Flash base
-CONFIG_SYS_INTEL_BASE -- defines the Intel Flash base
-
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
-CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. System memory map:
- Flash: 0x00000000-0x3FFFFFFF (1024MB)
- DDR: 0x40000000-0x7FFFFFFF (1024MB)
- SRAM: 0x80000000-0x8FFFFFFF (256MB)
- ATA: 0x90000000-0x9FFFFFFF (256MB)
- PCI: 0xA0000000-0xBFFFFFFF (512MB)
- FlexBus: 0xC0000000-0xDFFFFFFF (512MB)
- IP: 0xF0000000-0xFFFFFFFF (256MB)
-
-2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
- linux kernel, you can customize it based on your system requirements:
- Atmel boot:
- Flash0: 0x00000000-0x0007FFFF (512KB)
- Flash1: 0x04000000-0x05FFFFFF (32MB)
- Intel boot:
- Flash0: 0x00000000-0x01FFFFFF (32MB)
- Flash1: 0x04000000-0x0407FFFF (512KB)
-
- CPLD: 0x08000000-0x08FFFFFF (16MB)
- FPGA: 0x09000000-0x09FFFFFF (16MB)
- DDR: 0x40000000-0x4FFFFFFF (256MB)
- SRAM: 0x80000000-0x80007FFF (32KB)
- IP: 0xFC000000-0xFC0FFFFF (64KB)
-
-3. SWITCH SETTINGS
-==================
-3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
- SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
- SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
- 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
- SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
- SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
-
-4. COMPILATION
-==============
-4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
-from codesourcery.com was used. Download it from:
-http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
-
-4.2 Compilation
- export CROSS_COMPILE=cross-compile-prefix
- cd u-boot-1.x.x
- make distclean
- make M54455EVB_config, or - default to atmel 33Mhz input clock
- make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock
- make M54455EVB_a33_config, or - default to atmel 33Mhz input clock
- make M54455EVB_a66_config, or - default to atmel 66Mhz input clock
- make M54455EVB_intel_config, or - default to intel 33Mhz input clock
- make M54455EVB_i33_config, or - default to intel 33Mhz input clock
- make M54455EVB_i66_config, or - default to intel 66Mhz input clock
- make
-
-5. SCREEN DUMP
-==============
-5.1 M54455EVB Development board
- Boot from Atmel (NOTE: May not show exactly the same)
-
-U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
-
-CPU: Freescale MCF54455 (Mask:48 Version:1)
- CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
- PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
-Board: Freescale M54455 EVB
-I2C: ready
-DRAM: 256 MB
-FLASH: 16.5 MB
-In: serial
-Out: serial
-Err: serial
-Net: FEC0, FEC1
-IDE: Bus 0: not available
--> print
-bootargs=root=/dev/ram rw
-bootdelay=1
-baudrate=115200
-ethaddr=00:e0:0c:bc:e5:60
-eth1addr=00:e0:0c:bc:e5:61
-hostname=M54455EVB
-netdev=eth0
-inpclk=33333333
-loadaddr=40010000
-load=tftp ${loadaddr) ${u-boot}
-upd=run load; run prog
-prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
-ethact=FEC0
-mtdids=nor0=M54455EVB-1
-mtdparts=M54455EVB-1:16m(user)
-u-boot=u-boot54455.bin
-filesize=292b4
-fileaddr=40010000
-gatewayip=192.168.1.1
-netmask=255.255.255.0
-ipaddr=192.168.1.3
-serverip=192.168.1.2
-stdin=serial
-stdout=serial
-stderr=serial
-mem=261632k
-
-Environment size: 563/8188 bytes
--> bdinfo
-memstart = 0x40000000
-memsize = 0x10000000
-flashstart = 0x00000000
-flashsize = 0x01080000
-flashoffset = 0x00000000
-sramstart = 0x80000000
-sramsize = 0x00008000
-mbar = 0xFC000000
-busfreq = 133.333 MHz
-pcifreq = 33.333 MHz
-flbfreq = 66.666 MHz
-inpfreq = 33.333 MHz
-vcofreq = 533.333 MHz
-ethaddr = 00:E0:0C:BC:E5:60
-eth1addr = 00:E0:0C:BC:E5:61
-ip_addr = 192.168.1.3
-baudrate = 115200 bps
-->
--> help
-? - alias for 'help'
-base - print or set address offset
-bdinfo - print Board Info structure
-boot - boot default, i.e., run 'bootcmd'
-bootd - boot default, i.e., run 'bootcmd'
-bootelf - Boot from an ELF image in memory
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-bootvx - Boot vxWorks from an ELF image
-cmp - memory compare
-coninfo - print console devices and information
-cp - memory copy
-crc32 - checksum calculation
-date - get/set/reset date & time
-dcache - enable or disable data cache
-diskboot- boot from IDE device
-echo - echo args to console
-erase - erase FLASH memory
-ext2load- load binary file from a Ext2 filesystem
-ext2ls - list files in a directory (default /)
-fatinfo - print information about filesystem
-fatload - load binary file from a dos filesystem
-fatls - list files in a directory (default /)
-flinfo - print FLASH memory information
-fsinfo - print information about filesystems
-fsload - load binary file from a filesystem image
-go - start application at address 'addr'
-help - print online help
-i2c - I2C sub-system
-icache - enable or disable instruction cache
-ide - IDE sub-system
-iminfo - print header information for application image
-imls - list all images found in flash
-itest - return true/false on integer compare
-loadb - load binary file over serial line (kermit mode)
-loads - load S-Record file over serial line
-loady - load binary file over serial line (ymodem mode)
-loop - infinite loop on address range
-ls - list files in a directory (default /)
-md - memory display
-mii - MII utility commands
-mm - memory modify (auto-incrementing)
-mtest - simple RAM test
-mw - memory write (fill)
-nfs - boot image via network using NFS protocol
-nm - memory modify (constant address)
-pci - list and access PCI Configuration Space
-ping - send ICMP ECHO_REQUEST to network host
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-rarpboot- boot image via network using RARP/TFTP protocol
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sleep - delay execution for some time
-source - run script from memory
-tftpboot- boot image via network using TFTP protocol
-version - print monitor version
-->bootm 4000000
-
-## Booting image at 04000000 ...
- Image Name: Linux Kernel Image
- Created: 2007-08-14 15:13:00 UTC
- Image Type: M68K Linux Kernel Image (uncompressed)
- Data Size: 2301952 Bytes = 2.2 MB
- Load Address: 40020000
- Entry Point: 40020000
- Verifying Checksum ... OK
-OK
-Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr
-erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
-starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
-Built 1 zonelists. Total pages: 32624
-Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
-ysmap-flash.0:5M(kernel)ro,-(jffs2)
-PID hash table entries: 1024 (order: 10, 4096 bytes)
-Console: colour dummy device 80x25
-Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
-Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
-Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init)
-Mount-cache hash table entries: 1024
-NET: Registered protocol family 16
-SCSI subsystem initialized
-NET: Registered protocol family 2
-IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
-TCP established hash table entries: 8192 (order: 2, 32768 bytes)
-TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
-TCP: Hash tables configured (established 8192 bind 4096)
-TCP reno registered
-JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
-io scheduler noop registered
-io scheduler anticipatory registered
-io scheduler deadline registered
-io scheduler cfq registered (default)
-ColdFire internal UART serial driver version 1.00
-ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
-ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
-ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
-RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
-loop: loaded (max 8 devices)
-FEC ENET Version 0.2
-fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
-eth0: ethernet 00:08:ee:00:e4:19
-physmap platform flash device: 01000000 at 04000000
-physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
- Intel/Sharp Extended Query Table at 0x0031
-Using buffer write method
-cfi_cmdset_0001: Erase suspend on write enabled
-2 cmdlinepart partitions found on MTD device physmap-flash.0
-Creating 2 MTD partitions on "physmap-flash.0":
-0x00000000-0x00500000 : "kernel"
-mtd: Giving out device 0 to kernel
-0x00500000-0x01000000 : "jffs2"
-mtd: Giving out device 1 to jffs2
-mice: PS/2 mouse device common for all mice
-i2c /dev entries driver
-TCP cubic registered
-NET: Registered protocol family 1
-NET: Registered protocol family 17
-NET: Registered protocol family 15
-VFS: Mounted root (jffs2 filesystem).
-Setting the hostname to freescale
-Mounting filesystems
-mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
-Starting syslogd and klogd
-Setting up networking on loopback device:
-Setting up networking on eth0:
-eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
-Adding static route for default gateway to 172.27.255.254:
-Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
-Starting inetd:
-/ #
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
deleted file mode 100644
index c749ee4..0000000
--- a/board/freescale/m54455evb/m54455evb.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("Board: ");
- puts("Freescale M54455 EVB\n");
- return 0;
-};
-
-int dram_init(void)
-{
- u32 dramsize;
-#ifdef CONFIG_CF_SBF
- /*
- * Serial Boot: The dram is already initialized in start.S
- * only require to return DRAM size
- */
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
-#else
- sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
- gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
- u32 i;
-
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
-
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
- i--;
-
- out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
-
- out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
-
- out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
-
- /* Issue LEMR */
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
-
- udelay(500);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
-
- /* Perform two refresh cycles */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
-
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
-
- out_be32(&sdram->sdcr,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
-
- udelay(100);
-#endif
- gd->ram_size = dramsize << 1;
-
- return 0;
-};
-
-int testdram(void)
-{
- /* TODO: XXX XXX XXX */
- printf("DRAM test not implemented!\n");
-
- return (0);
-}
-
-#if defined(CONFIG_IDE)
-#include <ata.h>
-
-int ide_preinit(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- u32 tmp;
-
- tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
- setbits_8(&gpio->par_fec, tmp);
- tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
- (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
- setbits_be16(&gpio->par_feci2c, tmp);
-
- setbits_be16(&gpio->par_ata,
- GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
- GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
- GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
- GPIO_PAR_ATA_IORDY_IORDY);
- setbits_be16(&gpio->par_pci,
- GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
-
- return (0);
-}
-
-void ide_set_reset(int idereset)
-{
- atac_t *ata = (atac_t *) MMAP_ATA;
- long period;
- /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
- int piotms[5][9] = {
- {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
- {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
- {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
- {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
- {25, 70, 20, 10, 20, 5, 10, 0, 35}
- }; /* PIO 4 */
-
- if (idereset) {
- /* control reset */
- out_8(&ata->cr, 0);
- udelay(10000);
- } else {
-#define CALC_TIMING(t) (t + period - 1) / period
- period = 1000000000 / gd->bus_clk; /* period in ns */
-
- /*ata->ton = CALC_TIMING (180); */
- out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
- out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
- out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
- out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
- out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
- out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
- out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
-
- /* IORDY enable */
- out_8(&ata->cr, 0x40);
- udelay(200000);
- /* IORDY enable */
- setbits_8(&ata->cr, 0x01);
- }
-}
-#endif
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
-extern void pci_mcf5445x_init(struct pci_controller *hose);
-
-void pci_init_board(void)
-{
- pci_mcf5445x_init(&hose);
-}
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_FLASH_CFI_LEGACY)
-#include <flash.h>
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- int sect[] = CONFIG_SYS_ATMEL_SECT;
- int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
- int i, j, k;
-
- if (base != CONFIG_SYS_ATMEL_BASE)
- return 0;
-
- info->flash_id = 0x01000000;
- info->portwidth = 1;
- info->chipwidth = 1;
- info->buffer_size = 1;
- info->erase_blk_tout = 16384;
- info->write_tout = 2;
- info->buffer_write_tout = 5;
- info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
- info->cmd_reset = 0x00F0;
- info->interface = FLASH_CFI_X8;
- info->legacy_unlock = 0;
- info->manufacturer_id = (u16) ATM_MANUFACT;
- info->device_id = ATM_ID_LV040;
- info->device_id2 = 0;
-
- info->ext_addr = 0;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x0000;
- info->addr_unlock1 = 0x00000555;
- info->addr_unlock2 = 0x000002AA;
- info->name = "CFI conformant";
-
- info->size = 0;
- info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
- info->start[0] = base;
- for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
- info->size += sect[i] * sectsz[i];
-
- for (j = 0; j < sect[i]; j++, k++) {
- info->start[k + 1] = info->start[k] + sectsz[i];
- info->protect[k] = 0;
- }
- }
-
- return 1;
-}
-#endif /* CONFIG_SYS_FLASH_CFI */
diff --git a/board/freescale/m54455evb/sbf_dram_init.S b/board/freescale/m54455evb/sbf_dram_init.S
deleted file mode 100644
index fe5bb05..0000000
--- a/board/freescale/m54455evb/sbf_dram_init.S
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Board-specific sbf ddr/sdram init.
- *
- * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
- */
-
- #include <config.h>
-
-.global sbf_dram_init
-.text
-
-sbf_dram_init:
- /* Dram Initialization a1, a2, and d0 */
- /* mscr sdram */
- move.l #0xFC0A4074, %a1
- move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
- nop
-
- /* SDRAM Chip 0 and 1 */
- move.l #0xFC0B8110, %a1
- move.l #0xFC0B8114, %a2
-
- /* calculate the size */
- move.l #0x13, %d1
- move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
-#ifdef CONFIG_SYS_SDRAM_BASE1
- lsr.l #1, %d2
-#endif
-
-dramsz_loop:
- lsr.l #1, %d2
- add.l #1, %d1
- cmp.l #1, %d2
- bne dramsz_loop
-#ifdef CONFIG_SYS_NAND_BOOT
- beq asm_nand_chk_status
-#endif
- /* SDRAM Chip 0 and 1 */
- move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
- or.l %d1, (%a1)
-#ifdef CONFIG_SYS_SDRAM_BASE1
- move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
- or.l %d1, (%a2)
-#endif
- nop
-
- /* dram cfg1 and cfg2 */
- move.l #0xFC0B8008, %a1
- move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
- nop
- move.l #0xFC0B800C, %a2
- move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
- nop
-
- move.l #0xFC0B8000, %a1 /* Mode */
- move.l #0xFC0B8004, %a2 /* Ctrl */
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- /* Issue LEMR */
- move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
- nop
- move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
- nop
-
- move.l #1000, %d1
- bsr asm_delay
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- /* Perform two refresh cycles */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
- nop
- move.l %d0, (%a2)
- move.l %d0, (%a2)
- nop
-
- move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
- nop
-
- move.l #500, %d1
- bsr asm_delay
-
- move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
- and.l #0x7FFFFFFF, %d1
-
- or.l #0x10000C00, %d1
-
- move.l %d1, (%a2)
- nop
-
- move.l #2000, %d1
- bsr asm_delay
-
- rts
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 66b3d9a..84671f6 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -220,7 +220,7 @@
int board_late_init(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000);
#endif
return 0;
diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S
index 1466d97..11c2cbe 100644
--- a/board/nokia/rx51/lowlevel_init.S
+++ b/board/nokia/rx51/lowlevel_init.S
@@ -27,6 +27,9 @@
ih_magic: /* IH_MAGIC in big endian from include/image.h */
.word 0x56190527
+z_magic: /* LINUX_ARM_ZIMAGE_MAGIC */
+ .word 0x016f2818
+
/*
* Routine: save_boot_params (called after reset from start.S)
* Description: Copy attached kernel to address KERNEL_ADDRESS
@@ -75,6 +78,12 @@
ldr r4, [r0] /* r4 - 4 bytes header of kernel */
ldr r5, ih_magic /* r5 - IH_MAGIC */
cmp r4, r5
+ beq copy_kernel_loop
+
+ /* check for valid kernel zImage */
+ ldr r4, [r0, #36] /* r4 - 4 bytes header of kernel at offset 36 */
+ ldr r5, z_magic /* r5 - LINUX_ARM_ZIMAGE_MAGIC */
+ cmp r4, r5
bne copy_kernel_end /* skip if invalid image */
copy_kernel_loop:
@@ -85,7 +94,8 @@
copy_kernel_end:
mov r5, #0
- str r5, [r0] /* remove 4 bytes header of kernel */
+ str r5, [r0] /* remove 4 bytes header of kernel uImage */
+ str r5, [r0, #36] /* remove 4 bytes header of kernel zImage */
/* Fix u-boot code */
diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c
index 9134d6b..f2b9210 100644
--- a/board/tplink/wdr4300/wdr4300.c
+++ b/board/tplink/wdr4300/wdr4300.c
@@ -15,7 +15,7 @@
#include <mach/ddr.h>
#include <debug_uart.h>
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
static void wdr4300_usb_start(void)
{
void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig
index 0cf6d83..a2a5905 100644
--- a/board/tqc/tqma6/Kconfig
+++ b/board/tqc/tqma6/Kconfig
@@ -65,7 +65,6 @@
bool "TQMa6 on MBa6 Starterkit"
select DM_ETH
select USB
- select DM_USB
select CMD_USB
select USB_STORAGE
select USB_HOST_ETHER
diff --git a/cmd/Kconfig b/cmd/Kconfig
index f196e6c..e40d390 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1322,7 +1322,7 @@
config CMD_USB
bool "usb"
- depends on USB
+ depends on USB_HOST
select HAVE_BLOCK_DEVICE
help
USB support.
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
deleted file mode 100644
index bab8ac4..0000000
--- a/configs/M52277EVB_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x8000
-CONFIG_DEFAULT_DEVICE_TREE="M52277EVB"
-CONFIG_TARGET_M52277EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
deleted file mode 100644
index 98c64ff..0000000
--- a/configs/M52277EVB_stmicro_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x43E00000
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x30000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro"
-CONFIG_TARGET_M52277EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=2
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
deleted file mode 100644
index 6aa4c2f..0000000
--- a/configs/M54418TWR_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x40000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
deleted file mode 100644
index 7273ee0..0000000
--- a/configs/M54418TWR_nand_mii_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
deleted file mode 100644
index 90df8f4..0000000
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
deleted file mode 100644
index d7b0f2d..0000000
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
deleted file mode 100644
index 556bbef..0000000
--- a/configs/M54418TWR_serial_mii_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x40000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_mii"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
deleted file mode 100644
index 19b1aa6..0000000
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x40000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
deleted file mode 100644
index a3583e5..0000000
--- a/configs/M54451EVB_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54451EVB"
-CONFIG_TARGET_M54451EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
deleted file mode 100644
index 5f5e6a5..0000000
--- a/configs/M54451EVB_stmicro_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x20000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro"
-CONFIG_TARGET_M54451EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig
deleted file mode 100644
index 50bdb2c..0000000
--- a/configs/M54455EVB_a66_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x4000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_a66"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x4040000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
deleted file mode 100644
index 40d025f..0000000
--- a/configs/M54455EVB_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x4000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x4040000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig
deleted file mode 100644
index 97d5d15..0000000
--- a/configs/M54455EVB_i66_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_i66"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig
deleted file mode 100644
index d82f091..0000000
--- a/configs/M54455EVB_intel_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_intel"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
deleted file mode 100644
index 147d87e..0000000
--- a/configs/M54455EVB_stm33_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x4FE00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x30000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_stm33"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 498174a..a0baeec 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -16,7 +16,7 @@
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 79fb8b3..a33efff 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -9,7 +9,7 @@
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 9eb4ae1..8f0c330 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -14,7 +14,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 7eafb6d..8ae5c67 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
+# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x500000
CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian"
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x81000000
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_GUARDIAN=y
CONFIG_SPL_SERIAL_SUPPORT=y
@@ -17,6 +19,7 @@
CONFIG_ENV_OFFSET_REDUND=0x540000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
@@ -39,10 +42,12 @@
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
-CONFIG_CMD_SPL=y
+# CONFIG_CMD_SPL is not set
CONFIG_CMD_SPL_NAND_OFS=0x0
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -50,8 +55,7 @@
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_DNS2=y
-# CONFIG_CMD_LED is not set
+CONFIG_CMD_BMP=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),1m(u-boot-2),1m(u-boot-2.backup1),256k(u-boot-env),256k(u-boot-env.backup1),256k(splash-screen),-(UBI)"
@@ -68,7 +72,16 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_AM33XX_NVMEM=y
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_AM3_DPLL=y
+CONFIG_CLK_TI_CTRL=y
+CONFIG_CLK_TI_DIVIDER=y
+CONFIG_CLK_TI_GATE=y
+CONFIG_CLK_TI_MUX=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
@@ -80,12 +93,16 @@
CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x200000
CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
@@ -98,6 +115,11 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
+CONFIG_DM_VIDEO=y
+CONFIG_DM_PANEL_HX8238D=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_AM335X_LCD=y
CONFIG_SPL_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 3d678fa..83815e1 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -13,7 +13,7 @@
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index 21ef7d6..9c5ac03 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -16,7 +16,7 @@
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index d9e089e..6618563 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -10,7 +10,7 @@
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_AM3517_EVM=y
CONFIG_EMIF4=y
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x3000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2500
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
@@ -53,8 +53,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_PCA953X=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
@@ -84,3 +82,4 @@
CONFIG_USB_MUSB_AM35X=y
CONFIG_BCH=y
CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index b73fb92..05e7e77 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -12,7 +12,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_ETH_SUPPORT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 546669f..3520502 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -13,7 +13,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI,QSPI_BOOT"
CONFIG_QSPI_BOOT=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index ed5ce0f..c8db636 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -12,7 +12,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index b1be027..ae23343 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -11,7 +11,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 0f48729..f568aa6 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -21,7 +21,7 @@
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_ETH_SUPPORT=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index ba3f9ad..6fab1de 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -5,7 +5,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM642=y
-CONFIG_K3_ATF_LOAD_ADDR=0x701a0000
+CONFIG_K3_ATF_LOAD_ADDR=0x701c0000
CONFIG_TARGET_AM642_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 6f9309e..a5858fe 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -29,7 +29,7 @@
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
@@ -141,12 +141,14 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_REMOTEPROC_TI_PRU=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
+CONFIG_TI_PRUSS=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index c0354bc..2034cd1 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -57,5 +57,6 @@
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 5ee0449..5d9a6aa 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index ee4e6cc..36d96e5 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -91,6 +91,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index a163f42..48f0c03 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -52,6 +52,7 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index b449bdb..862061e 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -114,6 +114,13 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65941=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_TPS65941=y
+CONFIG_K3_AVS0=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 365d662..2e890cd 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -29,7 +29,7 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 2798d56..44cba29 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -76,6 +76,7 @@
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 6745da1..2392aec 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -76,6 +76,7 @@
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index f23bdbf..021129b 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -76,6 +76,7 @@
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 061f5c3..981e6f9 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -18,6 +18,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Nokia RX-51 # "
# CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 084c1ee..896fc87 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -5,7 +5,7 @@
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index 7f06249..61b8cad 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -5,7 +5,7 @@
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 2371fff..1a7421b 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -5,7 +5,7 @@
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 19b9ff8..fa1bdbe 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -5,7 +5,7 @@
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 08dc355..9e99e8b 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -39,7 +39,6 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_USB_GADGET=y
CONFIG_USB_HOST_ETHER=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index f90b281..fd93dc5 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -39,7 +39,6 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 7de4cdb..44e9dc7 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 5448386..5401892 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index fa5250e..91da734 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index b64f7bb..c52e7cb 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -31,7 +31,6 @@
CONFIG_TWL4030_INPUT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
-CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index cdf8630..1631b4f 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -73,5 +73,6 @@
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_PCI=y
CONFIG_USB_STORAGE=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 67e1e68..c9a99ca 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index be7aaa9..434d90c 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -33,13 +33,14 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_AT91_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_PHY_SMSC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="L+G VInCo"
diff --git a/doc/README.m54418twr b/doc/README.m54418twr
deleted file mode 100644
index 0ca74aa..0000000
--- a/doc/README.m54418twr
+++ /dev/null
@@ -1,245 +0,0 @@
-Freescale MCF54418TWR ColdFire Development Board
-================================================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created Mar 22, 2012
-===========================================
-
-
-Changed files:
-==============
-
-- board/freescale/m54418twr/m54418twr.c Dram setup
-- board/freescale/m54418twr/Makefile Makefile
-- board/freescale/m54418twr/config.mk config make
-- board/freescale/m54418twr/u-boot.lds Linker description
-- board/freescale/m54418twr/sbf_dram_init.S
- DDR/SDRAM initialization
-
-- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
-- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
-- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
-- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
-- arch/m68k/cpu/mcf5445x/Makefile Makefile
-- arch/m68k/cpu/mcf5445x/config.mk config make
-- arch/m68k/cpu/mcf5445x/start.S start up assembly code
-
-- doc/README.m54418twr This readme file
-
-- drivers/net/mcffec.c ColdFire common FEC driver
-- drivers/net/mcfmii.c ColdFire common MII driver
-- drivers/serial/mcfuart.c ColdFire common UART driver
-
-- arch/m68k/include/asm/bitops.h Bit operation function export
-- arch/m68k/include/asm/byteorder.h Byte order functions
-- arch/m68k/include/asm/fec.h FEC structure and definition
-- arch/m68k/include/asm/global_data.h Global data structure
-- arch/m68k/include/asm/immap.h ColdFire specific header file and driver macros
-- arch/m68k/include/asm/immap_5441x.h mcf5441x specific header file
-- arch/m68k/include/asm/io.h io functions
-- arch/m68k/include/asm/m5441x.h mcf5441x specific header file
-- arch/m68k/include/asm/posix_types.h Posix
-- arch/m68k/include/asm/processor.h header file
-- arch/m68k/include/asm/ptrace.h Exception structure
-- arch/m68k/include/asm/rtc.h Realtime clock header file
-- arch/m68k/include/asm/string.h String function export
-- arch/m68k/include/asm/timer.h Timer structure and definition
-- arch/m68k/include/asm/types.h Data types definition
-- arch/m68k/include/asm/uart.h Uart structure and definition
-- arch/m68k/include/asm/u-boot.h u-boot structure
-
-- include/configs/M54418TWR.h Board specific configuration file
-
-- arch/m68k/lib/board.c board init function
-- arch/m68k/lib/cache.c
-- arch/m68k/lib/interrupts.c Coldfire common interrupt functions
-- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
-- arch/m68k/lib/traps.c Exception init code
-
-1 MCF5441x specific Options/Settings
-====================================
-1.1 pre-loader is no longer suppoer in thie coldfire family
-
-1.2 Configuration settings for M54418TWR Development Board
-CONFIG_MCF5441x -- define for all MCF5441x CPUs
-CONFIG_M54418 -- define for all Freescale MCF54418 CPUs
-
-CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
-CONFIG_BAUDRATE -- define UART baudrate
-
-CONFIG_MCFFEC -- define to use common CF FEC driver
-CONFIG_MII -- enable to use MII driver
-CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
-CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
-CONFIG_SYS_FAULT_ECHO_LINK_DOWN --
-CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
-CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
-CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
-CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
-MCFFEC_TOUT_LOOP -- set FEC timeout loop
-CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
-
-CONFIG_MCFTMR -- define to use DMA timer
-
-CONFIG_SYS_IMMR -- define for MBAR offset
-
-CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
-
-CONFIG_SYS_MBAR -- define MBAR offset
-
-CONFIG_MONITOR_IS_IN_RAM -- Not support
-
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
-
-CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
-CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
-CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. System memory map:
- MRAM: 0x00000000-0x0003FFFF (256KB)
- DDR: 0x40000000-0x47FFFFFF (128MB)
- SRAM: 0x80000000-0x8000FFFF (64KB)
- IP: 0xE0000000-0xFFFFFFFF (512MB)
-
-3. COMPILATION
-==============
-3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF version)
-from codesourcery.com was used. Download it from:
-http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
-
-3.2 Compilation
- export CROSS_COMPILE=cross-compile-prefix
- cd u-boot
- make distclean
- make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
- make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
- make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
- make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
- make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
- make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
- make
-
-4. SCREEN DUMP
-==============
-4.1 M54418TWR Development board
- Boot from NAND flash (NOTE: May not show exactly the same)
-
-U-Boot 2012.10-00209-g12ae1d8-dirty (Oct 18 2012 - 15:54:54)
-
-CPU: Freescale MCF54418 (Mask:a3 Version:1)
- CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
- INP CLK 50 MHz VCO CLK 500 MHz
-Board: Freescale MCF54418 Tower System
-SPI: ready
-DRAM: 128 MiB
-NAND: 256 MiB
-In: serial
-Out: serial
-Err: serial
-Net: FEC0, FEC1
--> pri
-baudrate=115200
-bootargs=root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(k
-ernel)ro,-(jffs2) console=ttyS0,115200
-bootdelay=2
-eth1addr=00:e0:0c:bc:e5:61
-ethact=FEC0
-ethaddr=00:e0:0c:bc:e5:60
-fileaddr=40010000
-filesize=27354
-gatewayip=192.168.1.1
-hostname=M54418TWR
-inpclk=50000000
-ipaddr=192.168.1.2
-load=tftp ${loadaddr} ${u-boot};
-loadaddr=0x40010000
-mem=129024k
-netdev=eth0
-netmask=255.255.255.0
-prog=nand device 0;nand erase 0 40000;nb_update ${loadaddr} ${filesize};save
-serverip=192.168.1.1
-stderr=serial
-stdin=serial
-stdout=serial
-u-boot=u-boot.bin
-upd=run load; run prog
-
-Environment size: 653/131068 bytes
--> bdinfo
-memstart = 0x40000000
-memsize = 0x08000000
-flashstart = 0x00000000
-flashsize = 0x00000000
-flashoffset = 0x00000000
-sramstart = 0x80000000
-sramsize = 0x00010000
-mbar = 0xFC000000
-cpufreq = 250 MHz
-busfreq = 125 MHz
-flbfreq = 125 MHz
-inpfreq = 50 MHz
-vcofreq = 500 MHz
-ethaddr = 00:e0:0c:bc:e5:60
-eth1addr = 00:e0:0c:bc:e5:61
-ip_addr = 192.168.1.2
-baudrate = 115200 bps
--> help
-? - alias for 'help'
-base - print or set address offset
-bdinfo - print Board Info structure
-boot - boot default, i.e., run 'bootcmd'
-bootd - boot default, i.e., run 'bootcmd'
-bootelf - Boot from an ELF image in memory
-bootm - boot application image from memory
-bootp - boot image via network using BOOTP/TFTP protocol
-bootvx - Boot vxWorks from an ELF image
-cmp - memory compare
-coninfo - print console devices and information
-cp - memory copy
-crc32 - checksum calculation
-dcache - enable or disable data cache
-dhcp - boot image via network using DHCP/TFTP protocol
-echo - echo args to console
-editenv - edit environment variable
-env - environment handling commands
-exit - exit script
-false - do nothing, unsuccessfully
-go - start application at address 'addr'
-help - print command description/usage
-icache - enable or disable instruction cache
-iminfo - print header information for application image
-imxtract- extract a part of a multi-image
-itest - return true/false on integer compare
-loop - infinite loop on address range
-md - memory display
-mdio - MDIO utility commands
-mii - MII utility commands
-mm - memory modify (auto-incrementing address)
-mtest - simple RAM read/write test
-mw - memory write (fill)
-nand - NAND sub-system
-nb_update- Nand boot update program
-nboot - boot from NAND device
-nfs - boot image via network using NFS protocol
-nm - memory modify (constant address)
-ping - send ICMP ECHO_REQUEST to network host
-printenv- print environment variables
-reginfo - print register information
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sf - SPI flash sub-system
-showvar - print local hushshell variables
-sleep - delay execution for some time
-source - run script from memory
-sspi - SPI utility command
-test - minimal test like /bin/sh
-tftpboot- boot image via network using TFTP protocol
-true - do nothing, successfully
-version - print monitor, compiler and linker version
diff --git a/doc/README.nokia_rx51 b/doc/README.nokia_rx51
index 84d1912..7f22ed4 100644
--- a/doc/README.nokia_rx51
+++ b/doc/README.nokia_rx51
@@ -11,13 +11,14 @@
appended to u-boot.bin at 0x40000. NOLO will load the entire image into
(random) memory and execute u-boot, which saves hw revision, boot reason
and boot mode ATAGs set by NOLO. Then the bootscripts will attempt to load
-uImage or boot.scr from a fat, ext2/ext3 or ext4 filesystem in external
+uImage, zImage or boot.scr from a fat or ext2/3/4 filesystem on external
SD card or internal eMMC memory. If this fails or keyboard is closed then
the appended kernel image will be booted using some generated and some
stored ATAGs (see boot order).
-For generating combined image of u-boot and kernel there is a simple script
-called u-boot-gen-combined. It is available in following repository:
+For generating combined image of u-boot and kernel (either in uImage or zImage
+format) there is a simple script called u-boot-gen-combined. It is available in
+following repository:
https://github.com/pali/u-boot-maemo
@@ -41,7 +42,8 @@
* 1.
* 1.1 find boot.scr on first fat partition
* 1.2 find uImage on first fat partition
- * 1.3 same order for 2. - 4. fat partition
+ * 1.3 find zImage on first fat partition
+ * 1.4 same order for 2. - 4. fat partition
* 2. same as 1. but for ext2/3 partition
* 3. same as 1. but for ext4 partition
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 1e6dad8..4023332 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -1,7 +1,7 @@
config BLK
bool "Support block devices"
depends on DM
- default y if DM_MMC
+ default y if DM_MMC || DM_USB
help
Enable support for block devices, such as SCSI, MMC and USB
flash sticks. These provide a block-level interface which permits
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index b5ccea0..0de2b7b 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -42,6 +42,25 @@
This requires the RTC clocks, etc, to be enabled prior to use and
not all boards with this IP block on it will have the RTC in use.
+config BOOTCOUNT_AM33XX_NVMEM
+ bool "Boot counter in AM33XX RTC IP block with upgrade_available flag"
+ depends on AM33XX
+ select SPL_AM33XX_ENABLE_RTC32K_OSC if AM33XX
+ help
+ Add support for maintaining bootcount,upgrade_available,
+ version and BOOTMAGIC in a AM33xx RTC IP block
+ scratch register2.
+
+ A bootcount driver for the RTC IP block found on many TI platforms.
+ This requires the RTC clocks, etc, to be enabled prior to use and
+ not all boards with this IP block on it will have the RTC in use.
+
+ If there is upgrade in software then "upgrade_available" is 1,
+ "bootcount" is incremented otherwise "upgrade_available" and
+ "bootcount" is always 0. So the Userspace Application must set
+ the "upgrade_available" and "bootcount" variable to 0, if a boot
+ was successfully.
+
config BOOTCOUNT_ENV
bool "Boot counter in environment"
help
@@ -177,16 +196,25 @@
config SYS_BOOTCOUNT_ADDR
hex "RAM address used for reading and writing the boot counter"
- default 0x44E3E000 if BOOTCOUNT_AM33XX
+ default 0x44E3E000 if BOOTCOUNT_AM33XX || BOOTCOUNT_AM33XX_NVMEM
default 0xE0115FF8 if ARCH_LS1043A || ARCH_LS1021A
depends on BOOTCOUNT_AM33XX || BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
- BOOTCOUNT_I2C
+ BOOTCOUNT_I2C || BOOTCOUNT_AM33XX_NVMEM
help
Set the address used for reading and writing the boot counter.
config SYS_BOOTCOUNT_MAGIC
hex "Magic value for the boot counter"
- default 0xB001C041
+ default 0xB001C041 if BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
+ BOOTCOUNT_AM33XX || BOOTCOUNT_ENV || \
+ BOOTCOUNT_RAM || BOOTCOUNT_I2C || \
+ BOOTCOUNT_AT91 || DM_BOOTCOUNT
+ default 0xB0 if BOOTCOUNT_AM33XX_NVMEM
+ depends on BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
+ BOOTCOUNT_AM33XX || BOOTCOUNT_ENV || \
+ BOOTCOUNT_RAM || BOOTCOUNT_I2C || \
+ BOOTCOUNT_AT91 || DM_BOOTCOUNT || \
+ BOOTCOUNT_AM33XX_NVMEM
help
Set the magic value used for the boot counter.
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 51d860b..12658ff 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o
obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o
obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o
+obj-$(CONFIG_BOOTCOUNT_AM33XX_NVMEM) += bootcount_nvmem.o
obj-$(CONFIG_DM_BOOTCOUNT) += bootcount-uclass.o
obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o
diff --git a/drivers/bootcount/bootcount_nvmem.c b/drivers/bootcount/bootcount_nvmem.c
new file mode 100644
index 0000000..5f266d5
--- /dev/null
+++ b/drivers/bootcount/bootcount_nvmem.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ * (C) Copyright 2018 Robert Bosch Power Tools GmbH.
+ *
+ * A bootcount driver for the RTC IP block found on many TI platforms.
+ * This requires the RTC clocks, etc, to be enabled prior to use and
+ * not all boards with this IP block on it will have the RTC in use.
+ */
+
+#include <bootcount.h>
+#include <asm/davinci_rtc.h>
+
+#define BC_VERSION 2
+
+void bootcount_store(ulong bootcount)
+{
+ u8 upgrade_available = 0;
+ ulong val = 0;
+ struct davinci_rtc *reg =
+ (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ val = raw_bootcount_load(®->scratch2);
+ upgrade_available = (val >> 8) & 0x000000ff;
+
+ /* Only update bootcount during upgrade process */
+ if (!upgrade_available)
+ bootcount = 0;
+
+ val = (bootcount & 0x000000ff) |
+ (upgrade_available << 8) |
+ (BC_VERSION << 16) |
+ (CONFIG_SYS_BOOTCOUNT_MAGIC << 24);
+
+ /*
+ * write RTC kick registers to enable write
+ * for RTC Scratch registers. Scratch register 2 is
+ * used for bootcount value.
+ */
+ writel(RTC_KICK0R_WE, ®->kick0r);
+ writel(RTC_KICK1R_WE, ®->kick1r);
+ raw_bootcount_store(®->scratch2, val);
+}
+
+ulong bootcount_load(void)
+{
+ unsigned long val = 0;
+ struct davinci_rtc *reg =
+ (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ val = raw_bootcount_load(®->scratch2);
+ if ((val >> 24) != CONFIG_SYS_BOOTCOUNT_MAGIC)
+ return 0;
+ else
+ return val & 0x000000ff;
+}
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 43bb761..cef9eec 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -105,17 +105,11 @@
}
if ((dup_spd & 0xFFFF) == _100BASET) {
-#ifdef CONFIG_MCF5445x
- fecp->rcr &= ~0x200; /* disabled 10T base */
-#endif
#ifdef MII_DEBUG
printf("100Mbps\n");
#endif
bd->bi_ethspeed = 100;
} else {
-#ifdef CONFIG_MCF5445x
- fecp->rcr |= 0x200; /* enabled 10T base */
-#endif
#ifdef MII_DEBUG
printf("10Mbps\n");
#endif
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index c49cb6e..2ef4d46 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -1,22 +1,23 @@
menuconfig PCI
bool "PCI support"
+ depends on DM
default y if PPC
+ select DM_PCI
help
Enable support for PCI (Peripheral Interconnect Bus), a type of bus
used on some devices to allow the CPU to communicate with its
peripherals.
-if PCI
-
config DM_PCI
- bool "Enable driver model for PCI"
- depends on DM
+ bool
help
Use driver model for PCI. Driver model is the new method for
orgnising devices in U-Boot. For PCI, driver model keeps track of
available PCI devices, allows scanning of PCI buses and provides
device configuration support.
+if PCI
+
config DM_PCI_COMPAT
bool "Enable compatible functions for PCI"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index ec8ee9d..83d7a4e 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -3,16 +3,12 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_DM_VIDEO) += pci_rom.o
obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
obj-$(CONFIG_X86) += pci_x86.o pci_rom.o
-else
-obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
-endif
obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
deleted file mode 100644
index d8f9239..0000000
--- a/drivers/pci/pci.c
+++ /dev/null
@@ -1,588 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- *
- * (C) Copyright 2002, 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * Old PCI routines
- *
- * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
- * and change pci-uclass.c.
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <command.h>
-#include <env.h>
-#include <errno.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PCI_HOSE_OP(rw, size, type) \
-int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, \
- int offset, type value) \
-{ \
- return hose->rw##_##size(hose, dev, offset, value); \
-}
-
-PCI_HOSE_OP(read, byte, u8 *)
-PCI_HOSE_OP(read, word, u16 *)
-PCI_HOSE_OP(read, dword, u32 *)
-PCI_HOSE_OP(write, byte, u8)
-PCI_HOSE_OP(write, word, u16)
-PCI_HOSE_OP(write, dword, u32)
-
-#define PCI_OP(rw, size, type, error_code) \
-int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
-{ \
- struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
- \
- if (!hose) \
- { \
- error_code; \
- return -1; \
- } \
- \
- return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
-}
-
-PCI_OP(read, byte, u8 *, *value = 0xff)
-PCI_OP(read, word, u16 *, *value = 0xffff)
-PCI_OP(read, dword, u32 *, *value = 0xffffffff)
-PCI_OP(write, byte, u8, )
-PCI_OP(write, word, u16, )
-PCI_OP(write, dword, u32, )
-
-#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
-int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
- pci_dev_t dev, \
- int offset, type val) \
-{ \
- u32 val32; \
- \
- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
- *val = -1; \
- return -1; \
- } \
- \
- *val = (val32 >> ((offset & (int)off_mask) * 8)); \
- \
- return 0; \
-}
-
-#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
-int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
- pci_dev_t dev, \
- int offset, type val) \
-{ \
- u32 val32, mask, ldata, shift; \
- \
- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
- return -1; \
- \
- shift = ((offset & (int)off_mask) * 8); \
- ldata = (((unsigned long)val) & val_mask) << shift; \
- mask = val_mask << shift; \
- val32 = (val32 & ~mask) | ldata; \
- \
- if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
- return -1; \
- \
- return 0; \
-}
-
-PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
-PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
-PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
-PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
-
-/*
- *
- */
-
-static struct pci_controller* hose_head;
-
-struct pci_controller *pci_get_hose_head(void)
-{
- if (gd->hose)
- return gd->hose;
-
- return hose_head;
-}
-
-void pci_register_hose(struct pci_controller* hose)
-{
- struct pci_controller **phose = &hose_head;
-
- while(*phose)
- phose = &(*phose)->next;
-
- hose->next = NULL;
-
- *phose = hose;
-}
-
-struct pci_controller *pci_bus_to_hose(int bus)
-{
- struct pci_controller *hose;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- if (bus >= hose->first_busno && bus <= hose->last_busno)
- return hose;
- }
-
- printf("pci_bus_to_hose() failed\n");
- return NULL;
-}
-
-struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
-{
- struct pci_controller *hose;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- if (hose->cfg_addr == cfg_addr)
- return hose;
- }
-
- return NULL;
-}
-
-int pci_last_busno(void)
-{
- struct pci_controller *hose = pci_get_hose_head();
-
- if (!hose)
- return -1;
-
- while (hose->next)
- hose = hose->next;
-
- return hose->last_busno;
-}
-
-pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
-{
- struct pci_controller * hose;
- pci_dev_t bdf;
- int bus;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
- bdf = pci_hose_find_devices(hose, bus, ids, &index);
- if (bdf != -1)
- return bdf;
- }
- }
-
- return -1;
-}
-
-static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
- ulong io, pci_addr_t mem, ulong command)
-{
- u32 bar_response;
- unsigned int old_command;
- pci_addr_t bar_value;
- pci_size_t bar_size;
- unsigned char pin;
- int bar, found_mem64;
-
- debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
- (u64)mem, command);
-
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
-
- for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
- pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar, &bar_response);
-
- if (!bar_response)
- continue;
-
- found_mem64 = 0;
-
- /* Check the BAR type and set our address mask */
- if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
- /* round up region base address to a multiple of size */
- io = ((io - 1) | (bar_size - 1)) + 1;
- bar_value = io;
- /* compute new region base address */
- io = io + bar_size;
- } else {
- if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64) {
- u32 bar_response_upper;
- u64 bar64;
- pci_hose_write_config_dword(hose, dev, bar + 4,
- 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar + 4,
- &bar_response_upper);
-
- bar64 = ((u64)bar_response_upper << 32) | bar_response;
-
- bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
- found_mem64 = 1;
- } else {
- bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
- }
-
- /* round up region base address to multiple of size */
- mem = ((mem - 1) | (bar_size - 1)) + 1;
- bar_value = mem;
- /* compute new region base address */
- mem = mem + bar_size;
- }
-
- /* Write it out and update our limit */
- pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
-
- if (found_mem64) {
- bar += 4;
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar,
- (u32)(bar_value >> 32));
-#else
- pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
-#endif
- }
- }
-
- /* Configure Cache Line Size Register */
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /* Configure Latency Timer */
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-
- /* Disable interrupt line, if device says it wants to use interrupts */
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
- if (pin != 0) {
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- PCI_INTERRUPT_LINE_DISABLE);
- }
-
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
- (old_command & 0xffff0000) | command);
-
- return 0;
-}
-
-/*
- *
- */
-
-struct pci_config_table *pci_find_config(struct pci_controller *hose,
- unsigned short class,
- unsigned int vendor,
- unsigned int device,
- unsigned int bus,
- unsigned int dev,
- unsigned int func)
-{
- struct pci_config_table *table;
-
- for (table = hose->config_table; table && table->vendor; table++) {
- if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
- (table->device == PCI_ANY_ID || table->device == device) &&
- (table->class == PCI_ANY_ID || table->class == class) &&
- (table->bus == PCI_ANY_ID || table->bus == bus) &&
- (table->dev == PCI_ANY_ID || table->dev == dev) &&
- (table->func == PCI_ANY_ID || table->func == func)) {
- return table;
- }
- }
-
- return NULL;
-}
-
-void pci_cfgfunc_config_device(struct pci_controller *hose,
- pci_dev_t dev,
- struct pci_config_table *entry)
-{
- pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
- entry->priv[2]);
-}
-
-void pci_cfgfunc_do_nothing(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
-}
-
-/*
- * HJF: Changed this to return int. I think this is required
- * to get the correct result when scanning bridges
- */
-extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
-{
- if (dev == PCI_BDF(hose->first_busno, 0, 0))
- return 0;
-
- return 1;
-}
-#endif /* CONFIG_PCI_SCAN_SHOW */
-
-int pci_hose_scan_bus(struct pci_controller *hose, int bus)
-{
- unsigned int sub_bus, found_multi = 0;
- unsigned short vendor, device, class;
- unsigned char header_type;
-#ifndef CONFIG_PCI_PNP
- struct pci_config_table *cfg;
-#endif
- pci_dev_t dev;
-#ifdef CONFIG_PCI_SCAN_SHOW
- static int indent = 0;
-#endif
-
- sub_bus = bus;
-
- for (dev = PCI_BDF(bus,0,0);
- dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
- PCI_MAX_PCI_FUNCTIONS - 1);
- dev += PCI_BDF(0, 0, 1)) {
-
- if (pci_skip_dev(hose, dev))
- continue;
-
- if (PCI_FUNC(dev) && !found_multi)
- continue;
-
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
-
- pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
-
- if (vendor == 0xffff || vendor == 0x0000)
- continue;
-
- if (!PCI_FUNC(dev))
- found_multi = header_type & 0x80;
-
- debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
-
- pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
-
-#ifdef CONFIG_PCI_FIXUP_DEV
- board_pci_fixup_dev(hose, dev, vendor, device, class);
-#endif
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- indent++;
-
- /* Print leading space, including bus indentation */
- printf("%*c", indent + 1, ' ');
-
- if (pci_print_dev(hose, dev)) {
- printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
- PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
- vendor, device, pci_class_str(class >> 8));
- }
-#endif
-
-#ifdef CONFIG_PCI_PNP
- sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
- sub_bus);
-#else
- cfg = pci_find_config(hose, class, vendor, device,
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
- if (cfg) {
- cfg->config_device(hose, dev, cfg);
- sub_bus = max(sub_bus,
- (unsigned int)hose->current_busno);
- }
-#endif
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- indent--;
-#endif
-
- if (hose->fixup_irq)
- hose->fixup_irq(hose, dev);
- }
-
- return sub_bus;
-}
-
-int pci_hose_scan(struct pci_controller *hose)
-{
-#if defined(CONFIG_PCI_BOOTDELAY)
- char *s;
- int i;
-
- if (!gd->pcidelay_done) {
- /* wait "pcidelay" ms (if defined)... */
- s = env_get("pcidelay");
- if (s) {
- int val = simple_strtoul(s, NULL, 10);
- for (i = 0; i < val; i++)
- udelay(1000);
- }
- gd->pcidelay_done = 1;
- }
-#endif /* CONFIG_PCI_BOOTDELAY */
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- puts("PCI:\n");
-#endif
-
- /*
- * Start scan at current_busno.
- * PCIe will start scan at first_busno+1.
- */
- /* For legacy support, ensure current >= first */
- if (hose->first_busno > hose->current_busno)
- hose->current_busno = hose->first_busno;
-#ifdef CONFIG_PCI_PNP
- pciauto_config_init(hose);
-#endif
- return pci_hose_scan_bus(hose, hose->current_busno);
-}
-
-int pci_init(void)
-{
- hose_head = NULL;
-
- /* allow env to disable pci init/enum */
- if (env_get("pcidisable") != NULL)
- return 0;
-
- /* now call board specific pci_init()... */
- pci_init_board();
-
- return 0;
-}
-
-/* Returns the address of the requested capability structure within the
- * device's PCI configuration space or 0 in case the device does not
- * support it.
- * */
-int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
- int cap)
-{
- int pos;
- u8 hdr_type;
-
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
-
- pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
-
- if (pos)
- pos = pci_find_cap(hose, dev, pos, cap);
-
- return pos;
-}
-
-/* Find the header pointer to the Capabilities*/
-int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
- u8 hdr_type)
-{
- u16 status;
-
- pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
-
- if (!(status & PCI_STATUS_CAP_LIST))
- return 0;
-
- switch (hdr_type) {
- case PCI_HEADER_TYPE_NORMAL:
- case PCI_HEADER_TYPE_BRIDGE:
- return PCI_CAPABILITY_LIST;
- case PCI_HEADER_TYPE_CARDBUS:
- return PCI_CB_CAPABILITY_LIST;
- default:
- return 0;
- }
-}
-
-int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
-{
- int ttl = PCI_FIND_CAP_TTL;
- u8 id;
- u8 next_pos;
-
- while (ttl--) {
- pci_hose_read_config_byte(hose, dev, pos, &next_pos);
- if (next_pos < CAP_START_POS)
- break;
- next_pos &= ~3;
- pos = (int) next_pos;
- pci_hose_read_config_byte(hose, dev,
- pos + PCI_CAP_LIST_ID, &id);
- if (id == 0xff)
- break;
- if (id == cap)
- return pos;
- pos += PCI_CAP_LIST_NEXT;
- }
- return 0;
-}
-
-/**
- * pci_find_next_ext_capability - Find an extended capability
- *
- * Returns the address of the next matching extended capability structure
- * within the device's PCI configuration space or 0 if the device does
- * not support it. Some capabilities can occur several times, e.g., the
- * vendor-specific capability, and this provides a way to find them all.
- */
-int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
- int start, int cap)
-{
- u32 header;
- int ttl, pos = PCI_CFG_SPACE_SIZE;
-
- /* minimum 8 bytes per capability */
- ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
- if (start)
- pos = start;
-
- pci_hose_read_config_dword(hose, dev, pos, &header);
- if (header == 0xffffffff || header == 0)
- return 0;
-
- while (ttl-- > 0) {
- if (PCI_EXT_CAP_ID(header) == cap && pos != start)
- return pos;
-
- pos = PCI_EXT_CAP_NEXT(header);
- if (pos < PCI_CFG_SPACE_SIZE)
- break;
-
- pci_hose_read_config_dword(hose, dev, pos, &header);
- if (header == 0xffffffff || header == 0)
- break;
- }
-
- return 0;
-}
-
-/**
- * pci_hose_find_ext_capability - Find an extended capability
- *
- * Returns the address of the requested extended capability structure
- * within the device's PCI configuration space or 0 if the device does
- * not support it.
- */
-int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
- int cap)
-{
- return pci_find_next_ext_capability(hose, dev, 0, cap);
-}
diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
deleted file mode 100644
index c56ff53..0000000
--- a/drivers/pci/pci_auto_old.c
+++ /dev/null
@@ -1,387 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PCI autoconfiguration library (legacy version, do not change)
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * Copyright 2000 MontaVista Software Inc.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <log.h>
-#include <pci.h>
-
-/*
- * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
- * and change pci_auto.c.
- */
-
-/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
-#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
-#endif
-
-/*
- *
- */
-
-void pciauto_setup_device(struct pci_controller *hose,
- pci_dev_t dev, int bars_num,
- struct pci_region *mem,
- struct pci_region *prefetch,
- struct pci_region *io)
-{
- u32 bar_response;
- pci_size_t bar_size;
- u16 cmdstat = 0;
- int bar, bar_nr = 0;
- u8 header_type;
- int rom_addr;
- pci_addr_t bar_value;
- struct pci_region *bar_res;
- int found_mem64 = 0;
- u16 class;
-
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
-
- for (bar = PCI_BASE_ADDRESS_0;
- bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
- /* Tickle the BAR and get the response */
- pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar, &bar_response);
-
- /* If BAR is not implemented go to the next BAR */
- if (!bar_response)
- continue;
-
- found_mem64 = 0;
-
- /* Check the BAR type and set our address mask */
- if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
- & 0xffff) + 1;
- bar_res = io;
-
- debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
- bar_nr, (unsigned long long)bar_size);
- } else {
- if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64) {
- u32 bar_response_upper;
- u64 bar64;
-
- pci_hose_write_config_dword(hose, dev, bar + 4,
- 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar + 4,
- &bar_response_upper);
-
- bar64 = ((u64)bar_response_upper << 32) | bar_response;
-
- bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
- found_mem64 = 1;
- } else {
- bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
- }
- if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
- bar_res = prefetch;
- else
- bar_res = mem;
-
- debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
- bar_nr, bar_res == prefetch ? "Prf" : "Mem",
- (unsigned long long)bar_size);
- }
-
- if (pciauto_region_allocate(bar_res, bar_size,
- &bar_value, found_mem64) == 0) {
- /* Write it out and update our limit */
- pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
-
- if (found_mem64) {
- bar += 4;
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
-#else
- /*
- * If we are a 64-bit decoder then increment to the
- * upper 32 bits of the bar and force it to locate
- * in the lower 4GB of memory.
- */
- pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
-#endif
- }
-
- }
- cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
- PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
-
- debug("\n");
-
- bar_nr++;
- }
-
- /* Configure the expansion ROM address */
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
- header_type &= 0x7f;
- if (header_type != PCI_HEADER_TYPE_CARDBUS) {
- rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
- PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
- pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
- pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
- if (bar_response) {
- bar_size = -(bar_response & ~1);
- debug("PCI Autoconfig: ROM, size=%#x, ",
- (unsigned int)bar_size);
- if (pciauto_region_allocate(mem, bar_size,
- &bar_value, false) == 0) {
- pci_hose_write_config_dword(hose, dev, rom_addr,
- bar_value);
- }
- cmdstat |= PCI_COMMAND_MEMORY;
- debug("\n");
- }
- }
-
- /* PCI_COMMAND_IO must be set for VGA device */
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
- if (class == PCI_CLASS_DISPLAY_VGA)
- cmdstat |= PCI_COMMAND_IO;
-
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
- CONFIG_SYS_PCI_CACHE_LINE_SIZE);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-}
-
-void pciauto_prescan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
- u16 cmdstat, prefechable_64;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
- pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
- &prefechable_64);
- prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
-
- /* Configure bus number registers */
- pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
- PCI_BUS(dev) - hose->first_busno);
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
- sub_bus - hose->first_busno);
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
-
- if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
-
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
- (pci_mem->bus_lower & 0xfff00000) >> 16);
-
- cmdstat |= PCI_COMMAND_MEMORY;
- }
-
- if (pci_prefetch) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
-
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
- (pci_prefetch->bus_lower & 0xfff00000) >> 16);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_BASE_UPPER32,
- pci_prefetch->bus_lower >> 32);
-#else
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_BASE_UPPER32,
- 0x0);
-#endif
-
- cmdstat |= PCI_COMMAND_MEMORY;
- } else {
- /* We don't support prefetchable memory for now, so disable */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
- pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
- pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
- }
- }
-
- if (pci_io) {
- /* Round I/O allocator to 4KB boundary */
- pciauto_region_align(pci_io, 0x1000);
-
- pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
- (pci_io->bus_lower & 0x0000f000) >> 8);
- pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
- (pci_io->bus_lower & 0xffff0000) >> 16);
-
- cmdstat |= PCI_COMMAND_IO;
- }
-
- /* Enable memory and I/O accesses, enable bus master */
- pci_hose_write_config_word(hose, dev, PCI_COMMAND,
- cmdstat | PCI_COMMAND_MASTER);
-}
-
-void pciauto_postscan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- /* Configure bus number registers */
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
- sub_bus - hose->first_busno);
-
- if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
-
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower - 1) >> 16);
- }
-
- if (pci_prefetch) {
- u16 prefechable_64;
-
- pci_hose_read_config_word(hose, dev,
- PCI_PREF_MEMORY_LIMIT,
- &prefechable_64);
- prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
-
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
-
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower - 1) >> 16);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_LIMIT_UPPER32,
- (pci_prefetch->bus_lower - 1) >> 32);
-#else
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_LIMIT_UPPER32,
- 0x0);
-#endif
- }
-
- if (pci_io) {
- /* Round I/O allocator to 4KB boundary */
- pciauto_region_align(pci_io, 0x1000);
-
- pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
- pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
- ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
- }
-}
-
-
-/*
- * HJF: Changed this to return int. I think this is required
- * to get the correct result when scanning bridges
- */
-int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
- unsigned int sub_bus = PCI_BUS(dev);
- unsigned short class;
- int n;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
-
- switch (class) {
- case PCI_CLASS_BRIDGE_PCI:
- debug("PCI Autoconfig: Found P2P bridge, device %d\n",
- PCI_DEV(dev));
-
- pciauto_setup_device(hose, dev, 2, pci_mem,
- pci_prefetch, pci_io);
-
- /* Passing in current_busno allows for sibling P2P bridges */
- hose->current_busno++;
- pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
- /*
- * need to figure out if this is a subordinate bridge on the bus
- * to be able to properly set the pri/sec/sub bridge registers.
- */
- n = pci_hose_scan_bus(hose, hose->current_busno);
-
- /* figure out the deepest we've gone for this leg */
- sub_bus = max((unsigned int)n, sub_bus);
- pciauto_postscan_setup_bridge(hose, dev, sub_bus);
-
- sub_bus = hose->current_busno;
- break;
-
- case PCI_CLASS_BRIDGE_CARDBUS:
- /*
- * just do a minimal setup of the bridge,
- * let the OS take care of the rest
- */
- pciauto_setup_device(hose, dev, 0, pci_mem,
- pci_prefetch, pci_io);
-
- debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
- PCI_DEV(dev));
-
- hose->current_busno++;
- break;
-
-#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
- case PCI_CLASS_BRIDGE_OTHER:
- debug("PCI Autoconfig: Skipping bridge device %d\n",
- PCI_DEV(dev));
- break;
-#endif
-#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
- !defined(CONFIG_TARGET_CADDY2)
- case PCI_CLASS_BRIDGE_OTHER:
- /*
- * The host/PCI bridge 1 seems broken in 8349 - it presents
- * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
- * device claiming resources io/mem/irq.. we only allow for
- * the PIMMR window to be allocated (BAR0 - 1MB size)
- */
- debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
- pciauto_setup_device(hose, dev, 0, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
- break;
-#endif
-
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- debug("PCI AutoConfig: Found PowerPC device\n");
-
- default:
- pciauto_setup_device(hose, dev, 6, pci_mem,
- pci_prefetch, pci_io);
- break;
- }
-
- return sub_bus;
-}
diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c
index 3dfc191..114ef4d 100644
--- a/drivers/power/pmic/tps65941.c
+++ b/drivers/power/pmic/tps65941.c
@@ -72,6 +72,7 @@
static const struct udevice_id tps65941_ids[] = {
{ .compatible = "ti,tps659411", .data = TPS659411 },
{ .compatible = "ti,tps659413", .data = TPS659413 },
+ { .compatible = "ti,lp876441", .data = LP876441 },
{ }
};
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 7c2e480..24e5364 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -81,4 +81,15 @@
help
Say 'y' here to add support for TI power processors such as those
found on certain TI keystone and OMAP generation SoCs.
+
+config REMOTEPROC_TI_PRU
+ bool "Support for TI's K3 based PRU remoteproc driver"
+ select REMOTEPROC
+ depends on DM
+ depends on TI_PRUSS
+ depends on ARCH_K3
+ depends on OF_CONTROL
+ help
+ Say 'y' here to add support for TI' K3 remoteproc driver.
+
endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 69ae7bd..f0e8345 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -14,3 +14,4 @@
obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
+obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
new file mode 100644
index 0000000..924070a
--- /dev/null
+++ b/drivers/remoteproc/pru_rproc.c
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PRU-RTU remoteproc driver for various SoCs
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <elf.h>
+#include <dm/of_access.h>
+#include <remoteproc.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <linux/pruss_driver.h>
+#include <dm/device_compat.h>
+
+/* PRU_ICSS_PRU_CTRL registers */
+#define PRU_CTRL_CTRL 0x0000
+#define PRU_CTRL_STS 0x0004
+#define PRU_CTRL_WAKEUP_EN 0x0008
+#define PRU_CTRL_CYCLE 0x000C
+#define PRU_CTRL_STALL 0x0010
+#define PRU_CTRL_CTBIR0 0x0020
+#define PRU_CTRL_CTBIR1 0x0024
+#define PRU_CTRL_CTPPR0 0x0028
+#define PRU_CTRL_CTPPR1 0x002C
+
+/* CTRL register bit-fields */
+#define CTRL_CTRL_SOFT_RST_N BIT(0)
+#define CTRL_CTRL_EN BIT(1)
+#define CTRL_CTRL_SLEEPING BIT(2)
+#define CTRL_CTRL_CTR_EN BIT(3)
+#define CTRL_CTRL_SINGLE_STEP BIT(8)
+#define CTRL_CTRL_RUNSTATE BIT(15)
+
+#define RPROC_FLAGS_SHIFT 16
+#define RPROC_FLAGS_NONE 0
+#define RPROC_FLAGS_ELF_PHDR BIT(0 + RPROC_FLAGS_SHIFT)
+#define RPROC_FLAGS_ELF_SHDR BIT(1 + RPROC_FLAGS_SHIFT)
+
+/**
+ * enum pru_mem - PRU core memory range identifiers
+ */
+enum pru_mem {
+ PRU_MEM_IRAM = 0,
+ PRU_MEM_CTRL,
+ PRU_MEM_DEBUG,
+ PRU_MEM_MAX,
+};
+
+struct pru_privdata {
+ phys_addr_t pru_iram;
+ phys_addr_t pru_ctrl;
+ phys_addr_t pru_debug;
+ fdt_size_t pru_iramsz;
+ fdt_size_t pru_ctrlsz;
+ fdt_size_t pru_debugsz;
+ const char *fw_name;
+ u32 iram_da;
+ u32 pdram_da;
+ u32 sdram_da;
+ u32 shrdram_da;
+ u32 bootaddr;
+ int id;
+ struct pruss *prusspriv;
+};
+
+static inline u32 pru_control_read_reg(struct pru_privdata *pru, unsigned int reg)
+{
+ return readl(pru->pru_ctrl + reg);
+}
+
+static inline
+void pru_control_write_reg(struct pru_privdata *pru, unsigned int reg, u32 val)
+{
+ writel(val, pru->pru_ctrl + reg);
+}
+
+static inline
+void pru_control_set_reg(struct pru_privdata *pru, unsigned int reg,
+ u32 mask, u32 set)
+{
+ u32 val;
+
+ val = pru_control_read_reg(pru, reg);
+ val &= ~mask;
+ val |= (set & mask);
+ pru_control_write_reg(pru, reg, val);
+}
+
+/**
+ * pru_rproc_set_ctable() - set the constant table index for the PRU
+ * @rproc: the rproc instance of the PRU
+ * @c: constant table index to set
+ * @addr: physical address to set it to
+ */
+static int pru_rproc_set_ctable(struct pru_privdata *pru, enum pru_ctable_idx c, u32 addr)
+{
+ unsigned int reg;
+ u32 mask, set;
+ u16 idx;
+ u16 idx_mask;
+
+ /* pointer is 16 bit and index is 8-bit so mask out the rest */
+ idx_mask = (c >= PRU_C28) ? 0xFFFF : 0xFF;
+
+ /* ctable uses bit 8 and upwards only */
+ idx = (addr >> 8) & idx_mask;
+
+ /* configurable ctable (i.e. C24) starts at PRU_CTRL_CTBIR0 */
+ reg = PRU_CTRL_CTBIR0 + 4 * (c >> 1);
+ mask = idx_mask << (16 * (c & 1));
+ set = idx << (16 * (c & 1));
+
+ pru_control_set_reg(pru, reg, mask, set);
+
+ return 0;
+}
+
+/**
+ * pru_start() - start the pru processor
+ * @dev: corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pru_start(struct udevice *dev)
+{
+ struct pru_privdata *priv;
+ int val = 0;
+
+ priv = dev_get_priv(dev);
+
+ pru_rproc_set_ctable(priv, PRU_C28, 0x100 << 8);
+
+ val = CTRL_CTRL_EN | ((priv->bootaddr >> 2) << 16);
+ writel(val, priv->pru_ctrl + PRU_CTRL_CTRL);
+
+ return 0;
+}
+
+/**
+ * pru_stop() - Stop pru processor
+ * @dev: corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pru_stop(struct udevice *dev)
+{
+ struct pru_privdata *priv;
+ int val = 0;
+
+ priv = dev_get_priv(dev);
+
+ val = readl(priv->pru_ctrl + PRU_CTRL_CTRL);
+ val &= ~CTRL_CTRL_EN;
+ writel(val, priv->pru_ctrl + PRU_CTRL_CTRL);
+
+ return 0;
+}
+
+/**
+ * pru_init() - Initialize the remote processor
+ * @dev: rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int pru_init(struct udevice *dev)
+{
+ return 0;
+}
+
+/*
+ * Convert PRU device address (data spaces only) to kernel virtual address
+ *
+ * Each PRU has access to all data memories within the PRUSS, accessible at
+ * different ranges. So, look through both its primary and secondary Data
+ * RAMs as well as any shared Data RAM to convert a PRU device address to
+ * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data
+ * RAM1 is primary Data RAM for PRU1.
+ */
+static void *pru_d_da_to_pa(struct pru_privdata *priv, u32 da, int len)
+{
+ u32 offset;
+ void *pa = NULL;
+ phys_addr_t dram0, dram1, shrdram2;
+ u32 dram0sz, dram1sz, shrdram2sz;
+
+ if (len <= 0)
+ return NULL;
+
+ dram0 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM0].pa;
+ dram1 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].pa;
+ shrdram2 = priv->prusspriv->mem_regions[PRUSS_MEM_SHRD_RAM2].pa;
+ dram0sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM0].size;
+ dram1sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].size;
+ shrdram2sz = priv->prusspriv->mem_regions[PRUSS_MEM_SHRD_RAM2].size;
+
+ /* PRU1 has its local RAM addresses reversed */
+ if (priv->id == 1) {
+ dram1 = dram0;
+ dram1sz = dram0sz;
+
+ dram0 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].pa;
+ dram0sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].size;
+ }
+
+ if (da >= priv->pdram_da && da + len <= priv->pdram_da + dram0sz) {
+ offset = da - priv->pdram_da;
+ pa = (__force void *)(dram0 + offset);
+ } else if (da >= priv->sdram_da &&
+ da + len <= priv->sdram_da + dram1sz) {
+ offset = da - priv->sdram_da;
+ pa = (__force void *)(dram1 + offset);
+ } else if (da >= priv->shrdram_da &&
+ da + len <= priv->shrdram_da + shrdram2sz) {
+ offset = da - priv->shrdram_da;
+ pa = (__force void *)(shrdram2 + offset);
+ }
+
+ return pa;
+}
+
+/*
+ * Convert PRU device address (instruction space) to kernel virtual address
+ *
+ * A PRU does not have an unified address space. Each PRU has its very own
+ * private Instruction RAM, and its device address is identical to that of
+ * its primary Data RAM device address.
+ */
+static void *pru_i_da_to_pa(struct pru_privdata *priv, u32 da, int len)
+{
+ u32 offset;
+ void *pa = NULL;
+
+ if (len <= 0)
+ return NULL;
+
+ if (da >= priv->iram_da &&
+ da + len <= priv->iram_da + priv->pru_iramsz) {
+ offset = da - priv->iram_da;
+ pa = (__force void *)(priv->pru_iram + offset);
+ }
+
+ return pa;
+}
+
+/* PRU-specific address translator */
+static void *pru_da_to_pa(struct pru_privdata *priv, u64 da, int len, u32 flags)
+{
+ void *pa;
+ u32 exec_flag;
+
+ exec_flag = ((flags & RPROC_FLAGS_ELF_SHDR) ? flags & SHF_EXECINSTR :
+ ((flags & RPROC_FLAGS_ELF_PHDR) ? flags & PF_X : 0));
+
+ if (exec_flag)
+ pa = pru_i_da_to_pa(priv, da, len);
+ else
+ pa = pru_d_da_to_pa(priv, da, len);
+
+ return pa;
+}
+
+/*
+ * Custom memory copy implementation for ICSSG PRU/RTU Cores
+ *
+ * The ICSSG PRU/RTU cores have a memory copying issue with IRAM memories, that
+ * is not seen on previous generation SoCs. The data is reflected properly in
+ * the IRAM memories only for integer (4-byte) copies. Any unaligned copies
+ * result in all the other pre-existing bytes zeroed out within that 4-byte
+ * boundary, thereby resulting in wrong text/code in the IRAMs. Also, the
+ * IRAM memory port interface does not allow any 8-byte copies (as commonly
+ * used by ARM64 memcpy implementation) and throws an exception. The DRAM
+ * memory ports do not show this behavior. Use this custom copying function
+ * to properly load the PRU/RTU firmware images on all memories for simplicity.
+ *
+ * TODO: Improve the function to deal with additional corner cases like
+ * unaligned copy sizes or sub-integer trailing bytes when the need arises.
+ */
+static int pru_rproc_memcpy(void *dest, void *src, size_t count)
+{
+ const int *s = src;
+ int *d = dest;
+ int size = count / 4;
+ int *tmp_src = NULL;
+
+ /* limited to 4-byte aligned addresses and copy sizes */
+ if ((long)dest % 4 || count % 4)
+ return -EINVAL;
+
+ /* src offsets in ELF firmware image can be non-aligned */
+ if ((long)src % 4) {
+ tmp_src = malloc(count);
+ if (!tmp_src)
+ return -ENOMEM;
+
+ memcpy(tmp_src, src, count);
+ s = tmp_src;
+ }
+
+ while (size--)
+ *d++ = *s++;
+
+ kfree(tmp_src);
+
+ return 0;
+}
+
+/**
+ * pru_load() - Load pru firmware
+ * @dev: corresponding k3 remote processor device
+ * @addr: Address on the RAM from which firmware is to be loaded
+ * @size: Size of the pru firmware in bytes
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pru_load(struct udevice *dev, ulong addr, ulong size)
+{
+ struct pru_privdata *priv;
+ Elf32_Ehdr *ehdr;
+ Elf32_Phdr *phdr;
+ int i, ret = 0;
+
+ priv = dev_get_priv(dev);
+
+ ehdr = (Elf32_Ehdr *)addr;
+ phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
+
+ /* go through the available ELF segments */
+ for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
+ u32 da = phdr->p_paddr;
+ u32 memsz = phdr->p_memsz;
+ u32 filesz = phdr->p_filesz;
+ u32 offset = phdr->p_offset;
+ void *ptr;
+
+ if (phdr->p_type != PT_LOAD)
+ continue;
+
+ dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n",
+ phdr->p_type, da, memsz, filesz);
+
+ if (filesz > memsz) {
+ dev_dbg(dev, "bad phdr filesz 0x%x memsz 0x%x\n",
+ filesz, memsz);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (offset + filesz > size) {
+ dev_dbg(dev, "truncated fw: need 0x%x avail 0x%zx\n",
+ offset + filesz, size);
+ ret = -EINVAL;
+ break;
+ }
+
+ /* grab the kernel address for this device address */
+ ptr = pru_da_to_pa(priv, da, memsz,
+ RPROC_FLAGS_ELF_PHDR | phdr->p_flags);
+ if (!ptr) {
+ dev_dbg(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz);
+ ret = -EINVAL;
+ break;
+ }
+
+ /* skip the memzero logic performed by remoteproc ELF loader */
+ if (!phdr->p_filesz)
+ continue;
+
+ ret = pru_rproc_memcpy(ptr,
+ (void *)addr + phdr->p_offset, filesz);
+ if (ret) {
+ dev_dbg(dev, "PRU custom memory copy failed for da 0x%x memsz 0x%x\n",
+ da, memsz);
+ break;
+ }
+ }
+
+ priv->bootaddr = ehdr->e_entry;
+
+ return ret;
+}
+
+static const struct dm_rproc_ops pru_ops = {
+ .init = pru_init,
+ .start = pru_start,
+ .stop = pru_stop,
+ .load = pru_load,
+};
+
+static void pru_set_id(struct pru_privdata *priv, struct udevice *dev)
+{
+ u32 mask2 = 0x38000;
+
+ if (device_is_compatible(dev, "ti,am654-rtu"))
+ mask2 = 0x6000;
+
+ if (device_is_compatible(dev, "ti,am654-tx-pru"))
+ mask2 = 0xc000;
+
+ if ((priv->pru_iram & mask2) == mask2)
+ priv->id = 1;
+ else
+ priv->id = 0;
+}
+
+/**
+ * pru_probe() - Basic probe
+ * @dev: corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pru_probe(struct udevice *dev)
+{
+ struct pru_privdata *priv;
+ ofnode node;
+
+ node = dev_ofnode(dev);
+
+ priv = dev_get_priv(dev);
+ priv->prusspriv = dev_get_priv(dev->parent);
+
+ priv->pru_iram = devfdt_get_addr_size_index(dev, PRU_MEM_IRAM,
+ &priv->pru_iramsz);
+ priv->pru_ctrl = devfdt_get_addr_size_index(dev, PRU_MEM_CTRL,
+ &priv->pru_ctrlsz);
+ priv->pru_debug = devfdt_get_addr_size_index(dev, PRU_MEM_DEBUG,
+ &priv->pru_debugsz);
+
+ priv->iram_da = 0;
+ priv->pdram_da = 0;
+ priv->sdram_da = 0x2000;
+ priv->shrdram_da = 0x10000;
+
+ pru_set_id(priv, dev);
+
+ return 0;
+}
+
+static const struct udevice_id pru_ids[] = {
+ { .compatible = "ti,am654-pru"},
+ { .compatible = "ti,am654-rtu"},
+ { .compatible = "ti,am654-tx-pru" },
+ {}
+};
+
+U_BOOT_DRIVER(pru) = {
+ .name = "pru",
+ .of_match = pru_ids,
+ .id = UCLASS_REMOTEPROC,
+ .ops = &pru_ops,
+ .probe = pru_probe,
+ .priv_auto = sizeof(struct pru_privdata),
+};
diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig
index e4f8834..0ee21f9 100644
--- a/drivers/soc/ti/Kconfig
+++ b/drivers/soc/ti/Kconfig
@@ -23,4 +23,15 @@
SerDes driver for Keystone SoC used for ethernet support on TI
K2 platforms.
+config TI_PRUSS
+ bool "Support for TI's K3 based Pruss driver"
+ depends on DM
+ depends on ARCH_K3
+ depends on OF_CONTROL
+ depends on SYSCON
+ help
+ Support for TI PRU-ICSSG subsystem.
+ Currently supported on AM65xx SoCs Say Y here to support the
+ Programmable Realtime Unit (PRU).
+
endif # SOC_TI
diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile
index 4ec04ee..34f80aa 100644
--- a/drivers/soc/ti/Makefile
+++ b/drivers/soc/ti/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_TI_K3_NAVSS_RINGACC) += k3-navss-ringacc.o
obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
+obj-$(CONFIG_TI_PRUSS) += pruss.o
diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
new file mode 100644
index 0000000..4613909
--- /dev/null
+++ b/drivers/soc/ti/pruss.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PRU-ICSS platform driver for various TI SoCs
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <linux/pruss_driver.h>
+#include <dm/device_compat.h>
+
+#define PRUSS_CFG_IEPCLK 0x30
+#define ICSSG_CFG_CORE_SYNC 0x3c
+
+#define ICSSG_TASK_MGR_OFFSET 0x2a000
+
+/* PRUSS_IEPCLK register bits */
+#define PRUSS_IEPCLK_IEP_OCP_CLK_EN BIT(0)
+
+/* ICSSG CORE_SYNC register bits */
+#define ICSSG_CORE_VBUSP_SYNC_EN BIT(0)
+
+/*
+ * pruss_request_tm_region() - Request pruss for task manager region
+ * @dev: corresponding k3 device
+ * @loc: the task manager physical address
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+int pruss_request_tm_region(struct udevice *dev, phys_addr_t *loc)
+{
+ struct pruss *priv;
+
+ priv = dev_get_priv(dev);
+ if (!priv || !priv->mem_regions[PRUSS_MEM_DRAM0].pa)
+ return -EINVAL;
+
+ *loc = priv->mem_regions[PRUSS_MEM_DRAM0].pa + ICSSG_TASK_MGR_OFFSET;
+
+ return 0;
+}
+
+/**
+ * pruss_request_mem_region() - request a memory resource
+ * @dev: the pruss device
+ * @mem_id: the memory resource id
+ * @region: pointer to memory region structure to be filled in
+ *
+ * This function allows a client driver to request a memory resource,
+ * and if successful, will let the client driver own the particular
+ * memory region until released using the pruss_release_mem_region()
+ * API.
+ *
+ * Returns the memory region if requested resource is available, an
+ * error otherwise
+ */
+int pruss_request_mem_region(struct udevice *dev, enum pruss_mem mem_id,
+ struct pruss_mem_region *region)
+{
+ struct pruss *pruss;
+
+ pruss = dev_get_priv(dev);
+ if (!pruss || !region)
+ return -EINVAL;
+
+ if (mem_id >= PRUSS_MEM_MAX)
+ return -EINVAL;
+
+ if (pruss->mem_in_use[mem_id])
+ return -EBUSY;
+
+ *region = pruss->mem_regions[mem_id];
+ pruss->mem_in_use[mem_id] = region;
+
+ return 0;
+}
+
+/**
+ * pruss_release_mem_region() - release a memory resource
+ * @dev: the pruss device
+ * @region: the memory region to release
+ *
+ * This function is the complimentary function to
+ * pruss_request_mem_region(), and allows the client drivers to
+ * release back a memory resource.
+ *
+ * Returns 0 on success, an error code otherwise
+ */
+int pruss_release_mem_region(struct udevice *dev,
+ struct pruss_mem_region *region)
+{
+ struct pruss *pruss;
+ int id;
+
+ pruss = dev_get_priv(dev);
+ if (!pruss || !region)
+ return -EINVAL;
+
+ /* find out the memory region being released */
+ for (id = 0; id < PRUSS_MEM_MAX; id++) {
+ if (pruss->mem_in_use[id] == region)
+ break;
+ }
+
+ if (id == PRUSS_MEM_MAX)
+ return -EINVAL;
+
+ pruss->mem_in_use[id] = NULL;
+
+ return 0;
+}
+
+/**
+ * pruss_cfg_update() - configure a PRUSS CFG sub-module register
+ * @dev: the pruss device
+ * @reg: register offset within the CFG sub-module
+ * @mask: bit mask to use for programming the @val
+ * @val: value to write
+ *
+ * Programs a given register within the PRUSS CFG sub-module
+ *
+ * Returns 0 on success, or an error code otherwise
+ */
+int pruss_cfg_update(struct udevice *dev, unsigned int reg,
+ unsigned int mask, unsigned int val)
+{
+ struct pruss *pruss;
+
+ pruss = dev_get_priv(dev);
+ if (IS_ERR_OR_NULL(pruss))
+ return -EINVAL;
+
+ return regmap_update_bits(pruss->cfg, reg, mask, val);
+}
+
+/**
+ * pruss_probe() - Basic probe
+ * @dev: corresponding k3 device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pruss_probe(struct udevice *dev)
+{
+ const char *mem_names[PRUSS_MEM_MAX] = { "dram0", "dram1", "shrdram2" };
+ ofnode sub_node, node, memories;
+ struct udevice *syscon;
+ struct pruss *priv;
+ int ret, idx, i;
+
+ priv = dev_get_priv(dev);
+ node = dev_ofnode(dev);
+ priv->dev = dev;
+ memories = ofnode_find_subnode(node, "memories");
+
+ for (i = 0; i < ARRAY_SIZE(mem_names); i++) {
+ idx = ofnode_stringlist_search(memories, "reg-names", mem_names[i]);
+ priv->mem_regions[i].pa = ofnode_get_addr_size_index(memories, idx,
+ (u64 *)&priv->mem_regions[i].size);
+ }
+
+ sub_node = ofnode_find_subnode(node, "cfg");
+ ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, sub_node,
+ &syscon);
+
+ priv->cfg = syscon_get_regmap(syscon);
+ if (IS_ERR(priv->cfg)) {
+ dev_err(dev, "unable to get cfg regmap (%ld)\n",
+ PTR_ERR(priv->cfg));
+ return -ENODEV;
+ }
+
+ /*
+ * ToDo: To be modelled as clocks.
+ * The CORE block uses two multiplexers to allow software to
+ * select one of three source clocks (ICSSGn_CORE_CLK, ICSSGn_ICLK or
+ * ICSSGn_IEP_CLK) for the final clock source of the CORE block.
+ * The user needs to configure ICSSG_CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN
+ * bit & ICSSG_IEPCLK_REG[0] IEP_OCP_CLK_EN bit in order to select the
+ * clock source to the CORE block.
+ */
+ ret = regmap_update_bits(priv->cfg, ICSSG_CFG_CORE_SYNC,
+ ICSSG_CORE_VBUSP_SYNC_EN,
+ ICSSG_CORE_VBUSP_SYNC_EN);
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->cfg, PRUSS_CFG_IEPCLK,
+ PRUSS_IEPCLK_IEP_OCP_CLK_EN,
+ PRUSS_IEPCLK_IEP_OCP_CLK_EN);
+ if (ret)
+ return ret;
+
+ dev_dbg(dev, "pruss successfully probed %s\n", dev->name);
+
+ return 0;
+}
+
+static const struct udevice_id pruss_ids[] = {
+ { .compatible = "ti,am654-icssg"},
+ {}
+};
+
+U_BOOT_DRIVER(pruss) = {
+ .name = "pruss",
+ .of_match = pruss_ids,
+ .id = UCLASS_MISC,
+ .probe = pruss_probe,
+ .priv_auto = sizeof(struct pruss),
+};
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index f697573..ab1d061 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -34,8 +34,8 @@
if USB
config DM_USB
- bool "Enable driver model for USB"
- depends on USB && DM
+ bool
+ depends on DM && OF_CONTROL
help
Enable driver model for USB. The USB interface is then implemented
by the USB uclass. Multiple USB controllers of different types
@@ -48,7 +48,7 @@
automatically probed when found on the bus.
config SPL_DM_USB
- bool "Enable driver model for USB in SPL"
+ bool "Enable driver model for USB host most in SPL"
depends on SPL_DM && DM_USB
default y
@@ -84,6 +84,8 @@
source "drivers/usb/ulpi/Kconfig"
+if USB_HOST
+
comment "USB peripherals"
config USB_STORAGE
@@ -129,8 +131,10 @@
endif
-source "drivers/usb/gadget/Kconfig"
-
source "drivers/usb/eth/Kconfig"
endif
+
+source "drivers/usb/gadget/Kconfig"
+
+endif
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 4cf59c7..05785fc 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -1,6 +1,6 @@
config USB_CDNS3
tristate "Cadence USB3 Dual-Role Controller"
- depends on USB_HOST || USB_GADGET
+ depends on USB_XHCI_HCD || USB_GADGET
help
Say Y here if your system has a Cadence USB3 dual-role controller.
It supports: Host-only, and Peripheral-only.
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 802ee50..93707e0 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -1,6 +1,6 @@
config USB_DWC3
bool "DesignWare USB3 DRD Core Support"
- depends on USB_HOST || USB_GADGET
+ depends on USB_XHCI_HCD || USB_GADGET
help
Say Y here if your system has a Dual Role SuperSpeed
USB controller based on the DesignWare USB3 IP Core.
diff --git a/drivers/usb/emul/Kconfig b/drivers/usb/emul/Kconfig
index ae1ab23..279f6c6 100644
--- a/drivers/usb/emul/Kconfig
+++ b/drivers/usb/emul/Kconfig
@@ -1,6 +1,8 @@
config USB_EMUL
bool "Support for USB device emulation"
- depends on DM_USB && SANDBOX
+ depends on SANDBOX
+ select DM_USB
+ select USB_HOST
help
Since sandbox does not have access to a real USB bus, it is possible
to use device emulators instead. This allows testing of the USB
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 4a3b22e..327ea86 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -15,6 +15,8 @@
menuconfig USB_GADGET
bool "USB Gadget Support"
+ depends on DM
+ select DM_USB
help
USB is a master/slave protocol, organized with one master
host (such as a PC) controlling up to 127 peripheral devices.
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index f34cba2..427b360 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -5,9 +5,11 @@
config USB_HOST
bool
+ select DM_USB
config USB_XHCI_HCD
bool "xHCI HCD (USB 3.0) support"
+ depends on DM && OF_CONTROL
select USB_HOST
---help---
The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
@@ -107,6 +109,7 @@
config USB_EHCI_HCD
bool "EHCI HCD (USB 2.0) support"
default y if ARCH_MX5 || ARCH_MX6
+ depends on DM && OF_CONTROL
select USB_HOST
---help---
The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
@@ -217,7 +220,6 @@
config USB_EHCI_GENERIC
bool "Support for generic EHCI USB controller"
- depends on OF_CONTROL
depends on DM_USB
default ARCH_SUNXI
default n
@@ -234,6 +236,8 @@
config USB_OHCI_HCD
bool "OHCI HCD (USB 1.1) support"
+ depends on DM && OF_CONTROL
+ select USB_HOST
---help---
The Open Host Controller Interface (OHCI) is a standard for accessing
USB 1.1 host controller hardware. It does more in hardware than Intel's
@@ -244,21 +248,17 @@
based system where you're not sure, the "lspci -v" entry will list the
right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI.
+if USB_OHCI_HCD
+
config USB_OHCI_PCI
bool "Support for PCI-based OHCI USB controller"
- depends on DM_USB
- default n
+ depends on PCI
help
Enables support for the PCI-based OHCI controller.
-if USB_OHCI_HCD
-
config USB_OHCI_GENERIC
bool "Support for generic OHCI USB controller"
- depends on OF_CONTROL
- depends on DM_USB
default ARCH_SUNXI
- select USB_HOST
---help---
Enables support for generic OHCI controller.
@@ -289,6 +289,7 @@
config USB_DWC2
bool "DesignWare USB2 Core support"
+ depends on DM && OF_CONTROL
select USB_HOST
---help---
The DesignWare USB 2.0 controller is compliant with the
@@ -311,8 +312,7 @@
config USB_R8A66597_HCD
bool "Renesas R8A66597 USB Core support"
- depends on OF_CONTROL
- depends on DM_USB
+ depends on DM && OF_CONTROL
select USB_HOST
---help---
This enables support for the on-chip Renesas R8A66597 USB 2.0
diff --git a/drivers/usb/mtu3/Kconfig b/drivers/usb/mtu3/Kconfig
index a2a5991..5ec498e 100644
--- a/drivers/usb/mtu3/Kconfig
+++ b/drivers/usb/mtu3/Kconfig
@@ -4,7 +4,7 @@
config USB_MTU3
bool "MediaTek USB3 Dual Role controller"
- depends on USB_HOST || USB_GADGET
+ depends on USB_XHCI_HCD || USB_GADGET
depends on ARCH_MEDIATEK
help
Say Y here if your system runs on MediaTek SoCs with
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 81ceea9..a9a7c26 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -5,22 +5,26 @@
config USB_MUSB_HOST
bool "MUSB host mode support"
+ depends on DM && OF_CONTROL
select SPL_SPRINTF if SPL
select TPL_SPRINTF if TPL
+ select USB_HOST
help
Enables the MUSB USB dual-role controller in host mode.
config USB_MUSB_GADGET
bool "MUSB gadget mode support"
+ depends on USB_GADGET
select USB_GADGET_DUALSPEED
select SPL_SPRINTF if SPL
select TPL_SPRINTF if TPL
help
Enables the MUSB USB dual-role controller in gadget mode.
+if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_DA8XX
bool "Enable DA8xx MUSB Controller"
- depends on DM_USB
+ depends on ARCH_DAVINCI
help
Say y here to enable support for the dual role high
speed USB controller based on the Mentor Graphics
@@ -28,7 +32,7 @@
config USB_MUSB_TI
bool "Enable TI OTG USB controller"
- depends on DM_USB
+ depends on AM33XX
select USB_MUSB_DSPS
default n
help
@@ -46,10 +50,9 @@
config USB_MUSB_DSPS
bool "TI DSPS platforms"
-if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_MT85XX
bool "Enable Mediatek MT85XX DRC USB controller"
- depends on DM_USB && ARCH_MEDIATEK
+ depends on ARCH_MEDIATEK
default n
help
Say y to enable Mediatek MT85XX USB DRC controller support
@@ -59,7 +62,7 @@
config USB_MUSB_PIC32
bool "Enable Microchip PIC32 DRC USB controller"
- depends on DM_USB && MACH_PIC32
+ depends on MACH_PIC32
help
Say y to enable PIC32 USB DRC controller support
if it is available on your Microchip PIC32 platform.
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 933f06e..1c534a6 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -15,7 +15,7 @@
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
obj-$(CONFIG_PANEL) += panel-uclass.o
-obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o
+obj-$(CONFIG_DM_PANEL_HX8238D) += hx8238d.o
obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
endif
diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c
index f7e7753..6ee97cb 100644
--- a/drivers/video/hx8238d.c
+++ b/drivers/video/hx8238d.c
@@ -191,7 +191,7 @@
.name = "hx8238d",
.id = UCLASS_PANEL,
.of_match = hx8238d_ids,
- .ofdata_to_platdata = hx8238d_ofdata_to_platdata,
+ .of_to_plat = hx8238d_ofdata_to_platdata,
.probe = hx8238d_probe,
- .priv_auto_alloc_size = sizeof(struct hx8238d_priv),
+ .priv_auto = sizeof(struct hx8238d_priv),
};
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
deleted file mode 100644
index 0428be7..0000000
--- a/include/configs/M52277EVB.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF52277 EVB board.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M52277EVB_H
-#define _M52277EVB_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_HOSTNAME "M52277EVB"
-#define CONFIG_SYS_UBOOT_END 0x3FFFF
-#define CONFIG_SYS_LOAD_ADDR2 0x40010007
-#ifdef CONFIG_SYS_STMICRO_BOOT
-/* ST Micro serial flash */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "uboot=u-boot.bin\0" \
- "load=loadb ${loadaddr} ${baudrate};" \
- "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
- "upd=run load; run prog\0" \
- "prog=sf probe 0:2 10000 1;" \
- "sf erase 0 30000;" \
- "sf write ${loadaddr} 0 30000;" \
- "save\0" \
- ""
-#endif
-#ifdef CONFIG_SYS_SPANSION_BOOT
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "uboot=u-boot.bin\0" \
- "load=loadb ${loadaddr} ${baudrate}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
- " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
- "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
- __stringify(CONFIG_SYS_UBOOT_END) ";" \
- "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
- " ${filesize}; save\0" \
- "updsbf=run loadsbf; run progsbf\0" \
- "loadsbf=loadb ${loadaddr} ${baudrate};" \
- "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
- "progsbf=sf probe 0:2 10000 1;" \
- "sf erase 0 30000;" \
- "sf write ${loadaddr} 0 30000;" \
- ""
-#endif
-
-/* LCD */
-#ifdef CONFIG_CMD_BMP
-#define CONFIG_LCD_LOGO
-#define CONFIG_SHARP_LQ035Q7DH06
-#endif
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
-#define CONFIG_SYS_USB_EHCI_CPU_INIT
-#endif
-
-/* Realtime clock */
-#define CONFIG_MCFRTC
-#undef RTC_DEBUG
-#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SYS_SBFHDR_SIZE 0x7
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_SYS_INPUT_CLKSRC 16000000
-
-#define CONFIG_PRAM 2048 /* 2048 KB */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR 0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x43711630
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD 0x81810000
-#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
-#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
-
-#ifdef CONFIG_CF_SBF
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
-
-/*
- * Configuration for environment
- * Environment is not embedded in u-boot. First time runing may have env
- * crc error warning if there is no correct environment on the flash.
- */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_STMICRO_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-#endif
-#ifdef CONFIG_SYS_SPANSION_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-#endif
-
-#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_FLASH_SPANSION_S29WS_N 1
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-# define CONFIG_SYS_FLASH_CHECKSUM
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
-#endif
-
-#define LDS_BOARD_TEXT \
- arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
- arch/m68k/lib/built-in.o (.text*)
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-# define CONFIG_JFFS2_DEV "nor0"
-# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
- CF_CACR_DISD | CF_CACR_INVI | \
- CF_CACR_CEIB | CF_CACR_DCM | \
- CF_CACR_EUSP)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash
- * CS1 - Available
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-
-#ifdef CONFIG_CF_SBF
-#define CONFIG_SYS_CS0_BASE 0x04000000
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
-#else
-#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
-#endif
-
-#endif /* _M52277EVB_H */
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
deleted file mode 100644
index 5447f84..0000000
--- a/include/configs/M54418TWR.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF54418 TWR board.
- *
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M54418TWR_H
-#define _M54418TWR_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * NAND FLASH
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_JFFS2_NAND
-#define CONFIG_NAND_FSL_NFC
-#define CONFIG_SYS_NAND_BASE 0xFC0FC000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_NAND_SELECT_DEVICE
-#endif
-
-/* Network configuration */
-#ifdef CONFIG_MCFFEC
-#define CONFIG_MII_INIT 1
-#define CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_SYS_RX_ETH_BUFFER 2
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_SYS_TX_ETH_BUFFER 2
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_ETHPRIME "FEC0"
-#define CONFIG_IPADDR 192.168.1.2
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-
-#define CONFIG_SYS_FEC_BUF_USE_SRAM
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-#ifndef CONFIG_SYS_DISCOVER_PHY
-#define FECDUPLEX FULL
-#define FECSPEED _100BASET
-#define LINKSTATUS 1
-#else
-#define LINKSTATUS 0
-#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#endif
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#define CONFIG_HOSTNAME "M54418TWR"
-
-#if defined(CONFIG_CF_SBF)
-/* ST Micro serial flash */
-#define CONFIG_SYS_LOAD_ADDR2 0x40010007
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "sbfhdr=sbfhdr.bin\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
- "upd=run load; run prog\0" \
- "prog=sf probe 0:1 1000000 3;" \
- "sf erase 0 40000;" \
- "sf write ${loadaddr} 0 40000;" \
- "save\0" \
- ""
-#elif defined(CONFIG_SYS_NAND_BOOT)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot};\0" \
- "upd=run load; run prog\0" \
- "prog=nand device 0;" \
- "nand erase 0 40000;" \
- "nb_update ${loadaddr} ${filesize};" \
- "save\0" \
- ""
-#else
-#define CONFIG_SYS_UBOOT_END 0x3FFFF
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=40010000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr) ${u-boot}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off mram" " ;" \
- "cp.b ${loadaddr} 0 ${filesize};" \
- "save\0" \
- ""
-#endif
-
-/* Realtime clock */
-#undef CONFIG_MCFRTC
-#define CONFIG_RTC_MCFRRTC
-#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#undef CONFIG_SYS_FSL_I2C
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SERIAL_FLASH
-#define CONFIG_SYS_SBFHDR_SIZE 0x7
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_PRAM 2048 /* 2048 KB */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR 0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-/* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
-
-#define CONFIG_SYS_DRAM_TEST
-
-#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
-#define CONFIG_SERIAL_BOOT
-#endif
-
-#if defined(CONFIG_SERIAL_BOOT)
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-
-#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
-/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
- (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-
-/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-
-#ifdef CONFIG_SYS_FLASH_CFI
-
-/* Max size that the board might have */
-#define CONFIG_SYS_FLASH_SIZE 0x1000000
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 270
-/* "Real" (hardware) sectors protection */
-#define CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
-#else
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 270
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 0
-#endif
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_OFFSET (0x800000)
-
-#endif
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
- CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
- CF_CACR_DEC | CF_CACR_DDCM_P | \
- CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 12)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash 16MB
- * CS1 - Available
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-
- /* Flash */
-#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x000F0101
-#define CONFIG_SYS_CS0_CTRL 0x00001D60
-
-#endif /* _M54418TWR_H */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
deleted file mode 100644
index f5bafb7..0000000
--- a/include/configs/M54451EVB.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF54451 EVB board.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M54451EVB_H
-#define _M54451EVB_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_M54451EVB /* M54451EVB board */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-
-#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* Network configuration */
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_ETHPRIME "FEC0"
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#define CONFIG_HOSTNAME "M54451EVB"
-#ifdef CONFIG_SYS_STMICRO_BOOT
-/* ST Micro serial flash */
-#define CONFIG_SYS_LOAD_ADDR2 0x40010007
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "sbfhdr=sbfhdr.bin\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
- "upd=run load; run prog\0" \
- "prog=sf probe 0:1 1000000 3;" \
- "sf erase 0 30000;" \
- "sf write ${loadaddr} 0 30000;" \
- "save\0" \
- ""
-#else
-#define CONFIG_SYS_UBOOT_END 0x3FFFF
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=40010000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr) ${u-boot}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
- "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
- "cp.b ${loadaddr} 0 ${filesize};" \
- "save\0" \
- ""
-#endif
-
-/* Realtime clock */
-#define CONFIG_MCFRTC
-#undef RTC_DEBUG
-#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SERIAL_FLASH
-#define CONFIG_SYS_SBFHDR_SIZE 0x7
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_PRAM 2048 /* 2048 KB */
-
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR 0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
-#define CONFIG_SYS_SDRAM_CFG2 0x57670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
-#define CONFIG_SYS_SDRAM_EMOD 0x80810000
-#define CONFIG_SYS_SDRAM_MODE 0x008D0000
-#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
-
-#ifdef CONFIG_CF_SBF
-# define CONFIG_SERIAL_BOOT
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* Configuration for environment
- * Environment is not embedded in u-boot. First time runing may have env
- * crc error warning if there is no correct environment on the flash.
- */
-
-/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-
-#ifdef CONFIG_SYS_FLASH_CFI
-
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-# define CONFIG_SYS_FLASH_CHECKSUM
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
-
-#endif
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-# define CONFIG_JFFS2_DEV "nor0"
-# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
-#endif
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
- CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
- CF_CACR_DEC | CF_CACR_DDCM_P | \
- CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash 16MB
- * CS1 - Available
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-
- /* Flash */
-#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00004D80
-
-#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
-
-#endif /* _M54451EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
deleted file mode 100644
index f3621d6..0000000
--- a/include/configs/M54455EVB.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF54455 EVB board.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M54455EVB_H
-#define _M54455EVB_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_M54455EVB /* M54455EVB board */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-
-#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* Network configuration */
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_HAS_ETH1
-# define CONFIG_ETHPRIME "FEC0"
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#define CONFIG_HOSTNAME "M54455EVB"
-#ifdef CONFIG_SYS_STMICRO_BOOT
-/* ST Micro serial flash */
-#define CONFIG_SYS_LOAD_ADDR2 0x40010013
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "sbfhdr=sbfhdr.bin\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
- "upd=run load; run prog\0" \
- "prog=sf probe 0:1 1000000 3;" \
- "sf erase 0 30000;" \
- "sf write ${loadaddr} 0 0x30000;" \
- "save\0" \
- ""
-#else
-/* Atmel and Intel */
-#ifdef CONFIG_SYS_ATMEL_BOOT
-# define CONFIG_SYS_UBOOT_END 0x0403FFFF
-#elif defined(CONFIG_SYS_INTEL_BOOT)
-# define CONFIG_SYS_UBOOT_END 0x3FFFF
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${uboot}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
- " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
- "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
- __stringify(CONFIG_SYS_UBOOT_END) ";" \
- "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
- " ${filesize}; save\0" \
- ""
-#endif
-
-/* ATA configuration */
-#define CONFIG_IDE_RESET 1
-#define CONFIG_IDE_PREINIT 1
-#define CONFIG_ATAPI
-#undef CONFIG_LBA48
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
-#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
-
-/* Realtime clock */
-#define CONFIG_MCFRTC
-#undef RTC_DEBUG
-#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SYS_SBFHDR_SIZE 0x13
-
-/* PCI */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
-
-#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
-#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
-#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
-#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
-#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
-#endif
-
-/* FPGA - Spartan 2 */
-/* experiment
-#define CONFIG_FPGA_COUNT 1
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_CHECK_CTRLC
-*/
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_PRAM 2048 /* 2048 KB */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR 0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_BASE1 0x48000000
-#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x65311610
-#define CONFIG_SYS_SDRAM_CFG2 0x59670000
-#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
-#define CONFIG_SYS_SDRAM_EMOD 0x40010000
-#define CONFIG_SYS_SDRAM_MODE 0x00010033
-#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
-
-#ifdef CONFIG_CF_SBF
-# define CONFIG_SERIAL_BOOT
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/*
- * Configuration for environment
- * Environment is not embedded in u-boot. First time runing may have env
- * crc error warning if there is no correct environment on the flash.
- */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_STMICRO_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
-#endif
-#ifdef CONFIG_SYS_ATMEL_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
-#endif
-#ifdef CONFIG_SYS_INTEL_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
-#endif
-
-#ifdef CONFIG_SYS_FLASH_CFI
-
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-# define CONFIG_SYS_FLASH_CHECKSUM
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
-# define CONFIG_FLASH_CFI_LEGACY
-
-#ifdef CONFIG_FLASH_CFI_LEGACY
-# define CONFIG_SYS_ATMEL_REGION 4
-# define CONFIG_SYS_ATMEL_TOTALSECT 11
-# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
-# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
-#endif
-#endif
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-#ifdef CF_STMICRO_BOOT
-# define CONFIG_JFFS2_DEV "nor1"
-# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
-#endif
-#ifdef CONFIG_SYS_ATMEL_BOOT
-# define CONFIG_JFFS2_DEV "nor1"
-# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
-#endif
-#ifdef CONFIG_SYS_INTEL_BOOT
-# define CONFIG_JFFS2_DEV "nor0"
-# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
-#endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
- CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
- CF_CACR_DEC | CF_CACR_DDCM_P | \
- CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash 1, 2, 4, or 8MB
- * CS1 - CompactFlash and registers
- * CS2 - CPLD
- * CS3 - FPGA
- * CS4 - Available
- * CS5 - Available
- */
-
-#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
- /* Atmel Flash */
-#define CONFIG_SYS_CS0_BASE 0x04000000
-#define CONFIG_SYS_CS0_MASK 0x00070001
-#define CONFIG_SYS_CS0_CTRL 0x00001140
-/* Intel Flash */
-#define CONFIG_SYS_CS1_BASE 0x00000000
-#define CONFIG_SYS_CS1_MASK 0x01FF0001
-#define CONFIG_SYS_CS1_CTRL 0x00000D60
-
-#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
-#else
-/* Intel Flash */
-#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x01FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00000D60
- /* Atmel Flash */
-#define CONFIG_SYS_CS1_BASE 0x04000000
-#define CONFIG_SYS_CS1_MASK 0x00070001
-#define CONFIG_SYS_CS1_CTRL 0x00001140
-
-#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
-#endif
-
-/* CPLD */
-#define CONFIG_SYS_CS2_BASE 0x08000000
-#define CONFIG_SYS_CS2_MASK 0x00070001
-#define CONFIG_SYS_CS2_CTRL 0x003f1140
-
-/* FPGA */
-#define CONFIG_SYS_CS3_BASE 0x09000000
-#define CONFIG_SYS_CS3_MASK 0x00070001
-#define CONFIG_SYS_CS3_CTRL 0x00000020
-
-#endif /* _M54455EVB_H */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 5af90d9..ad5616d 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -50,15 +50,6 @@
#define NANDARGS ""
#endif
-#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "setenv mmcdev " #instance"; "\
- "setenv bootpart " #instance":2 ; "\
- "run mmcboot\0"
-
-#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel "=" \
"run nandboot\0"
@@ -86,9 +77,7 @@
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
- func(LEGACY_MMC, legacy_mmc, 0) \
func(MMC, mmc, 1) \
- func(LEGACY_MMC, legacy_mmc, 1) \
func(NAND, nand, 0) \
BOOT_TARGET_USB(func) \
BOOT_TARGET_PXE(func) \
@@ -98,16 +87,11 @@
#ifndef CONFIG_SPL_BUILD
#include <environment/ti/dfu.h>
-#include <environment/ti/mmc.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
- DEFAULT_MMC_TI_ARGS \
- DEFAULT_FIT_TI_ARGS \
- "bootpart=0:2\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
"fdtfile=undefined\0" \
+ "finduuid=part uuid mmc 0:2 uuid\0" \
"console=ttyO0,115200n8\0" \
"partitions=" \
"uuid_disk=${uuid_gpt_disk};" \
diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h
index c34c07a..c161b93 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h
@@ -29,6 +29,7 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x80000000\0" \
"pxefile_addr_r=0x80100000\0" \
+ "tftp_load_addr=0x82000000\0" \
"kernel_addr_r=0x82000000\0" \
"fdt_addr_r=0x88000000\0" \
"ramdisk_addr_r=0x88080000\0" \
@@ -57,19 +58,20 @@
MEM_LAYOUT_ENV_SETTINGS \
BOOTENV \
GUARDIAN_DEFAULT_PROD_ENV \
+ "autoload=no\0" \
+ "backlight_brightness=50\0" \
"bootubivol=rootfs\0" \
"distro_bootcmd=" \
- "setenv autoload no; " \
"setenv rootflags \"bulk_read,chk_data_crc\"; " \
"setenv ethact usb_ether; " \
"if test \"${swi_status}\" -eq 1; then " \
- "setenv extrabootargs \"swi_attached\"; " \
"if dhcp; then " \
"sleep 1; " \
"if tftp \"${tftp_load_addr}\" \"bootscript.scr\"; then " \
"source \"${tftp_load_addr}\"; " \
"fi; " \
"fi; " \
+ "setenv extrabootargs $extrabootargs \"swi_attached\"; " \
"fi;" \
"run bootcmd_ubifs0;\0" \
"altbootcmd=" \
@@ -80,6 +82,17 @@
#endif /* ! CONFIG_SPL_BUILD */
+#define CONFIG_BMP_16BPP
+#define SPLASH_SCREEN_NAND_PART "nand0,10"
+#define SPLASH_SCREEN_BMP_FILE_SIZE 0x26000
+#define SPLASH_SCREEN_BMP_LOAD_ADDR 0x82000000
+#define SPLASH_SCREEN_TEXT "U-Boot"
+
+/* BGR 16Bit Color Definitions */
+#define CONSOLE_COLOR_BLACK 0x0000
+#define CONSOLE_COLOR_WHITE 0xFFFF
+#define CONSOLE_COLOR_RED 0x001F
+
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 6df6b49..a9ec1aa 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -108,59 +108,41 @@
#define DFUARGS
#endif
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel "=" \
+ "run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(NAND, nand, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
#ifndef CONFIG_SPL_BUILD
#include <environment/ti/dfu.h>
-#include <environment/ti/mmc.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
- DEFAULT_MMC_TI_ARGS \
- DEFAULT_FIT_TI_ARGS \
"fdtfile=undefined\0" \
- "bootpart=0:2\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
+ "finduuid=part uuid mmc 0:2 uuid\0" \
"console=ttyO0,115200n8\0" \
"partitions=" \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
"optargs=\0" \
- "usbroot=/dev/sda2 rw\0" \
- "usbrootfstype=ext4 rootwait\0" \
- "usbdev=0\0" \
"ramroot=/dev/ram0 rw\0" \
"ramrootfstype=ext2\0" \
- "usbargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${usbroot} " \
- "rootfstype=${usbrootfstype}\0" \
"ramargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${ramroot} " \
"rootfstype=${ramrootfstype}\0" \
"loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
- "usbboot=" \
- "setenv devnum ${usbdev}; " \
- "setenv devtype usb; " \
- "usb start ${usbdev}; " \
- "if usb dev ${usbdev}; then " \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadimage; then " \
- "run loadfdt; " \
- "echo Booting from usb ${usbdev}...; " \
- "run usbargs;" \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;" \
- "fi\0" \
- "fi;" \
- "usb stop ${usbdev};\0" \
"findfdt="\
"if test $board_name = AM43EPOS; then " \
"setenv fdtfile am43x-epos-evm.dtb; fi; " \
@@ -177,16 +159,7 @@
NANDARGS \
NETARGS \
DFUARGS \
-
-#define CONFIG_BOOTCOMMAND \
- "if test ${boot_fit} -eq 1; then " \
- "run update_to_fit;" \
- "fi;" \
- "run findfdt; " \
- "run envboot;" \
- "run mmcboot;" \
- "run usbboot;" \
- NANDBOOT \
+ BOOTENV
#endif
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 8c50fe9..d4514a0 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -10,7 +10,6 @@
#define __CONFIG_AM654_EVM_H
#include <linux/sizes.h>
-#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h>
#include <environment/ti/k3_rproc.h>
#include <environment/ti/k3_dfu.h>
@@ -126,6 +125,16 @@
DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_OSPI
+#ifdef CONFIG_TARGET_AM654_A53_EVM
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
@@ -136,7 +145,8 @@
EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \
EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \
EXTRA_ENV_RPROC_SETTINGS \
- EXTRA_ENV_DFUARGS
+ EXTRA_ENV_DFUARGS \
+ BOOTENV
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index c8e9d3b..2b61172 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -33,17 +33,6 @@
#define CONFIG_LBA48
#endif
-/* USB Configs */
-#ifdef CONFIG_USB
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
-#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_MASS_STORAGE
-#endif
-
/* Serial Flash */
#define CONFIG_LOADADDR 0x12000000
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index b707fc4..62da8ff 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -10,7 +10,6 @@
#define __CONFIG_J721E_EVM_H
#include <linux/sizes.h>
-#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h>
#include <environment/ti/k3_rproc.h>
#include <environment/ti/ufs.h>
@@ -160,6 +159,26 @@
#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD
#endif
+#if CONFIG_IS_ENABLED(CMD_PXE)
+# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ BOOT_TARGET_PXE(func) \
+ BOOT_TARGET_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
@@ -170,7 +189,8 @@
EXTRA_ENV_RPROC_SETTINGS \
EXTRA_ENV_DFUARGS \
DEFAULT_UFS_TI_ARGS \
- EXTRA_ENV_J721E_BOARD_SETTINGS_MTD
+ EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \
+ BOOTENV
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 15ea0e4..1338ee3 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -142,7 +142,7 @@
#endif
/* USB */
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
#define CONFIG_HAS_FSL_XHCI_USB
#ifndef CONFIG_TARGET_LX2162AQDS
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index fe991ea..7ef25ea 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -129,32 +129,22 @@
"scriptboot=echo Running ${mmcscriptfile} from mmc " \
"${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \
"kernboot=echo Booting ${mmckernfile} from mmc " \
- "${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \
+ "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} || " \
+ "bootz ${kernaddr}\0" \
"kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\
- "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \
+ "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr} || " \
+ "bootz ${kernaddr} ${initrdaddr}\0" \
"attachboot=echo Booting attached kernel image ...;" \
"setenv setup_omap_atag 1;" \
- "bootm ${attkernaddr};" \
+ "bootm ${attkernaddr} || bootz ${attkernaddr};" \
"setenv setup_omap_atag\0" \
- "trymmcscriptboot=if run switchmmc; then " \
- "if run scriptload; then " \
- "run scriptboot;" \
- "fi;" \
- "fi\0" \
- "trymmckernboot=if run switchmmc; then " \
- "if run kernload; then " \
- "run kernboot;" \
- "fi;" \
- "fi\0" \
- "trymmckerninitrdboot=if run switchmmc; then " \
- "if run initrdload; then " \
- "if run kernload; then " \
- "run kerninitrdboot;" \
- "fi;" \
- "fi; " \
- "fi\0" \
+ "trymmcscriptboot=run switchmmc && run scriptload && run scriptboot\0" \
+ "trymmckernboot=run switchmmc && run kernload && run kernboot\0" \
+ "trymmckerninitrdboot=run switchmmc && run initrdload && " \
+ "run kernload && run kerninitrdboot\0" \
"trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \
- "setenv mmckernfile uImage; run trymmckernboot\0" \
+ "setenv mmckernfile uImage; run trymmckernboot;" \
+ "setenv mmckernfile zImage; run trymmckernboot\0" \
"trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \
"setenv mmcpart 2; run trymmcpartboot;" \
"setenv mmcpart 3; run trymmcpartboot;" \
@@ -167,15 +157,11 @@
"fi\0" \
"emmcboot=setenv mmcnum 1; run trymmcboot\0" \
"sdboot=setenv mmcnum 0; run trymmcboot\0" \
- "preboot=setenv mmcnum 1; setenv mmcpart 1;" \
- "setenv mmcscriptfile bootmenu.scr;" \
- "if run switchmmc; then " \
- "setenv mmctype fat;" \
- "if run scriptload; then run scriptboot; else " \
- "setenv mmctype ext4;" \
- "if run scriptload; then run scriptboot; fi;" \
- "fi;" \
- "fi;" \
+ "trymmcbootmenu=setenv mmctype fat && run trymmcscriptboot || " \
+ "setenv mmctype ext4 && run trymmcscriptboot\0" \
+ "preboot=setenv mmcpart 1; setenv mmcscriptfile bootmenu.scr;" \
+ "setenv mmcnum 0 && run trymmcbootmenu || " \
+ "setenv mmcnum 1 && run trymmcbootmenu;" \
"if run slide; then true; else " \
"setenv bootmenu_delay 0;" \
"setenv bootdelay 0;" \
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index 2e7f49e..b372838 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -101,7 +101,7 @@
#define BOOT_TARGET_UBIFS(func)
#endif
-#ifdef CONFIG_USB
+#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_USB(func) func(USB, usb, 0)
#else
#define BOOT_TARGET_USB(func)
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index fae0e76..dd7a75a 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -21,11 +21,18 @@
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
#ifndef CONFIG_SPL_BUILD
+
+#if CONFIG_IS_ENABLED(CMD_USB)
+# define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+# define BOOT_TARGET_USB(func)
+#endif
+
#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
- func(USB, usb, 0) \
+ BOOT_TARGET_USB(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#endif
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 1e31622..d0eddcc 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -51,12 +51,6 @@
#define CONFIG_TWL6030_POWER 1
#endif
-/* USB */
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-
/*
* Environment setup
*/
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index de0a6af..055d108 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -32,6 +32,8 @@
#define CONFIG_PALMAS_POWER
+#include <linux/stringify.h>
+
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
@@ -54,10 +56,233 @@
#define DFUARGS
#endif
-#include <environment/ti/boot.h>
#include <environment/ti/mmc.h>
#include <environment/ti/nand.h>
+#ifndef CONSOLEDEV
+#define CONSOLEDEV "ttyS2"
+#endif
+
+#ifndef PARTS_DEFAULT
+/*
+ * Default GPT tables for eMMC (Linux and Android). Notes:
+ * 1. Keep partitions aligned to erase group size (512 KiB) when possible
+ * 2. Keep partitions in sync with DFU_ALT_INFO_EMMC (see dfu.h)
+ * 3. Keep 'bootloader' partition (U-Boot proper) start address in sync with
+ * CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (see common/spl/Kconfig)
+ */
+#define PARTS_DEFAULT \
+ /* Linux partitions */ \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};" \
+ "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ /* Android partitions */ \
+ "partitions_android=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
+ "name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \
+ "name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \
+ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
+ "name=boot_a,size=20M,uuid=${uuid_gpt_boot_a};" \
+ "name=boot_b,size=20M,uuid=${uuid_gpt_boot_b};" \
+ "name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a};" \
+ "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \
+ "name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a};" \
+ "name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b};" \
+ "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \
+ "name=super,size=2560M,uuid=${uuid_gpt_super};" \
+ "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
+ "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
+#endif /* PARTS_DEFAULT */
+
+#if defined(CONFIG_CMD_AVB)
+#define AVB_VERIFY_CHECK "if run avb_verify; then " \
+ "echo AVB verification OK.;" \
+ "set bootargs $bootargs $avb_bootargs;" \
+ "else " \
+ "echo AVB verification failed.;" \
+ "exit; fi;"
+#define AVB_VERIFY_CMD "avb_verify=avb init 1; avb verify $slot_suffix;\0"
+#else
+#define AVB_VERIFY_CHECK ""
+#define AVB_VERIFY_CMD ""
+#endif
+
+#define CONTROL_PARTITION "misc"
+
+#if defined(CONFIG_CMD_AB_SELECT)
+#define AB_SELECT_SLOT \
+ "if part number mmc 1 " CONTROL_PARTITION " control_part_number; " \
+ "then " \
+ "echo " CONTROL_PARTITION \
+ " partition number:${control_part_number};" \
+ "ab_select slot_name mmc ${mmcdev}:${control_part_number};" \
+ "else " \
+ "echo " CONTROL_PARTITION " partition not found;" \
+ "exit;" \
+ "fi;" \
+ "setenv slot_suffix _${slot_name};"
+#define AB_SELECT_ARGS \
+ "setenv bootargs_ab androidboot.slot_suffix=${slot_suffix}; " \
+ "echo A/B cmdline addition: ${bootargs_ab};" \
+ "setenv bootargs ${bootargs} ${bootargs_ab};"
+#else
+#define AB_SELECT_SLOT ""
+#define AB_SELECT_ARGS ""
+#endif
+
+/*
+ * Prepares complete device tree blob for current board (for Android boot).
+ *
+ * Boot image or recovery image should be loaded into $loadaddr prior to running
+ * these commands. The logic of these commnads is next:
+ *
+ * 1. Read correct DTB for current SoC/board from boot image in $loadaddr
+ * to $fdtaddr
+ * 2. Merge all needed DTBO for current board from 'dtbo' partition into read
+ * DTB
+ * 3. User should provide $fdtaddr as 3rd argument to 'bootm'
+ */
+#define PREPARE_FDT \
+ "echo Preparing FDT...; " \
+ "if test $board_name = am57xx_evm_reva3; then " \
+ "echo \" Reading DTBO partition...\"; " \
+ "part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; " \
+ "part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; " \
+ "mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; " \
+ "echo \" Reading DTB for AM57x EVM RevA3...\"; " \
+ "abootimg get dtb --index=0 dtb_start dtb_size; " \
+ "cp.b $dtb_start $fdtaddr $dtb_size; " \
+ "fdt addr $fdtaddr 0x80000; " \
+ "echo \" Applying DTBOs for AM57x EVM RevA3...\"; " \
+ "adtimg addr $dtboaddr; " \
+ "adtimg get dt --index=0 dtbo0_addr dtbo0_size; " \
+ "fdt apply $dtbo0_addr; " \
+ "adtimg get dt --index=1 dtbo1_addr dtbo1_size; " \
+ "fdt apply $dtbo1_addr; " \
+ "elif test $board_name = beagle_x15_revc; then " \
+ "echo \" Reading DTB for Beagle X15 RevC...\"; " \
+ "abootimg get dtb --index=0 dtb_start dtb_size; " \
+ "cp.b $dtb_start $fdtaddr $dtb_size; " \
+ "fdt addr $fdtaddr 0x80000; " \
+ "else " \
+ "echo Error: Android boot is not supported for $board_name; " \
+ "exit; " \
+ "fi; " \
+
+#define FASTBOOT_CMD \
+ "echo Booting into fastboot ...; " \
+ "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; "
+
+#define DEFAULT_COMMON_BOOT_TI_ARGS \
+ "console=" CONSOLEDEV ",115200n8\0" \
+ "fdtfile=undefined\0" \
+ "finduuid=part uuid mmc 0:2 uuid\0" \
+ "usbtty=cdc_acm\0" \
+ "vram=16M\0" \
+ AVB_VERIFY_CMD \
+ "partitions=" PARTS_DEFAULT "\0" \
+ "optargs=\0" \
+ "dofastboot=0\0" \
+ "emmc_android_boot=" \
+ "setenv mmcdev 1; " \
+ "mmc dev $mmcdev; " \
+ "mmc rescan; " \
+ AB_SELECT_SLOT \
+ "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \
+ CONTROL_PARTITION "; then " \
+ "setenv ardaddr -; " \
+ "if bcb test command = bootonce-bootloader; then " \
+ "echo Android: Bootloader boot...; " \
+ "bcb clear command; bcb store; " \
+ FASTBOOT_CMD \
+ "exit; " \
+ "elif bcb test command = boot-recovery; then " \
+ "echo Android: Recovery boot...; " \
+ "setenv ardaddr $loadaddr;" \
+ "setenv apart recovery; " \
+ "else " \
+ "echo Android: Normal boot...; " \
+ "setenv ardaddr $loadaddr; " \
+ "setenv apart boot${slot_suffix}; " \
+ "fi; " \
+ "else " \
+ "echo Warning: BCB is corrupted or does not exist; " \
+ "echo Android: Normal boot...; " \
+ "fi; " \
+ "setenv eval_bootargs setenv bootargs $bootargs; " \
+ "run eval_bootargs; " \
+ "setenv machid fe6; " \
+ AVB_VERIFY_CHECK \
+ AB_SELECT_ARGS \
+ "if part start mmc $mmcdev $apart boot_start; then " \
+ "part size mmc $mmcdev $apart boot_size; " \
+ "mmc read $loadaddr $boot_start $boot_size; " \
+ PREPARE_FDT \
+ "bootm $loadaddr $ardaddr $fdtaddr; " \
+ "else " \
+ "echo $apart partition not found; " \
+ "exit; " \
+ "fi;\0"
+
+#define DEFAULT_FDT_TI_ARGS \
+ "findfdt="\
+ "if test $board_name = omap5_uevm; then " \
+ "setenv fdtfile omap5-uevm.dtb; fi; " \
+ "if test $board_name = dra7xx; then " \
+ "setenv fdtfile dra7-evm.dtb; fi;" \
+ "if test $board_name = dra72x-revc; then " \
+ "setenv fdtfile dra72-evm-revc.dtb; fi;" \
+ "if test $board_name = dra72x; then " \
+ "setenv fdtfile dra72-evm.dtb; fi;" \
+ "if test $board_name = dra71x; then " \
+ "setenv fdtfile dra71-evm.dtb; fi;" \
+ "if test $board_name = dra76x_acd; then " \
+ "setenv fdtfile dra76-evm.dtb; fi;" \
+ "if test $board_name = beagle_x15; then " \
+ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = beagle_x15_revb1; then " \
+ "setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \
+ "if test $board_name = beagle_x15_revc; then " \
+ "setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \
+ "if test $board_name = am5729_beagleboneai; then " \
+ "setenv fdtfile am5729-beagleboneai.dtb; fi;" \
+ "if test $board_name = am572x_idk; then " \
+ "setenv fdtfile am572x-idk.dtb; fi;" \
+ "if test $board_name = am574x_idk; then " \
+ "setenv fdtfile am574x-idk.dtb; fi;" \
+ "if test $board_name = am57xx_evm; then " \
+ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = am57xx_evm_reva3; then " \
+ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = am571x_idk; then " \
+ "setenv fdtfile am571x-idk.dtb; fi;" \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0"
+
+#define CONFIG_BOOTCOMMAND \
+ "if test ${dofastboot} -eq 1; then " \
+ "echo Boot fastboot requested, resetting dofastboot ...;" \
+ "setenv dofastboot 0; saveenv;" \
+ FASTBOOT_CMD \
+ "fi;" \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
+ "run findfdt; " \
+ "run finduuid; " \
+ "run distro_bootcmd;" \
+ "run emmc_android_boot; " \
+ ""
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
@@ -67,6 +292,7 @@
DFUARGS \
NETARGS \
NANDARGS \
+ BOOTENV
/*
* SPL related defines. The Public RAM memory map the ROM defines the
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index c12cd7c..b668817 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -34,7 +34,7 @@
/* Setup proper boot sequences for Miami boards */
-#if defined(CONFIG_USB)
+#if defined(CONFIG_USB_HOST)
# define EXTRA_ENV_USB \
"usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
"i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
deleted file mode 100644
index a9d8f28..0000000
--- a/include/environment/ti/boot.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Boot related environment variable definitions on TI boards.
- *
- * (C) Copyright 2017 Linaro Ltd.
- * Sam Protsenko <semen.protsenko@linaro.org>
- */
-
-#ifndef __TI_BOOT_H
-#define __TI_BOOT_H
-
-#include <linux/stringify.h>
-
-#ifndef CONSOLEDEV
-#define CONSOLEDEV "ttyS2"
-#endif
-
-#ifndef PARTS_DEFAULT
-/*
- * Default GPT tables for eMMC (Linux and Android). Notes:
- * 1. Keep partitions aligned to erase group size (512 KiB) when possible
- * 2. Keep partitions in sync with DFU_ALT_INFO_EMMC (see dfu.h)
- * 3. Keep 'bootloader' partition (U-Boot proper) start address in sync with
- * CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (see common/spl/Kconfig)
- */
-#define PARTS_DEFAULT \
- /* Linux partitions */ \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};" \
- "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \
- /* Android partitions */ \
- "partitions_android=" \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
- "name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \
- "name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \
- "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
- "name=boot_a,size=20M,uuid=${uuid_gpt_boot_a};" \
- "name=boot_b,size=20M,uuid=${uuid_gpt_boot_b};" \
- "name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a};" \
- "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \
- "name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a};" \
- "name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b};" \
- "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \
- "name=super,size=2560M,uuid=${uuid_gpt_super};" \
- "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
- "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
-#endif /* PARTS_DEFAULT */
-
-#if defined(CONFIG_CMD_AVB)
-#define AVB_VERIFY_CHECK "if run avb_verify; then " \
- "echo AVB verification OK.;" \
- "set bootargs $bootargs $avb_bootargs;" \
- "else " \
- "echo AVB verification failed.;" \
- "exit; fi;"
-#define AVB_VERIFY_CMD "avb_verify=avb init 1; avb verify $slot_suffix;\0"
-#else
-#define AVB_VERIFY_CHECK ""
-#define AVB_VERIFY_CMD ""
-#endif
-
-#define CONTROL_PARTITION "misc"
-
-#if defined(CONFIG_CMD_AB_SELECT)
-#define AB_SELECT_SLOT \
- "if part number mmc 1 " CONTROL_PARTITION " control_part_number; " \
- "then " \
- "echo " CONTROL_PARTITION \
- " partition number:${control_part_number};" \
- "ab_select slot_name mmc ${mmcdev}:${control_part_number};" \
- "else " \
- "echo " CONTROL_PARTITION " partition not found;" \
- "exit;" \
- "fi;" \
- "setenv slot_suffix _${slot_name};"
-#define AB_SELECT_ARGS \
- "setenv bootargs_ab androidboot.slot_suffix=${slot_suffix}; " \
- "echo A/B cmdline addition: ${bootargs_ab};" \
- "setenv bootargs ${bootargs} ${bootargs_ab};"
-#else
-#define AB_SELECT_SLOT ""
-#define AB_SELECT_ARGS ""
-#endif
-
-/*
- * Prepares complete device tree blob for current board (for Android boot).
- *
- * Boot image or recovery image should be loaded into $loadaddr prior to running
- * these commands. The logic of these commnads is next:
- *
- * 1. Read correct DTB for current SoC/board from boot image in $loadaddr
- * to $fdtaddr
- * 2. Merge all needed DTBO for current board from 'dtbo' partition into read
- * DTB
- * 3. User should provide $fdtaddr as 3rd argument to 'bootm'
- */
-#define PREPARE_FDT \
- "echo Preparing FDT...; " \
- "if test $board_name = am57xx_evm_reva3; then " \
- "echo \" Reading DTBO partition...\"; " \
- "part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; " \
- "part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; " \
- "mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; " \
- "echo \" Reading DTB for AM57x EVM RevA3...\"; " \
- "abootimg get dtb --index=0 dtb_start dtb_size; " \
- "cp.b $dtb_start $fdtaddr $dtb_size; " \
- "fdt addr $fdtaddr 0x80000; " \
- "echo \" Applying DTBOs for AM57x EVM RevA3...\"; " \
- "adtimg addr $dtboaddr; " \
- "adtimg get dt --index=0 dtbo0_addr dtbo0_size; " \
- "fdt apply $dtbo0_addr; " \
- "adtimg get dt --index=1 dtbo1_addr dtbo1_size; " \
- "fdt apply $dtbo1_addr; " \
- "elif test $board_name = beagle_x15_revc; then " \
- "echo \" Reading DTB for Beagle X15 RevC...\"; " \
- "abootimg get dtb --index=0 dtb_start dtb_size; " \
- "cp.b $dtb_start $fdtaddr $dtb_size; " \
- "fdt addr $fdtaddr 0x80000; " \
- "else " \
- "echo Error: Android boot is not supported for $board_name; " \
- "exit; " \
- "fi; " \
-
-#define FASTBOOT_CMD \
- "echo Booting into fastboot ...; " \
- "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; "
-
-#define DEFAULT_COMMON_BOOT_TI_ARGS \
- "console=" CONSOLEDEV ",115200n8\0" \
- "fdtfile=undefined\0" \
- "bootpart=0:2\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
- "usbtty=cdc_acm\0" \
- "vram=16M\0" \
- AVB_VERIFY_CMD \
- "partitions=" PARTS_DEFAULT "\0" \
- "optargs=\0" \
- "dofastboot=0\0" \
- "emmc_linux_boot=" \
- "echo Trying to boot Linux from eMMC ...; " \
- "setenv mmcdev 1; " \
- "setenv bootpart 1:2; " \
- "setenv mmcroot /dev/mmcblk0p2 rw; " \
- "run mmcboot;\0" \
- "emmc_android_boot=" \
- "setenv mmcdev 1; " \
- "mmc dev $mmcdev; " \
- "mmc rescan; " \
- AB_SELECT_SLOT \
- "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \
- CONTROL_PARTITION "; then " \
- "setenv ardaddr -; " \
- "if bcb test command = bootonce-bootloader; then " \
- "echo Android: Bootloader boot...; " \
- "bcb clear command; bcb store; " \
- FASTBOOT_CMD \
- "exit; " \
- "elif bcb test command = boot-recovery; then " \
- "echo Android: Recovery boot...; " \
- "setenv ardaddr $loadaddr;" \
- "setenv apart recovery; " \
- "else " \
- "echo Android: Normal boot...; " \
- "setenv ardaddr $loadaddr; " \
- "setenv apart boot${slot_suffix}; " \
- "fi; " \
- "else " \
- "echo Warning: BCB is corrupted or does not exist; " \
- "echo Android: Normal boot...; " \
- "fi; " \
- "setenv eval_bootargs setenv bootargs $bootargs; " \
- "run eval_bootargs; " \
- "setenv machid fe6; " \
- AVB_VERIFY_CHECK \
- AB_SELECT_ARGS \
- "if part start mmc $mmcdev $apart boot_start; then " \
- "part size mmc $mmcdev $apart boot_size; " \
- "mmc read $loadaddr $boot_start $boot_size; " \
- PREPARE_FDT \
- "bootm $loadaddr $ardaddr $fdtaddr; " \
- "else " \
- "echo $apart partition not found; " \
- "exit; " \
- "fi;\0"
-
-#ifdef CONFIG_OMAP54XX
-
-#define DEFAULT_FDT_TI_ARGS \
- "findfdt="\
- "if test $board_name = omap5_uevm; then " \
- "setenv fdtfile omap5-uevm.dtb; fi; " \
- "if test $board_name = dra7xx; then " \
- "setenv fdtfile dra7-evm.dtb; fi;" \
- "if test $board_name = dra72x-revc; then " \
- "setenv fdtfile dra72-evm-revc.dtb; fi;" \
- "if test $board_name = dra72x; then " \
- "setenv fdtfile dra72-evm.dtb; fi;" \
- "if test $board_name = dra71x; then " \
- "setenv fdtfile dra71-evm.dtb; fi;" \
- "if test $board_name = dra76x_acd; then " \
- "setenv fdtfile dra76-evm.dtb; fi;" \
- "if test $board_name = beagle_x15; then " \
- "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
- "if test $board_name = beagle_x15_revb1; then " \
- "setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \
- "if test $board_name = beagle_x15_revc; then " \
- "setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \
- "if test $board_name = am5729_beagleboneai; then " \
- "setenv fdtfile am5729-beagleboneai.dtb; fi;" \
- "if test $board_name = am572x_idk; then " \
- "setenv fdtfile am572x-idk.dtb; fi;" \
- "if test $board_name = am574x_idk; then " \
- "setenv fdtfile am574x-idk.dtb; fi;" \
- "if test $board_name = am57xx_evm; then " \
- "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
- "if test $board_name = am57xx_evm_reva3; then " \
- "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
- "if test $board_name = am571x_idk; then " \
- "setenv fdtfile am571x-idk.dtb; fi;" \
- "if test $fdtfile = undefined; then " \
- "echo WARNING: Could not determine device tree to use; fi; \0"
-
-#define CONFIG_BOOTCOMMAND \
- "if test ${dofastboot} -eq 1; then " \
- "echo Boot fastboot requested, resetting dofastboot ...;" \
- "setenv dofastboot 0; saveenv;" \
- FASTBOOT_CMD \
- "fi;" \
- "if test ${boot_fit} -eq 1; then " \
- "run update_to_fit;" \
- "fi;" \
- "run findfdt; " \
- "run envboot; " \
- "run mmcboot;" \
- "run emmc_linux_boot; " \
- "run emmc_android_boot; " \
- ""
-
-#endif /* CONFIG_OMAP54XX */
-
-#endif /* __TI_BOOT_H */
diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h
new file mode 100644
index 0000000..25272e8
--- /dev/null
+++ b/include/linux/pruss_driver.h
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __TI_PRUSS_H
+#define __TI_PRUSS_H
+
+/*
+ * PRU_ICSS_CFG registers
+ * SYSCFG, ISRP, ISP, IESP, IECP, SCRP applicable on AMxxxx devices only
+ */
+#define PRUSS_CFG_REVID 0x00
+#define PRUSS_CFG_SYSCFG 0x04
+#define PRUSS_CFG_GPCFG(x) (0x08 + (x) * 4)
+#define PRUSS_CFG_CGR 0x10
+#define PRUSS_CFG_ISRP 0x14
+#define PRUSS_CFG_ISP 0x18
+#define PRUSS_CFG_IESP 0x1C
+#define PRUSS_CFG_IECP 0x20
+#define PRUSS_CFG_SCRP 0x24
+#define PRUSS_CFG_PMAO 0x28
+#define PRUSS_CFG_MII_RT 0x2C
+#define PRUSS_CFG_IEPCLK 0x30
+#define PRUSS_CFG_SPP 0x34
+#define PRUSS_CFG_PIN_MX 0x40
+
+/* PRUSS_GPCFG register bits */
+#define PRUSS_GPCFG_PRU_GPO_SH_SEL BIT(25)
+
+#define PRUSS_GPCFG_PRU_DIV1_SHIFT 20
+#define PRUSS_GPCFG_PRU_DIV1_MASK GENMASK(24, 20)
+
+#define PRUSS_GPCFG_PRU_DIV0_SHIFT 15
+#define PRUSS_GPCFG_PRU_DIV0_MASK GENMASK(15, 19)
+
+#define PRUSS_GPCFG_PRU_GPO_MODE BIT(14)
+#define PRUSS_GPCFG_PRU_GPO_MODE_DIRECT 0
+#define PRUSS_GPCFG_PRU_GPO_MODE_SERIAL BIT(14)
+
+#define PRUSS_GPCFG_PRU_GPI_SB BIT(13)
+
+#define PRUSS_GPCFG_PRU_GPI_DIV1_SHIFT 8
+#define PRUSS_GPCFG_PRU_GPI_DIV1_MASK GENMASK(12, 8)
+
+#define PRUSS_GPCFG_PRU_GPI_DIV0_SHIFT 3
+#define PRUSS_GPCFG_PRU_GPI_DIV0_MASK GENMASK(7, 3)
+
+#define PRUSS_GPCFG_PRU_GPI_CLK_MODE_POSITIVE 0
+#define PRUSS_GPCFG_PRU_GPI_CLK_MODE_NEGATIVE BIT(2)
+#define PRUSS_GPCFG_PRU_GPI_CLK_MODE BIT(2)
+
+#define PRUSS_GPCFG_PRU_GPI_MODE_MASK GENMASK(1, 0)
+#define PRUSS_GPCFG_PRU_GPI_MODE_SHIFT 0
+
+#define PRUSS_GPCFG_PRU_MUX_SEL_SHIFT 26
+#define PRUSS_GPCFG_PRU_MUX_SEL_MASK GENMASK(29, 26)
+
+/* PRUSS_MII_RT register bits */
+#define PRUSS_MII_RT_EVENT_EN BIT(0)
+
+/* PRUSS_SPP register bits */
+#define PRUSS_SPP_PRU1_PAD_HP_EN BIT(0)
+#define PRUSS_SPP_XFER_SHIFT_EN BIT(1)
+#define PRUSS_SPP_XFR_BYTE_SHIFT_EN BIT(2)
+#define PRUSS_SPP_RTU_XFR_SHIFT_EN BIT(3)
+
+/**
+ * enum pruss_gp_mux_sel - PRUSS GPI/O Mux modes for the
+ * PRUSS_GPCFG0/1 registers
+ *
+ * NOTE: The below defines are the most common values, but there
+ * are some exceptions like on 66AK2G, where the RESERVED and MII2
+ * values are interchanged. Also, this bit-field does not exist on
+ * AM335x SoCs
+ */
+enum pruss_gp_mux_sel {
+ PRUSS_GP_MUX_SEL_GP = 0,
+ PRUSS_GP_MUX_SEL_ENDAT,
+ PRUSS_GP_MUX_SEL_RESERVED,
+ PRUSS_GP_MUX_SEL_SD,
+ PRUSS_GP_MUX_SEL_MII2,
+ PRUSS_GP_MUX_SEL_MAX,
+};
+
+/**
+ * enum pruss_gpi_mode - PRUSS GPI configuration modes, used
+ * to program the PRUSS_GPCFG0/1 registers
+ */
+enum pruss_gpi_mode {
+ PRUSS_GPI_MODE_DIRECT = 0,
+ PRUSS_GPI_MODE_PARALLEL,
+ PRUSS_GPI_MODE_28BIT_SHIFT,
+ PRUSS_GPI_MODE_MII,
+};
+
+/**
+ * enum pruss_pru_id - PRU core identifiers
+ */
+enum pruss_pru_id {
+ PRUSS_PRU0 = 0,
+ PRUSS_PRU1,
+ PRUSS_NUM_PRUS,
+};
+
+/**
+ * enum pru_ctable_idx - Configurable Constant table index identifiers
+ */
+enum pru_ctable_idx {
+ PRU_C24 = 0,
+ PRU_C25,
+ PRU_C26,
+ PRU_C27,
+ PRU_C28,
+ PRU_C29,
+ PRU_C30,
+ PRU_C31,
+};
+
+/**
+ * enum pruss_mem - PRUSS memory range identifiers
+ */
+enum pruss_mem {
+ PRUSS_MEM_DRAM0 = 0,
+ PRUSS_MEM_DRAM1,
+ PRUSS_MEM_SHRD_RAM2,
+ PRUSS_MEM_MAX,
+};
+
+/**
+ * struct pruss_mem_region - PRUSS memory region structure
+ * @va: kernel virtual address of the PRUSS memory region
+ * @pa: physical (bus) address of the PRUSS memory region
+ * @size: size of the PRUSS memory region
+ */
+struct pruss_mem_region {
+ void __iomem *va;
+ phys_addr_t pa;
+ size_t size;
+};
+
+/**
+ * struct pruss - PRUSS parent structure
+ * @dev: pruss device pointer
+ * @cfg: regmap for config region
+ * @mem_regions: data for each of the PRUSS memory regions
+ * @mem_in_use: to indicate if memory resource is in use
+ */
+struct pruss {
+ struct udevice *dev;
+ struct regmap *cfg;
+ struct pruss_mem_region mem_regions[PRUSS_MEM_MAX];
+ struct pruss_mem_region *mem_in_use[PRUSS_MEM_MAX];
+};
+
+int pruss_request_tm_region(struct udevice *dev, phys_addr_t *loc);
+int pruss_request_mem_region(struct udevice *dev, enum pruss_mem mem_id,
+ struct pruss_mem_region *region);
+int pruss_release_mem_region(struct udevice *dev, struct pruss_mem_region *region);
+int pruss_cfg_update(struct udevice *dev, unsigned int reg,
+ unsigned int mask, unsigned int val);
+
+/**
+ * pruss_cfg_gpimode() - set the GPI mode of the PRU
+ * @dev: the pruss device
+ * @pru_id: the rproc instance handle of the PRU
+ * @mode: GPI mode to set
+ *
+ * Sets the GPI mode for a given PRU by programming the
+ * corresponding PRUSS_CFG_GPCFGx register
+ *
+ * Returns 0 on success, or an error code otherwise
+ */
+static inline int pruss_cfg_gpimode(struct udevice *dev, enum pruss_pru_id id,
+ enum pruss_gpi_mode mode)
+{
+ if (id < 0)
+ return -EINVAL;
+
+ return pruss_cfg_update(dev, PRUSS_CFG_GPCFG(id),
+ PRUSS_GPCFG_PRU_GPI_MODE_MASK,
+ mode << PRUSS_GPCFG_PRU_GPI_MODE_SHIFT);
+}
+
+/**
+ * pruss_cfg_miirt_enable() - Enable/disable MII RT Events
+ * @dev: the pruss device
+ * @enable: enable/disable
+ *
+ * Enable/disable the MII RT Events for the PRUSS.
+ */
+static inline int pruss_cfg_miirt_enable(struct udevice *dev, bool enable)
+{
+ u32 set = enable ? PRUSS_MII_RT_EVENT_EN : 0;
+
+ return pruss_cfg_update(dev, PRUSS_CFG_MII_RT,
+ PRUSS_MII_RT_EVENT_EN, set);
+}
+
+/**
+ * pruss_cfg_xfr_enable() - Enable/disable XIN XOUT shift functionality
+ * @dev: the pruss device
+ * @enable: enable/disable
+ */
+static inline int pruss_cfg_xfr_enable(struct udevice *dev, bool enable)
+{
+ u32 set = enable ? PRUSS_SPP_XFER_SHIFT_EN : 0;
+
+ return pruss_cfg_update(dev, PRUSS_CFG_SPP,
+ PRUSS_SPP_XFER_SHIFT_EN, set);
+}
+
+/**
+ * pruss_cfg_set_gpmux() - set the GPMUX value for a PRU device
+ * @pruss: pruss device
+ * @pru_id: PRU identifier (0-1)
+ * @mux: new mux value for PRU
+ */
+static inline int pruss_cfg_set_gpmux(struct udevice *dev,
+ enum pruss_pru_id id, u8 mux)
+{
+ if (mux >= PRUSS_GP_MUX_SEL_MAX)
+ return -EINVAL;
+
+ return pruss_cfg_update(dev, PRUSS_CFG_GPCFG(id),
+ PRUSS_GPCFG_PRU_MUX_SEL_MASK,
+ (u32)mux << PRUSS_GPCFG_PRU_MUX_SEL_SHIFT);
+}
+
+#endif /* __TI_PRUSS_H */
diff --git a/include/power/tps65941.h b/include/power/tps65941.h
index 2d48b31..a2bc681 100644
--- a/include/power/tps65941.h
+++ b/include/power/tps65941.h
@@ -2,6 +2,7 @@
#define TPS659412 0x1
#define TPS659413 0x2
#define TPS659414 0x3
+#define LP876441 0x4
/* I2C device address for pmic tps65941 */
#define TPS65941_I2C_ADDR (0x12 >> 1)
diff --git a/test/nokia_rx51_test.sh b/test/nokia_rx51_test.sh
index ff840c1..28aa554 100755
--- a/test/nokia_rx51_test.sh
+++ b/test/nokia_rx51_test.sh
@@ -18,6 +18,7 @@
mformat (from mtools, homepage http://www.gnu.org/software/mtools/)
/usr/sbin/mkfs.ubifs (from mtd-utils, homepage http://www.linux-mtd.infradead.org/)
/usr/sbin/ubinize (from mtd-utils, homepage http://www.linux-mtd.infradead.org/)
+ /lib/ld-linux.so.2 (32-bit x86 version of LD loader, needed for qflasher)
' | while read tool info; do
if test -z "$tool"; then continue; fi
if ! which $tool 1>/dev/null 2>&1; then
@@ -159,7 +160,7 @@
EOF
./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_uboot -d bootmenu_uboot bootmenu_uboot.scr
-# Generate bootmenu for eMMC booting
+# Generate bootmenu for eMMC booting (uImage)
cat > bootmenu_emmc << EOF
setenv bootmenu_0 'uImage-2.6.28-omap1 from eMMC=setenv mmcnum 1; setenv mmcpart 1; setenv mmctype fat; setenv bootargs; setenv setup_omap_atag 1; setenv mmckernfile uImage-2.6.28-omap1; run trymmckernboot';
setenv bootmenu_1;
@@ -168,6 +169,15 @@
EOF
./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_emmc -d bootmenu_emmc bootmenu_emmc.scr
+# Generate bootmenu for eMMC booting (zImage)
+cat > bootmenu_emmc2 << EOF
+setenv bootmenu_0 'zImage-2.6.28-omap1 from eMMC=setenv mmcnum 1; setenv mmcpart 1; setenv mmctype fat; setenv bootargs; setenv setup_omap_atag 1; setenv mmckernfile zImage-2.6.28-omap1; run trymmckernboot';
+setenv bootmenu_1;
+setenv bootmenu_delay 1;
+setenv bootdelay 1;
+EOF
+./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_emmc2 -d bootmenu_emmc2 bootmenu_emmc2.scr
+
# Generate bootmenu for OneNAND booting
cat > bootmenu_nand << EOF
setenv bootmenu_0 'uImage-2.6.28-omap1 from OneNAND=mtd read initfs \${kernaddr}; setenv bootargs; setenv setup_omap_atag 1; bootm \${kernaddr}';
@@ -177,10 +187,18 @@
EOF
./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_nand -d bootmenu_nand bootmenu_nand.scr
+# Generate bootmenu for default booting
+cat > bootmenu_default << EOF
+setenv bootmenu_delay 1;
+setenv bootdelay 1;
+EOF
+./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_default -d bootmenu_default bootmenu_default.scr
+
# Generate combined image from u-boot and Maemo fiasco kernel
dd if=kernel_2.6.28/boot/zImage-2.6.28-20103103+0m5.fiasco of=zImage-2.6.28-omap1 skip=95 bs=1
+./u-boot-gen-combined u-boot.bin zImage-2.6.28-omap1 combined_zimage.bin
./mkimage -A arm -O linux -T kernel -C none -a 80008000 -e 80008000 -n zImage-2.6.28-omap1 -d zImage-2.6.28-omap1 uImage-2.6.28-omap1
-./u-boot-gen-combined u-boot.bin uImage-2.6.28-omap1 combined.bin
+./u-boot-gen-combined u-boot.bin uImage-2.6.28-omap1 combined_uimage.bin
# Generate combined hack image from u-boot and Maemo fiasco kernel (kernel starts at 2MB offset and qflasher puts 2kB header before supplied image)
cp u-boot.bin combined_hack.bin
@@ -191,24 +209,37 @@
mformat -m 0xf8 -F -h 4 -s 16 -c 1 -t $((50*1024*1024/(4*16*512))) :: -i emmc_uboot.img
mcopy bootmenu_uboot.scr ::/bootmenu.scr -i emmc_uboot.img
-# Generate FAT32 eMMC image for eMMC booting
+# Generate FAT32 eMMC image for eMMC booting (uImage)
truncate -s 50MiB emmc_emmc.img
mformat -m 0xf8 -F -h 4 -s 16 -c 1 -t $((50*1024*1024/(4*16*512))) :: -i emmc_emmc.img
mcopy uImage-2.6.28-omap1 ::/uImage-2.6.28-omap1 -i emmc_emmc.img
mcopy bootmenu_emmc.scr ::/bootmenu.scr -i emmc_emmc.img
+# Generate FAT32 eMMC image for eMMC booting (zImage)
+truncate -s 50MiB emmc_emmc2.img
+mformat -m 0xf8 -F -h 4 -s 16 -c 1 -t $((50*1024*1024/(4*16*512))) :: -i emmc_emmc2.img
+mcopy zImage-2.6.28-omap1 ::/zImage-2.6.28-omap1 -i emmc_emmc2.img
+mcopy bootmenu_emmc2.scr ::/bootmenu.scr -i emmc_emmc2.img
+
# Generate FAT32 eMMC image for OneNAND booting
truncate -s 50MiB emmc_nand.img
mformat -m 0xf8 -F -h 4 -s 16 -c 1 -t $((50*1024*1024/(4*16*512))) :: -i emmc_nand.img
mcopy bootmenu_nand.scr ::/bootmenu.scr -i emmc_nand.img
+# Generate FAT32 eMMC image for default booting
+truncate -s 50MiB emmc_default.img
+mformat -m 0xf8 -F -h 4 -s 16 -c 1 -t $((50*1024*1024/(4*16*512))) :: -i emmc_default.img
+mcopy bootmenu_default.scr ::/bootmenu.scr -i emmc_default.img
+
# Generate MTD image for U-Boot serial console testing
rm -f mtd_uboot.img
./qflasher -v -x xloader-qemu.bin -s secondary-qemu.bin -k u-boot.bin -m rx51 -o mtd_uboot.img
# Generate MTD image for RAM booting from bootloader nolo images, compiled image and rootfs image
rm -f mtd_ram.img
-./qflasher -v -x xloader-qemu.bin -s secondary-qemu.bin -k combined.bin -r ubi.img -m rx51 -o mtd_ram.img
+./qflasher -v -x xloader-qemu.bin -s secondary-qemu.bin -k combined_uimage.bin -r ubi.img -m rx51 -o mtd_ram.img
+rm -f mtd_ram2.img
+./qflasher -v -x xloader-qemu.bin -s secondary-qemu.bin -k combined_zimage.bin -r ubi.img -m rx51 -o mtd_ram2.img
# Generate MTD image for eMMC booting from bootloader nolo images, u-boot image and rootfs image
rm -f mtd_emmc.img
@@ -238,7 +269,7 @@
kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true
wait || true
-# Run MTD image in qemu and wait for 300s if kernel from RAM is correctly booted
+# Run MTD image in qemu and wait for 300s if uImage kernel from RAM is correctly booted
rm -f qemu_ram.log
./qemu-system-arm -M n900 -mtdblock mtd_ram.img -serial /dev/stdout -display none > qemu_ram.log &
qemu_pid=$!
@@ -250,7 +281,19 @@
kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true
wait || true
-# Run MTD image in qemu and wait for 300s if kernel from eMMC is correctly booted
+# Run MTD image in qemu and wait for 300s if zImage kernel from RAM is correctly booted
+rm -f qemu_ram2.log
+./qemu-system-arm -M n900 -mtdblock mtd_ram2.img -sd emmc_default.img -serial /dev/stdout -display none > qemu_ram2.log &
+qemu_pid=$!
+tail -F qemu_ram2.log &
+tail_pid=$!
+sleep 300 &
+sleep_pid=$!
+wait -n $sleep_pid $qemu_pid || true
+kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true
+wait || true
+
+# Run MTD image in qemu and wait for 300s if uImage kernel from eMMC is correctly booted
rm -f qemu_emmc.log
./qemu-system-arm -M n900 -mtdblock mtd_emmc.img -sd emmc_emmc.img -serial /dev/stdout -display none > qemu_emmc.log &
qemu_pid=$!
@@ -262,6 +305,18 @@
kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true
wait || true
+# Run MTD image in qemu and wait for 300s if zImage kernel from eMMC is correctly booted
+rm -f qemu_emmc2.log
+./qemu-system-arm -M n900 -mtdblock mtd_emmc.img -sd emmc_emmc2.img -serial /dev/stdout -display none > qemu_emmc2.log &
+qemu_pid=$!
+tail -F qemu_emmc2.log &
+tail_pid=$!
+sleep 300 &
+sleep_pid=$!
+wait -n $sleep_pid $qemu_pid || true
+kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true
+wait || true
+
# Run MTD image in qemu and wait for 300s if kernel from OneNAND is correctly booted
rm -f qemu_nand.log
./qemu-system-arm -M n900 -mtdblock mtd_nand.img -sd emmc_nand.img -serial /dev/stdout -display none > qemu_nand.log &
@@ -281,13 +336,15 @@
echo
if grep -q 'Successfully booted' qemu_uboot.log; then echo "U-Boot serial console is working"; else echo "U-Boot serial console test failed"; fi
-if grep -q 'Successfully booted' qemu_ram.log; then echo "Kernel was successfully booted from RAM"; else echo "Failed to boot kernel from RAM"; fi
-if grep -q 'Successfully booted' qemu_emmc.log; then echo "Kernel was successfully booted from eMMC"; else echo "Failed to boot kernel from eMMC"; fi
-if grep -q 'Successfully booted' qemu_nand.log; then echo "Kernel was successfully booted from OneNAND"; else echo "Failed to boot kernel from OneNAND"; fi
+if grep -q 'Successfully booted' qemu_ram.log; then echo "Kernel (uImage) was successfully booted from RAM"; else echo "Failed to boot kernel (uImage) from RAM"; fi
+if grep -q 'Successfully booted' qemu_ram2.log; then echo "Kernel (zImage) was successfully booted from RAM"; else echo "Failed to boot kernel (zImage) from RAM"; fi
+if grep -q 'Successfully booted' qemu_emmc.log; then echo "Kernel (uImage) was successfully booted from eMMC"; else echo "Failed to boot kernel (uImage) from eMMC"; fi
+if grep -q 'Successfully booted' qemu_emmc2.log; then echo "Kernel (zImage) was successfully booted from eMMC"; else echo "Failed to boot kernel (zImage) from eMMC"; fi
+if grep -q 'Successfully booted' qemu_nand.log; then echo "Kernel (uImage) was successfully booted from OneNAND"; else echo "Failed to boot kernel (uImage) from OneNAND"; fi
echo
-if grep -q 'Successfully booted' qemu_uboot.log && grep -q 'Successfully booted' qemu_ram.log && grep -q 'Successfully booted' qemu_emmc.log && grep -q 'Successfully booted' qemu_nand.log; then
+if grep -q 'Successfully booted' qemu_uboot.log && grep -q 'Successfully booted' qemu_ram.log && grep -q 'Successfully booted' qemu_ram2.log && grep -q 'Successfully booted' qemu_emmc.log && grep -q 'Successfully booted' qemu_emmc2.log && grep -q 'Successfully booted' qemu_nand.log; then
echo "All tests passed"
exit 0
else