blob: 7093ad1cd4fc642e953a715cc0015ecff94f2456 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassd2cb9b22015-03-05 12:25:29 -07002/*
3 * PCI emulation device which swaps the case of text
4 *
5 * Copyright (c) 2014 Google, Inc
6 * Written by Simon Glass <sjg@chromium.org>
Simon Glassd2cb9b22015-03-05 12:25:29 -07007 */
8
9#include <common.h>
10#include <dm.h>
Simon Glass38068822015-05-04 11:31:08 -060011#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Simon Glassd2cb9b22015-03-05 12:25:29 -070013#include <pci.h>
14#include <asm/test.h>
15#include <linux/ctype.h>
16
17/**
Simon Glass8a8d24b2020-12-03 16:55:23 -070018 * struct swap_case_plat - platform data for this device
Simon Glassd2cb9b22015-03-05 12:25:29 -070019 *
20 * @command: Current PCI command value
21 * @bar: Current base address values
22 */
Simon Glass8a8d24b2020-12-03 16:55:23 -070023struct swap_case_plat {
Simon Glassd2cb9b22015-03-05 12:25:29 -070024 u16 command;
Simon Glassfe996ec2018-06-12 00:05:02 -060025 u32 bar[6];
Simon Glassd2cb9b22015-03-05 12:25:29 -070026};
27
Simon Glassd2cb9b22015-03-05 12:25:29 -070028enum {
29 MEM_TEXT_SIZE = 0x100,
30};
31
32enum swap_case_op {
33 OP_TO_LOWER,
34 OP_TO_UPPER,
35 OP_SWAP,
36};
37
38static struct pci_bar {
39 int type;
40 u32 size;
41} barinfo[] = {
42 { PCI_BASE_ADDRESS_SPACE_IO, 1 },
43 { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
44 { 0, 0 },
45 { 0, 0 },
46 { 0, 0 },
47 { 0, 0 },
48};
49
50struct swap_case_priv {
51 enum swap_case_op op;
52 char mem_text[MEM_TEXT_SIZE];
53};
54
Simon Glassc4e72c42020-01-27 08:49:37 -070055static int sandbox_swap_case_use_ea(const struct udevice *dev)
Alex Marginean21ebbaf2019-06-07 11:24:24 +030056{
Simon Glassf10643c2020-12-19 10:40:14 -070057 return !!ofnode_get_property(dev_ofnode(dev), "use-ea", NULL);
Alex Marginean21ebbaf2019-06-07 11:24:24 +030058}
59
60/* Please keep these macros in sync with ea_regs below */
61#define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
62#define PCI_CAP_ID_EA_ENTRY_CNT 4
63/* Hardcoded EA structure, excluding 1st DW. */
64static const u32 ea_regs[] = {
65 /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
66 (2 << 8) | 2,
67 PCI_CAP_EA_BASE_LO0,
68 0,
69 /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
70 (1 << 4) | 2,
71 PCI_CAP_EA_BASE_LO1,
72 MEM_TEXT_SIZE - 1,
73 /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
74 (2 << 4) | 3,
75 PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
76 PCI_CAP_EA_SIZE_LO,
77 PCI_CAP_EA_BASE_HI2,
78 /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
79 (4 << 4) | 4,
80 PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
81 PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
82 PCI_CAP_EA_BASE_HI4,
83 PCI_CAP_EA_SIZE_HI,
84};
85
Simon Glassc4e72c42020-01-27 08:49:37 -070086static int sandbox_swap_case_read_ea(const struct udevice *emul, uint offset,
Alex Marginean21ebbaf2019-06-07 11:24:24 +030087 ulong *valuep, enum pci_size_t size)
88{
89 u32 reg;
90
91 offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
92 reg = ea_regs[offset >> 2];
93 reg >>= (offset % 4) * 8;
94
95 *valuep = reg;
96 return 0;
97}
98
Simon Glassc4e72c42020-01-27 08:49:37 -070099static int sandbox_swap_case_read_config(const struct udevice *emul,
100 uint offset, ulong *valuep,
101 enum pci_size_t size)
Simon Glassd2cb9b22015-03-05 12:25:29 -0700102{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700103 struct swap_case_plat *plat = dev_get_plat(emul);
Simon Glassd2cb9b22015-03-05 12:25:29 -0700104
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300105 /*
106 * The content of the EA capability structure is handled elsewhere to
107 * keep the switch/case below sane
108 */
109 if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
110 offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
111 return sandbox_swap_case_read_ea(emul, offset, valuep, size);
112
Simon Glassd2cb9b22015-03-05 12:25:29 -0700113 switch (offset) {
114 case PCI_COMMAND:
115 *valuep = plat->command;
116 break;
117 case PCI_HEADER_TYPE:
118 *valuep = 0;
119 break;
120 case PCI_VENDOR_ID:
121 *valuep = SANDBOX_PCI_VENDOR_ID;
122 break;
123 case PCI_DEVICE_ID:
Simon Glass34145812019-09-25 08:56:01 -0600124 *valuep = SANDBOX_PCI_SWAP_CASE_EMUL_ID;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700125 break;
126 case PCI_CLASS_DEVICE:
127 if (size == PCI_SIZE_8) {
128 *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
129 } else {
130 *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
131 SANDBOX_PCI_CLASS_SUB_CODE;
132 }
133 break;
134 case PCI_CLASS_CODE:
135 *valuep = SANDBOX_PCI_CLASS_CODE;
136 break;
137 case PCI_BASE_ADDRESS_0:
138 case PCI_BASE_ADDRESS_1:
139 case PCI_BASE_ADDRESS_2:
140 case PCI_BASE_ADDRESS_3:
141 case PCI_BASE_ADDRESS_4:
142 case PCI_BASE_ADDRESS_5: {
143 int barnum;
Simon Glass75d8f492019-09-25 08:56:42 -0600144 u32 *bar;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700145
Simon Glass37a1cf92019-09-25 08:56:06 -0600146 barnum = pci_offset_to_barnum(offset);
Simon Glassd2cb9b22015-03-05 12:25:29 -0700147 bar = &plat->bar[barnum];
148
Simon Glass75d8f492019-09-25 08:56:42 -0600149 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
150 barinfo[barnum].size);
Simon Glassd2cb9b22015-03-05 12:25:29 -0700151 break;
152 }
Bin Meng95e11062018-08-03 01:14:53 -0700153 case PCI_CAPABILITY_LIST:
154 *valuep = PCI_CAP_ID_PM_OFFSET;
155 break;
156 case PCI_CAP_ID_PM_OFFSET:
157 *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM;
158 break;
Bin Meng7a206142018-10-15 02:21:22 -0700159 case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT:
160 *valuep = PCI_CAP_ID_EXP_OFFSET;
161 break;
Bin Meng95e11062018-08-03 01:14:53 -0700162 case PCI_CAP_ID_EXP_OFFSET:
163 *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP;
164 break;
Bin Meng7a206142018-10-15 02:21:22 -0700165 case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT:
166 *valuep = PCI_CAP_ID_MSIX_OFFSET;
167 break;
Bin Meng95e11062018-08-03 01:14:53 -0700168 case PCI_CAP_ID_MSIX_OFFSET:
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300169 if (sandbox_swap_case_use_ea(emul))
170 *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
171 else
172 *valuep = PCI_CAP_ID_MSIX;
Bin Meng95e11062018-08-03 01:14:53 -0700173 break;
Bin Meng7a206142018-10-15 02:21:22 -0700174 case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300175 if (sandbox_swap_case_use_ea(emul))
176 *valuep = PCI_CAP_ID_EA_OFFSET;
177 else
178 *valuep = 0;
179 break;
180 case PCI_CAP_ID_EA_OFFSET:
181 *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
182 break;
183 case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
Bin Meng7a206142018-10-15 02:21:22 -0700184 *valuep = 0;
185 break;
Bin Meng95e11062018-08-03 01:14:53 -0700186 case PCI_EXT_CAP_ID_ERR_OFFSET:
187 *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR;
188 break;
189 case PCI_EXT_CAP_ID_VC_OFFSET:
190 *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC;
191 break;
192 case PCI_EXT_CAP_ID_DSN_OFFSET:
193 *valuep = PCI_EXT_CAP_ID_DSN;
194 break;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700195 }
196
197 return 0;
198}
199
200static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
201 ulong value, enum pci_size_t size)
202{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700203 struct swap_case_plat *plat = dev_get_plat(emul);
Simon Glassd2cb9b22015-03-05 12:25:29 -0700204
205 switch (offset) {
206 case PCI_COMMAND:
207 plat->command = value;
208 break;
209 case PCI_BASE_ADDRESS_0:
210 case PCI_BASE_ADDRESS_1: {
211 int barnum;
212 u32 *bar;
213
Simon Glass37a1cf92019-09-25 08:56:06 -0600214 barnum = pci_offset_to_barnum(offset);
Simon Glassd2cb9b22015-03-05 12:25:29 -0700215 bar = &plat->bar[barnum];
216
217 debug("w bar %d=%lx\n", barnum, value);
218 *bar = value;
Bin Meng76330ae2018-08-03 01:14:40 -0700219 /* space indicator (bit#0) is read-only */
220 *bar |= barinfo[barnum].type;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700221 break;
222 }
223 }
224
225 return 0;
226}
227
228static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
229 int *barnump, unsigned int *offsetp)
230{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700231 struct swap_case_plat *plat = dev_get_plat(emul);
Simon Glassd2cb9b22015-03-05 12:25:29 -0700232 int barnum;
233
234 for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
235 unsigned int size = barinfo[barnum].size;
Bin Meng76330ae2018-08-03 01:14:40 -0700236 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700237
Bin Meng76330ae2018-08-03 01:14:40 -0700238 if (addr >= base && addr < base + size) {
Simon Glassd2cb9b22015-03-05 12:25:29 -0700239 *barnump = barnum;
Bin Meng76330ae2018-08-03 01:14:40 -0700240 *offsetp = addr - base;
Simon Glassd2cb9b22015-03-05 12:25:29 -0700241 return 0;
242 }
243 }
244 *barnump = -1;
245
246 return -ENOENT;
247}
248
249static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len)
250{
251 for (; len > 0; len--, str++) {
252 switch (op) {
253 case OP_TO_UPPER:
254 *str = toupper(*str);
255 break;
256 case OP_TO_LOWER:
257 *str = tolower(*str);
258 break;
259 case OP_SWAP:
260 if (isupper(*str))
261 *str = tolower(*str);
262 else
263 *str = toupper(*str);
264 break;
265 }
266 }
267}
268
Simon Glasscea7c092019-09-25 08:56:03 -0600269static int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr,
270 ulong *valuep, enum pci_size_t size)
Simon Glassd2cb9b22015-03-05 12:25:29 -0700271{
272 struct swap_case_priv *priv = dev_get_priv(dev);
273 unsigned int offset;
274 int barnum;
275 int ret;
276
277 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
278 if (ret)
279 return ret;
280
281 if (barnum == 0 && offset == 0)
282 *valuep = (*valuep & ~0xff) | priv->op;
283
284 return 0;
285}
286
Simon Glasscea7c092019-09-25 08:56:03 -0600287static int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
288 ulong value, enum pci_size_t size)
Simon Glassd2cb9b22015-03-05 12:25:29 -0700289{
290 struct swap_case_priv *priv = dev_get_priv(dev);
291 unsigned int offset;
292 int barnum;
293 int ret;
294
295 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
296 if (ret)
297 return ret;
298 if (barnum == 0 && offset == 0)
299 priv->op = value;
300
301 return 0;
302}
303
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300304static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300305
Simon Glassd2cb9b22015-03-05 12:25:29 -0700306static int sandbox_swap_case_map_physmem(struct udevice *dev,
307 phys_addr_t addr, unsigned long *lenp, void **ptrp)
308{
309 struct swap_case_priv *priv = dev_get_priv(dev);
310 unsigned int offset, avail;
311 int barnum;
312 int ret;
313
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300314 if (sandbox_swap_case_use_ea(dev)) {
315 /*
316 * only support mapping base address in EA test for now, we
317 * don't handle mapping an offset inside a BAR. Seems good
318 * enough for the current test.
319 */
320 switch (addr) {
321 case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
322 *ptrp = &priv->op;
323 *lenp = 4;
324 break;
325 case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
326 *ptrp = priv->mem_text;
327 *lenp = barinfo[1].size - 1;
328 break;
329 case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
330 PCI_CAP_EA_BASE_LO2):
331 *ptrp = &pci_ea_bar2_magic;
332 *lenp = PCI_CAP_EA_SIZE_LO;
333 break;
Simon Glass05a7cab2021-07-18 14:14:23 -0600334#ifdef CONFIG_HOST_64BIT
335 /*
336 * This cannot be work on a 32-bit machine since *lenp is ulong
337 * which is 32-bits, but it needs to have a 64-bit value
338 * assigned
339 */
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300340 case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
Simon Glass05a7cab2021-07-18 14:14:23 -0600341 PCI_CAP_EA_BASE_LO4): {
342 static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
343
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300344 *ptrp = &pci_ea_bar4_magic;
345 *lenp = (PCI_CAP_EA_SIZE_HI << 32) |
346 PCI_CAP_EA_SIZE_LO;
347 break;
Simon Glass05a7cab2021-07-18 14:14:23 -0600348 }
349#endif
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300350 default:
351 return -ENOENT;
352 }
353 return 0;
354 }
355
Simon Glassd2cb9b22015-03-05 12:25:29 -0700356 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
357 if (ret)
358 return ret;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300359
Simon Glassd2cb9b22015-03-05 12:25:29 -0700360 if (barnum == 1) {
361 *ptrp = priv->mem_text + offset;
362 avail = barinfo[1].size - offset;
363 if (avail > barinfo[1].size)
364 *lenp = 0;
365 else
366 *lenp = min(*lenp, (ulong)avail);
367
368 return 0;
369 }
370
371 return -ENOENT;
372}
373
374static int sandbox_swap_case_unmap_physmem(struct udevice *dev,
375 const void *vaddr, unsigned long len)
376{
377 struct swap_case_priv *priv = dev_get_priv(dev);
378
379 sandbox_swap_case_do_op(priv->op, (void *)vaddr, len);
380
381 return 0;
382}
383
Simon Glasscea7c092019-09-25 08:56:03 -0600384static struct dm_pci_emul_ops sandbox_swap_case_emul_ops = {
Simon Glassd2cb9b22015-03-05 12:25:29 -0700385 .read_config = sandbox_swap_case_read_config,
386 .write_config = sandbox_swap_case_write_config,
387 .read_io = sandbox_swap_case_read_io,
388 .write_io = sandbox_swap_case_write_io,
389 .map_physmem = sandbox_swap_case_map_physmem,
390 .unmap_physmem = sandbox_swap_case_unmap_physmem,
391};
392
393static const struct udevice_id sandbox_swap_case_ids[] = {
394 { .compatible = "sandbox,swap-case" },
395 { }
396};
397
398U_BOOT_DRIVER(sandbox_swap_case_emul) = {
399 .name = "sandbox_swap_case_emul",
400 .id = UCLASS_PCI_EMUL,
401 .of_match = sandbox_swap_case_ids,
402 .ops = &sandbox_swap_case_emul_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700403 .priv_auto = sizeof(struct swap_case_priv),
Simon Glass8a8d24b2020-12-03 16:55:23 -0700404 .plat_auto = sizeof(struct swap_case_plat),
Simon Glassd2cb9b22015-03-05 12:25:29 -0700405};
Bin Meng59a160e2018-08-03 01:14:46 -0700406
407static struct pci_device_id sandbox_swap_case_supported[] = {
Simon Glass34145812019-09-25 08:56:01 -0600408 { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_SWAP_CASE_EMUL_ID),
409 SWAP_CASE_DRV_DATA },
Bin Meng59a160e2018-08-03 01:14:46 -0700410 {},
411};
412
413U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);