Blame - arch/arm/mach-socfpga/Kconfig - platform/external/u-boot

blob: 2563e7926d1d80a2fc4770e7cf10f2aa60c978db [file] [log] [blame]

Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Simon Glass	77d2f7f	2016-09-12 23:18:41 -0600	[diff] [blame]	3	config SPL_LIBCOMMON_SUPPORT
				4	default y
				5
Simon Glass	1646eba	2016-09-12 23:18:42 -0600	[diff] [blame]	6	config SPL_LIBDISK_SUPPORT
				7	default y
				8
Simon Glass	cc4288e	2016-09-12 23:18:43 -0600	[diff] [blame]	9	config SPL_LIBGENERIC_SUPPORT
				10	default y
				11
Simon Glass	1fdf7c6	2016-09-12 23:18:44 -0600	[diff] [blame]	12	config SPL_MMC_SUPPORT
				13	default y if DM_MMC
				14
Simon Glass	d6b9bd8	2016-09-12 23:18:48 -0600	[diff] [blame]	15	config SPL_NAND_SUPPORT
				16	default y if SPL_NAND_DENALI
				17
Simon Glass	e00f76c	2016-09-12 23:18:56 -0600	[diff] [blame]	18	config SPL_SERIAL_SUPPORT
				19	default y
				20
Simon Glass	e404ade	2016-09-12 23:18:57 -0600	[diff] [blame]	21	config SPL_SPI_FLASH_SUPPORT
Simon Glass	f35ed9e	2016-09-12 23:18:58 -0600	[diff] [blame]	22	default y if SPL_SPI_SUPPORT
				23
				24	config SPL_SPI_SUPPORT
Simon Glass	e404ade	2016-09-12 23:18:57 -0600	[diff] [blame]	25	default y if DM_SPI
				26
Simon Glass	02e69a5	2016-09-12 23:19:02 -0600	[diff] [blame]	27	config SPL_WATCHDOG_SUPPORT
				28	default y
				29
Dalon Westergreen	f0fb4fa	2017-02-10 17:15:34 -0800	[diff] [blame]	30	config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
				31	default y
				32
				33	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
				34	default 0xa2
				35
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	36	config TARGET_SOCFPGA_ARRIA5
				37	bool
Dinh Nguyen	ed77aeb	2015-12-02 13:31:25 -0600	[diff] [blame]	38	select TARGET_SOCFPGA_GEN5
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	39
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	40	config TARGET_SOCFPGA_ARRIA10
				41	bool
				42
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	43	config TARGET_SOCFPGA_CYCLONE5
				44	bool
Dinh Nguyen	ed77aeb	2015-12-02 13:31:25 -0600	[diff] [blame]	45	select TARGET_SOCFPGA_GEN5
				46
				47	config TARGET_SOCFPGA_GEN5
				48	bool
Ley Foon Tan	707cd01	2017-04-05 17:32:51 +0800	[diff] [blame]	49	select ALTERA_SDRAM
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	50
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	51	choice
				52	prompt "Altera SOCFPGA board select"
Joe Hershberger	a26cd04	2015-05-12 14:46:23 -0500	[diff] [blame]	53	optional
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	54
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	55	config TARGET_SOCFPGA_ARRIA10_SOCDK
				56	bool "Altera SOCFPGA SoCDK (Arria 10)"
				57	select TARGET_SOCFPGA_ARRIA10
				58
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	59	config TARGET_SOCFPGA_ARRIA5_SOCDK
				60	bool "Altera SOCFPGA SoCDK (Arria V)"
				61	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	62
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	63	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				64	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				65	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	66
Marek Vasut	a548bc5	2017-04-05 13:17:03 +0200	[diff] [blame]	67	config TARGET_SOCFPGA_ARIES_MCVEVK
				68	bool "Aries MCVEVK (Cyclone V)"
Marek Vasut	d88995a	2015-08-03 01:37:28 +0200	[diff] [blame]	69	select TARGET_SOCFPGA_CYCLONE5
				70
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	71	config TARGET_SOCFPGA_EBV_SOCRATES
				72	bool "EBV SoCrates (Cyclone V)"
				73	select TARGET_SOCFPGA_CYCLONE5
				74
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	75	config TARGET_SOCFPGA_IS1
				76	bool "IS1 (Cyclone V)"
				77	select TARGET_SOCFPGA_CYCLONE5
				78
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	79	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				80	bool "samtec VIN\|ING FPGA (Cyclone V)"
Tom Rini	e5ec481	2017-01-22 19:43:11 -0500	[diff] [blame]	81	select BOARD_LATE_INIT
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	82	select TARGET_SOCFPGA_CYCLONE5
				83
Marek Vasut	cf0a8da	2016-06-08 02:57:05 +0200	[diff] [blame]	84	config TARGET_SOCFPGA_SR1500
				85	bool "SR1500 (Cyclone V)"
				86	select TARGET_SOCFPGA_CYCLONE5
				87
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	88	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				89	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				90	select TARGET_SOCFPGA_CYCLONE5
				91
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	92	config TARGET_SOCFPGA_TERASIC_DE10_NANO
				93	bool "Terasic DE10-Nano (Cyclone V)"
				94	select TARGET_SOCFPGA_CYCLONE5
				95
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	96	config TARGET_SOCFPGA_TERASIC_DE1_SOC
				97	bool "Terasic DE1-SoC (Cyclone V)"
				98	select TARGET_SOCFPGA_CYCLONE5
				99
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	100	config TARGET_SOCFPGA_TERASIC_SOCKIT
				101	bool "Terasic SoCkit (Cyclone V)"
				102	select TARGET_SOCFPGA_CYCLONE5
				103
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	104	endchoice
				105
				106	config SYS_BOARD
Marek Vasut	f089240	2015-08-10 21:24:53 +0200	[diff] [blame]	107	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	108	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	f089240	2015-08-10 21:24:53 +0200	[diff] [blame]	109	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	110	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	111	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	112	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	113	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	a548bc5	2017-04-05 13:17:03 +0200	[diff] [blame]	114	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	115	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	116	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	ae9996c	2015-11-18 11:06:09 +0100	[diff] [blame]	117	default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	118	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	119
				120	config SYS_VENDOR
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	121	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	122	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	123	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	a548bc5	2017-04-05 13:17:03 +0200	[diff] [blame]	124	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	125	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	126	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	127	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	128	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	129	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	130	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	131
				132	config SYS_SOC
				133	default "socfpga"
				134
				135	config SYS_CONFIG_NAME
Dinh Nguyen	3cbc7b8	2015-09-22 17:01:32 -0500	[diff] [blame]	136	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	137	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen	3cbc7b8	2015-09-22 17:01:32 -0500	[diff] [blame]	138	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	139	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	140	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	141	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	142	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	a548bc5	2017-04-05 13:17:03 +0200	[diff] [blame]	143	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	144	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	145	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	ae9996c	2015-11-18 11:06:09 +0100	[diff] [blame]	146	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	147	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	148
				149	endif