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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass6854f872014-11-14 20:56:33 -07002/*
3 * Copyright (C) 2014 Google, Inc
4 *
5 * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
6 *
7 * Modifications are:
8 * Copyright (C) 2003-2004 Linux Networx
9 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
10 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
11 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
12 * Copyright (C) 2005-2006 Tyan
13 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
14 * Copyright (C) 2005-2009 coresystems GmbH
15 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
16 *
17 * PCI Bus Services, see include/linux/pci.h for further explanation.
18 *
19 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
20 * David Mosberger-Tang
21 *
22 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
Simon Glass6854f872014-11-14 20:56:33 -070023 */
24
25#include <common.h>
26#include <bios_emul.h>
Simon Glass52f24232020-05-10 11:40:00 -060027#include <bootstage.h>
Simon Glass3f4e1e82015-11-29 13:17:57 -070028#include <dm.h>
Simon Glass6854f872014-11-14 20:56:33 -070029#include <errno.h>
Simon Glass35a3f872019-12-28 10:44:56 -070030#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060031#include <log.h>
Simon Glass6854f872014-11-14 20:56:33 -070032#include <malloc.h>
33#include <pci.h>
34#include <pci_rom.h>
35#include <vbe.h>
Simon Glassee87ee82016-10-05 20:42:17 -060036#include <video.h>
Simon Glass6854f872014-11-14 20:56:33 -070037#include <video_fb.h>
Simon Glass3cabcf92020-04-08 16:57:35 -060038#include <acpi/acpi_s3.h>
Bin Menga4520022015-07-06 16:31:36 +080039#include <linux/screen_info.h>
Simon Glass6854f872014-11-14 20:56:33 -070040
Bin Meng68769eb2017-04-21 07:24:46 -070041DECLARE_GLOBAL_DATA_PTR;
Bin Meng68769eb2017-04-21 07:24:46 -070042
Simon Glass3f4e1e82015-11-29 13:17:57 -070043__weak bool board_should_run_oprom(struct udevice *dev)
Simon Glass6854f872014-11-14 20:56:33 -070044{
Bin Meng68769eb2017-04-21 07:24:46 -070045#if defined(CONFIG_X86) && defined(CONFIG_HAVE_ACPI_RESUME)
46 if (gd->arch.prev_sleep_state == ACPI_S3) {
47 if (IS_ENABLED(CONFIG_S3_VGA_ROM_RUN))
48 return true;
49 else
50 return false;
51 }
52#endif
53
Simon Glass6854f872014-11-14 20:56:33 -070054 return true;
55}
56
Bin Mengf698baa2016-06-14 02:02:40 -070057__weak bool board_should_load_oprom(struct udevice *dev)
Simon Glass6854f872014-11-14 20:56:33 -070058{
Bin Mengc0aea6b2016-06-14 02:02:39 -070059 return true;
Simon Glass6854f872014-11-14 20:56:33 -070060}
61
62__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
63{
64 return vendev;
65}
66
Simon Glass3f4e1e82015-11-29 13:17:57 -070067static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
Simon Glass6854f872014-11-14 20:56:33 -070068{
Simon Glass3f4e1e82015-11-29 13:17:57 -070069 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
Simon Glass6854f872014-11-14 20:56:33 -070070 struct pci_rom_header *rom_header;
71 struct pci_rom_data *rom_data;
Simon Glass40305242014-12-29 19:32:23 -070072 u16 rom_vendor, rom_device;
Bin Mengd57c2f22015-04-24 15:48:03 +080073 u32 rom_class;
Simon Glass6854f872014-11-14 20:56:33 -070074 u32 vendev;
75 u32 mapped_vendev;
76 u32 rom_address;
77
Simon Glass3f4e1e82015-11-29 13:17:57 -070078 vendev = pplat->vendor << 16 | pplat->device;
Simon Glass6854f872014-11-14 20:56:33 -070079 mapped_vendev = board_map_oprom_vendev(vendev);
80 if (vendev != mapped_vendev)
81 debug("Device ID mapped to %#08x\n", mapped_vendev);
82
Bin Meng786a08e2015-07-06 16:31:33 +080083#ifdef CONFIG_VGA_BIOS_ADDR
84 rom_address = CONFIG_VGA_BIOS_ADDR;
Simon Glass6854f872014-11-14 20:56:33 -070085#else
Simon Glass4a2708a2015-01-14 21:37:04 -070086
Simon Glass3f4e1e82015-11-29 13:17:57 -070087 dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
Simon Glass6854f872014-11-14 20:56:33 -070088 if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
89 debug("%s: rom_address=%x\n", __func__, rom_address);
90 return -ENOENT;
91 }
92
93 /* Enable expansion ROM address decoding. */
Simon Glass3f4e1e82015-11-29 13:17:57 -070094 dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
95 rom_address | PCI_ROM_ADDRESS_ENABLE);
Simon Glass6854f872014-11-14 20:56:33 -070096#endif
97 debug("Option ROM address %x\n", rom_address);
Minghuan Lianef2d17f2015-01-22 13:21:55 +080098 rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
Simon Glass6854f872014-11-14 20:56:33 -070099
100 debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700101 le16_to_cpu(rom_header->signature),
102 rom_header->size * 512, le16_to_cpu(rom_header->data));
Simon Glass6854f872014-11-14 20:56:33 -0700103
Simon Glass40305242014-12-29 19:32:23 -0700104 if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
Simon Glass6854f872014-11-14 20:56:33 -0700105 printf("Incorrect expansion ROM header signature %04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700106 le16_to_cpu(rom_header->signature));
Bin Mengf110da92015-07-08 13:06:41 +0800107#ifndef CONFIG_VGA_BIOS_ADDR
108 /* Disable expansion ROM address decoding */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700109 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
Bin Mengf110da92015-07-08 13:06:41 +0800110#endif
Simon Glass6854f872014-11-14 20:56:33 -0700111 return -EINVAL;
112 }
113
Simon Glass40305242014-12-29 19:32:23 -0700114 rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
115 rom_vendor = le16_to_cpu(rom_data->vendor);
116 rom_device = le16_to_cpu(rom_data->device);
Simon Glass6854f872014-11-14 20:56:33 -0700117
118 debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
Simon Glass40305242014-12-29 19:32:23 -0700119 rom_vendor, rom_device);
Simon Glass6854f872014-11-14 20:56:33 -0700120
121 /* If the device id is mapped, a mismatch is expected */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700122 if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
Simon Glass6854f872014-11-14 20:56:33 -0700123 (vendev == mapped_vendev)) {
124 printf("ID mismatch: vendor ID %04x, device ID %04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700125 rom_vendor, rom_device);
Simon Glassc5caba02014-12-29 19:32:27 -0700126 /* Continue anyway */
Simon Glass6854f872014-11-14 20:56:33 -0700127 }
128
Bin Mengd57c2f22015-04-24 15:48:03 +0800129 rom_class = (le16_to_cpu(rom_data->class_hi) << 8) | rom_data->class_lo;
130 debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
131 rom_class, rom_data->type);
Simon Glass6854f872014-11-14 20:56:33 -0700132
Simon Glass3f4e1e82015-11-29 13:17:57 -0700133 if (pplat->class != rom_class) {
Bin Mengd57c2f22015-04-24 15:48:03 +0800134 debug("Class Code mismatch ROM %06x, dev %06x\n",
Simon Glass3f4e1e82015-11-29 13:17:57 -0700135 rom_class, pplat->class);
Simon Glass6854f872014-11-14 20:56:33 -0700136 }
137 *hdrp = rom_header;
138
139 return 0;
140}
141
Simon Glassd830b152016-01-15 05:23:22 -0700142/**
143 * pci_rom_load() - Load a ROM image and return a pointer to it
144 *
145 * @rom_header: Pointer to ROM image
146 * @ram_headerp: Returns a pointer to the image in RAM
147 * @allocedp: Returns true if @ram_headerp was allocated and needs
148 * to be freed
149 * @return 0 if OK, -ve on error. Note that @allocedp is set up regardless of
150 * the error state. Even if this function returns an error, it may have
151 * allocated memory.
152 */
153static int pci_rom_load(struct pci_rom_header *rom_header,
154 struct pci_rom_header **ram_headerp, bool *allocedp)
Simon Glass6854f872014-11-14 20:56:33 -0700155{
156 struct pci_rom_data *rom_data;
157 unsigned int rom_size;
158 unsigned int image_size = 0;
159 void *target;
160
Simon Glassd830b152016-01-15 05:23:22 -0700161 *allocedp = false;
Simon Glass6854f872014-11-14 20:56:33 -0700162 do {
163 /* Get next image, until we see an x86 version */
164 rom_header = (struct pci_rom_header *)((void *)rom_header +
165 image_size);
166
167 rom_data = (struct pci_rom_data *)((void *)rom_header +
Simon Glass40305242014-12-29 19:32:23 -0700168 le16_to_cpu(rom_header->data));
Simon Glass6854f872014-11-14 20:56:33 -0700169
Simon Glass40305242014-12-29 19:32:23 -0700170 image_size = le16_to_cpu(rom_data->ilen) * 512;
171 } while ((rom_data->type != 0) && (rom_data->indicator == 0));
Simon Glass6854f872014-11-14 20:56:33 -0700172
173 if (rom_data->type != 0)
174 return -EACCES;
175
176 rom_size = rom_header->size * 512;
177
Simon Glassbdc88d42014-12-29 19:32:24 -0700178#ifdef PCI_VGA_RAM_IMAGE_START
Simon Glass6854f872014-11-14 20:56:33 -0700179 target = (void *)PCI_VGA_RAM_IMAGE_START;
Simon Glassbdc88d42014-12-29 19:32:24 -0700180#else
181 target = (void *)malloc(rom_size);
182 if (!target)
183 return -ENOMEM;
Simon Glassd830b152016-01-15 05:23:22 -0700184 *allocedp = true;
Simon Glassbdc88d42014-12-29 19:32:24 -0700185#endif
Simon Glass6854f872014-11-14 20:56:33 -0700186 if (target != rom_header) {
Simon Glassfba7eac2015-01-01 16:18:01 -0700187 ulong start = get_timer(0);
188
Simon Glass6854f872014-11-14 20:56:33 -0700189 debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
190 rom_header, target, rom_size);
191 memcpy(target, rom_header, rom_size);
192 if (memcmp(target, rom_header, rom_size)) {
193 printf("VGA ROM copy failed\n");
194 return -EFAULT;
195 }
Simon Glassfba7eac2015-01-01 16:18:01 -0700196 debug("Copy took %lums\n", get_timer(start));
Simon Glass6854f872014-11-14 20:56:33 -0700197 }
198 *ram_headerp = target;
199
200 return 0;
201}
202
Bin Meng153e1dd2015-08-13 00:29:16 -0700203struct vbe_mode_info mode_info;
Simon Glass6854f872014-11-14 20:56:33 -0700204
Bin Menga4520022015-07-06 16:31:36 +0800205void setup_video(struct screen_info *screen_info)
206{
Bin Menga4520022015-07-06 16:31:36 +0800207 struct vesa_mode_info *vesa = &mode_info.vesa;
208
Bin Meng1e7a0472015-07-30 03:49:13 -0700209 /* Sanity test on VESA parameters */
210 if (!vesa->x_resolution || !vesa->y_resolution)
211 return;
212
Bin Menga4520022015-07-06 16:31:36 +0800213 screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB;
214
215 screen_info->lfb_width = vesa->x_resolution;
216 screen_info->lfb_height = vesa->y_resolution;
217 screen_info->lfb_depth = vesa->bits_per_pixel;
218 screen_info->lfb_linelength = vesa->bytes_per_scanline;
219 screen_info->lfb_base = vesa->phys_base_ptr;
220 screen_info->lfb_size =
221 ALIGN(screen_info->lfb_linelength * screen_info->lfb_height,
222 65536);
223 screen_info->lfb_size >>= 16;
224 screen_info->red_size = vesa->red_mask_size;
225 screen_info->red_pos = vesa->red_mask_pos;
226 screen_info->green_size = vesa->green_mask_size;
227 screen_info->green_pos = vesa->green_mask_pos;
228 screen_info->blue_size = vesa->blue_mask_size;
229 screen_info->blue_pos = vesa->blue_mask_pos;
230 screen_info->rsvd_size = vesa->reserved_mask_size;
231 screen_info->rsvd_pos = vesa->reserved_mask_pos;
Bin Menga4520022015-07-06 16:31:36 +0800232}
233
Simon Glass3f4e1e82015-11-29 13:17:57 -0700234int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
235 int exec_method)
Simon Glass6854f872014-11-14 20:56:33 -0700236{
Simon Glass3f4e1e82015-11-29 13:17:57 -0700237 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
Andreas Bießmanned488992016-02-16 23:29:31 +0100238 struct pci_rom_header *rom = NULL, *ram = NULL;
Simon Glass6854f872014-11-14 20:56:33 -0700239 int vesa_mode = -1;
Simon Glassd830b152016-01-15 05:23:22 -0700240 bool emulate, alloced;
Simon Glass6854f872014-11-14 20:56:33 -0700241 int ret;
242
243 /* Only execute VGA ROMs */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700244 if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
245 debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
Simon Glass6854f872014-11-14 20:56:33 -0700246 PCI_CLASS_DISPLAY_VGA);
247 return -ENODEV;
248 }
249
Bin Mengf698baa2016-06-14 02:02:40 -0700250 if (!board_should_load_oprom(dev))
Simon Glass595aac92018-10-01 12:22:44 -0600251 return log_msg_ret("Should not load OPROM", -ENXIO);
Simon Glass6854f872014-11-14 20:56:33 -0700252
Simon Glass3f4e1e82015-11-29 13:17:57 -0700253 ret = pci_rom_probe(dev, &rom);
Simon Glass6854f872014-11-14 20:56:33 -0700254 if (ret)
255 return ret;
256
Simon Glassd830b152016-01-15 05:23:22 -0700257 ret = pci_rom_load(rom, &ram, &alloced);
Simon Glass6854f872014-11-14 20:56:33 -0700258 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700259 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700260
Simon Glassd830b152016-01-15 05:23:22 -0700261 if (!board_should_run_oprom(dev)) {
262 ret = -ENXIO;
263 goto err;
264 }
Simon Glass6854f872014-11-14 20:56:33 -0700265
266#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
267 defined(CONFIG_FRAMEBUFFER_VESA_MODE)
268 vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
269#endif
Simon Glass9a99caf2015-01-01 16:18:05 -0700270 debug("Selected vesa mode %#x\n", vesa_mode);
Simon Glassbc17d8f2015-01-27 22:13:34 -0700271
272 if (exec_method & PCI_ROM_USE_NATIVE) {
273#ifdef CONFIG_X86
274 emulate = false;
275#else
276 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
277 printf("BIOS native execution is only available on x86\n");
Simon Glassd830b152016-01-15 05:23:22 -0700278 ret = -ENOSYS;
279 goto err;
Simon Glassbc17d8f2015-01-27 22:13:34 -0700280 }
281 emulate = true;
282#endif
283 } else {
284#ifdef CONFIG_BIOSEMU
285 emulate = true;
286#else
287 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
288 printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
Simon Glassd830b152016-01-15 05:23:22 -0700289 ret = -ENOSYS;
290 goto err;
Simon Glassbc17d8f2015-01-27 22:13:34 -0700291 }
292 emulate = false;
293#endif
294 }
295
Simon Glass6854f872014-11-14 20:56:33 -0700296 if (emulate) {
297#ifdef CONFIG_BIOSEMU
298 BE_VGAInfo *info;
299
Simon Glass72826722016-01-17 16:11:09 -0700300 ret = biosemu_setup(dev, &info);
Simon Glass6854f872014-11-14 20:56:33 -0700301 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700302 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700303 biosemu_set_interrupt_handler(0x15, int15_handler);
Simon Glass72826722016-01-17 16:11:09 -0700304 ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
305 true, vesa_mode, &mode_info);
Simon Glass6854f872014-11-14 20:56:33 -0700306 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700307 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700308#endif
309 } else {
Simon Glass6c456512019-04-25 21:59:08 -0600310#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
Simon Glass6854f872014-11-14 20:56:33 -0700311 bios_set_interrupt_handler(0x15, int15_handler);
312
Simon Glass8beb0bd2015-11-29 13:17:58 -0700313 bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
314 &mode_info);
Simon Glass6854f872014-11-14 20:56:33 -0700315#endif
316 }
Simon Glass9a99caf2015-01-01 16:18:05 -0700317 debug("Final vesa mode %#x\n", mode_info.video_mode);
Simon Glassd830b152016-01-15 05:23:22 -0700318 ret = 0;
Simon Glass6854f872014-11-14 20:56:33 -0700319
Simon Glassd830b152016-01-15 05:23:22 -0700320err:
321 if (alloced)
322 free(ram);
323 return ret;
Simon Glass6854f872014-11-14 20:56:33 -0700324}
Simon Glassee87ee82016-10-05 20:42:17 -0600325
326#ifdef CONFIG_DM_VIDEO
Bin Meng5f6ad022016-10-09 04:14:15 -0700327int vbe_setup_video_priv(struct vesa_mode_info *vesa,
328 struct video_priv *uc_priv,
329 struct video_uc_platdata *plat)
Simon Glassee87ee82016-10-05 20:42:17 -0600330{
331 if (!vesa->x_resolution)
Simon Glass595aac92018-10-01 12:22:44 -0600332 return log_msg_ret("No x resolution", -ENXIO);
Simon Glassee87ee82016-10-05 20:42:17 -0600333 uc_priv->xsize = vesa->x_resolution;
334 uc_priv->ysize = vesa->y_resolution;
Simon Glass06696eb2018-11-29 15:08:52 -0700335 uc_priv->line_length = vesa->bytes_per_scanline;
Simon Glassee87ee82016-10-05 20:42:17 -0600336 switch (vesa->bits_per_pixel) {
337 case 32:
338 case 24:
339 uc_priv->bpix = VIDEO_BPP32;
340 break;
341 case 16:
342 uc_priv->bpix = VIDEO_BPP16;
343 break;
344 default:
345 return -EPROTONOSUPPORT;
346 }
347 plat->base = vesa->phys_base_ptr;
348 plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
349
350 return 0;
351}
352
353int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
354{
355 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
356 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
357 int ret;
358
359 /* If we are running from EFI or coreboot, this can't work */
Bin Mengf0920e42016-10-09 04:14:12 -0700360 if (!ll_boot_init()) {
361 printf("Not available (previous bootloader prevents it)\n");
Simon Glassee87ee82016-10-05 20:42:17 -0600362 return -EPERM;
Bin Mengf0920e42016-10-09 04:14:12 -0700363 }
Simon Glassee87ee82016-10-05 20:42:17 -0600364 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
365 ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
366 PCI_ROM_ALLOW_FALLBACK);
367 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
368 if (ret) {
369 debug("failed to run video BIOS: %d\n", ret);
370 return ret;
371 }
372
373 ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat);
374 if (ret) {
375 debug("No video mode configured\n");
376 return ret;
377 }
378
Bin Meng61130932018-04-11 22:02:18 -0700379 printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
Bin Mengf0920e42016-10-09 04:14:12 -0700380 mode_info.vesa.bits_per_pixel);
381
Simon Glassee87ee82016-10-05 20:42:17 -0600382 return 0;
383}
384#endif