blob: 75fb0933371583da12cf3e9f03154f3326d7d7ac [file] [log] [blame]
Simon Glass6854f872014-11-14 20:56:33 -07001/*
2 * Copyright (C) 2014 Google, Inc
3 *
4 * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
5 *
6 * Modifications are:
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
15 *
16 * PCI Bus Services, see include/linux/pci.h for further explanation.
17 *
18 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
19 * David Mosberger-Tang
20 *
21 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
22
23 * SPDX-License-Identifier: GPL-2.0
24 */
25
26#include <common.h>
27#include <bios_emul.h>
Simon Glass3f4e1e82015-11-29 13:17:57 -070028#include <dm.h>
Simon Glass6854f872014-11-14 20:56:33 -070029#include <errno.h>
30#include <malloc.h>
31#include <pci.h>
32#include <pci_rom.h>
33#include <vbe.h>
Simon Glassee87ee82016-10-05 20:42:17 -060034#include <video.h>
Simon Glass6854f872014-11-14 20:56:33 -070035#include <video_fb.h>
Bin Menga4520022015-07-06 16:31:36 +080036#include <linux/screen_info.h>
Simon Glass6854f872014-11-14 20:56:33 -070037
Bin Meng68769eb2017-04-21 07:24:46 -070038#ifdef CONFIG_X86
39#include <asm/acpi_s3.h>
40DECLARE_GLOBAL_DATA_PTR;
41#endif
42
Simon Glass3f4e1e82015-11-29 13:17:57 -070043__weak bool board_should_run_oprom(struct udevice *dev)
Simon Glass6854f872014-11-14 20:56:33 -070044{
Bin Meng68769eb2017-04-21 07:24:46 -070045#if defined(CONFIG_X86) && defined(CONFIG_HAVE_ACPI_RESUME)
46 if (gd->arch.prev_sleep_state == ACPI_S3) {
47 if (IS_ENABLED(CONFIG_S3_VGA_ROM_RUN))
48 return true;
49 else
50 return false;
51 }
52#endif
53
Simon Glass6854f872014-11-14 20:56:33 -070054 return true;
55}
56
Bin Mengf698baa2016-06-14 02:02:40 -070057__weak bool board_should_load_oprom(struct udevice *dev)
Simon Glass6854f872014-11-14 20:56:33 -070058{
Bin Mengc0aea6b2016-06-14 02:02:39 -070059 return true;
Simon Glass6854f872014-11-14 20:56:33 -070060}
61
62__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
63{
64 return vendev;
65}
66
Simon Glass3f4e1e82015-11-29 13:17:57 -070067static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
Simon Glass6854f872014-11-14 20:56:33 -070068{
Simon Glass3f4e1e82015-11-29 13:17:57 -070069 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
Simon Glass6854f872014-11-14 20:56:33 -070070 struct pci_rom_header *rom_header;
71 struct pci_rom_data *rom_data;
Simon Glass40305242014-12-29 19:32:23 -070072 u16 rom_vendor, rom_device;
Bin Mengd57c2f22015-04-24 15:48:03 +080073 u32 rom_class;
Simon Glass6854f872014-11-14 20:56:33 -070074 u32 vendev;
75 u32 mapped_vendev;
76 u32 rom_address;
77
Simon Glass3f4e1e82015-11-29 13:17:57 -070078 vendev = pplat->vendor << 16 | pplat->device;
Simon Glass6854f872014-11-14 20:56:33 -070079 mapped_vendev = board_map_oprom_vendev(vendev);
80 if (vendev != mapped_vendev)
81 debug("Device ID mapped to %#08x\n", mapped_vendev);
82
Bin Meng786a08e2015-07-06 16:31:33 +080083#ifdef CONFIG_VGA_BIOS_ADDR
84 rom_address = CONFIG_VGA_BIOS_ADDR;
Simon Glass6854f872014-11-14 20:56:33 -070085#else
Simon Glass4a2708a2015-01-14 21:37:04 -070086
Simon Glass3f4e1e82015-11-29 13:17:57 -070087 dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
Simon Glass6854f872014-11-14 20:56:33 -070088 if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
89 debug("%s: rom_address=%x\n", __func__, rom_address);
90 return -ENOENT;
91 }
92
93 /* Enable expansion ROM address decoding. */
Simon Glass3f4e1e82015-11-29 13:17:57 -070094 dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
95 rom_address | PCI_ROM_ADDRESS_ENABLE);
Simon Glass6854f872014-11-14 20:56:33 -070096#endif
97 debug("Option ROM address %x\n", rom_address);
Minghuan Lianef2d17f2015-01-22 13:21:55 +080098 rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
Simon Glass6854f872014-11-14 20:56:33 -070099
100 debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700101 le16_to_cpu(rom_header->signature),
102 rom_header->size * 512, le16_to_cpu(rom_header->data));
Simon Glass6854f872014-11-14 20:56:33 -0700103
Simon Glass40305242014-12-29 19:32:23 -0700104 if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
Simon Glass6854f872014-11-14 20:56:33 -0700105 printf("Incorrect expansion ROM header signature %04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700106 le16_to_cpu(rom_header->signature));
Bin Mengf110da92015-07-08 13:06:41 +0800107#ifndef CONFIG_VGA_BIOS_ADDR
108 /* Disable expansion ROM address decoding */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700109 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
Bin Mengf110da92015-07-08 13:06:41 +0800110#endif
Simon Glass6854f872014-11-14 20:56:33 -0700111 return -EINVAL;
112 }
113
Simon Glass40305242014-12-29 19:32:23 -0700114 rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
115 rom_vendor = le16_to_cpu(rom_data->vendor);
116 rom_device = le16_to_cpu(rom_data->device);
Simon Glass6854f872014-11-14 20:56:33 -0700117
118 debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
Simon Glass40305242014-12-29 19:32:23 -0700119 rom_vendor, rom_device);
Simon Glass6854f872014-11-14 20:56:33 -0700120
121 /* If the device id is mapped, a mismatch is expected */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700122 if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
Simon Glass6854f872014-11-14 20:56:33 -0700123 (vendev == mapped_vendev)) {
124 printf("ID mismatch: vendor ID %04x, device ID %04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700125 rom_vendor, rom_device);
Simon Glassc5caba02014-12-29 19:32:27 -0700126 /* Continue anyway */
Simon Glass6854f872014-11-14 20:56:33 -0700127 }
128
Bin Mengd57c2f22015-04-24 15:48:03 +0800129 rom_class = (le16_to_cpu(rom_data->class_hi) << 8) | rom_data->class_lo;
130 debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
131 rom_class, rom_data->type);
Simon Glass6854f872014-11-14 20:56:33 -0700132
Simon Glass3f4e1e82015-11-29 13:17:57 -0700133 if (pplat->class != rom_class) {
Bin Mengd57c2f22015-04-24 15:48:03 +0800134 debug("Class Code mismatch ROM %06x, dev %06x\n",
Simon Glass3f4e1e82015-11-29 13:17:57 -0700135 rom_class, pplat->class);
Simon Glass6854f872014-11-14 20:56:33 -0700136 }
137 *hdrp = rom_header;
138
139 return 0;
140}
141
Simon Glassd830b152016-01-15 05:23:22 -0700142/**
143 * pci_rom_load() - Load a ROM image and return a pointer to it
144 *
145 * @rom_header: Pointer to ROM image
146 * @ram_headerp: Returns a pointer to the image in RAM
147 * @allocedp: Returns true if @ram_headerp was allocated and needs
148 * to be freed
149 * @return 0 if OK, -ve on error. Note that @allocedp is set up regardless of
150 * the error state. Even if this function returns an error, it may have
151 * allocated memory.
152 */
153static int pci_rom_load(struct pci_rom_header *rom_header,
154 struct pci_rom_header **ram_headerp, bool *allocedp)
Simon Glass6854f872014-11-14 20:56:33 -0700155{
156 struct pci_rom_data *rom_data;
157 unsigned int rom_size;
158 unsigned int image_size = 0;
159 void *target;
160
Simon Glassd830b152016-01-15 05:23:22 -0700161 *allocedp = false;
Simon Glass6854f872014-11-14 20:56:33 -0700162 do {
163 /* Get next image, until we see an x86 version */
164 rom_header = (struct pci_rom_header *)((void *)rom_header +
165 image_size);
166
167 rom_data = (struct pci_rom_data *)((void *)rom_header +
Simon Glass40305242014-12-29 19:32:23 -0700168 le16_to_cpu(rom_header->data));
Simon Glass6854f872014-11-14 20:56:33 -0700169
Simon Glass40305242014-12-29 19:32:23 -0700170 image_size = le16_to_cpu(rom_data->ilen) * 512;
171 } while ((rom_data->type != 0) && (rom_data->indicator == 0));
Simon Glass6854f872014-11-14 20:56:33 -0700172
173 if (rom_data->type != 0)
174 return -EACCES;
175
176 rom_size = rom_header->size * 512;
177
Simon Glassbdc88d42014-12-29 19:32:24 -0700178#ifdef PCI_VGA_RAM_IMAGE_START
Simon Glass6854f872014-11-14 20:56:33 -0700179 target = (void *)PCI_VGA_RAM_IMAGE_START;
Simon Glassbdc88d42014-12-29 19:32:24 -0700180#else
181 target = (void *)malloc(rom_size);
182 if (!target)
183 return -ENOMEM;
Simon Glassd830b152016-01-15 05:23:22 -0700184 *allocedp = true;
Simon Glassbdc88d42014-12-29 19:32:24 -0700185#endif
Simon Glass6854f872014-11-14 20:56:33 -0700186 if (target != rom_header) {
Simon Glassfba7eac2015-01-01 16:18:01 -0700187 ulong start = get_timer(0);
188
Simon Glass6854f872014-11-14 20:56:33 -0700189 debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
190 rom_header, target, rom_size);
191 memcpy(target, rom_header, rom_size);
192 if (memcmp(target, rom_header, rom_size)) {
193 printf("VGA ROM copy failed\n");
194 return -EFAULT;
195 }
Simon Glassfba7eac2015-01-01 16:18:01 -0700196 debug("Copy took %lums\n", get_timer(start));
Simon Glass6854f872014-11-14 20:56:33 -0700197 }
198 *ram_headerp = target;
199
200 return 0;
201}
202
Bin Meng153e1dd2015-08-13 00:29:16 -0700203struct vbe_mode_info mode_info;
Simon Glass6854f872014-11-14 20:56:33 -0700204
205int vbe_get_video_info(struct graphic_device *gdev)
206{
207#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE
208 struct vesa_mode_info *vesa = &mode_info.vesa;
209
210 gdev->winSizeX = vesa->x_resolution;
211 gdev->winSizeY = vesa->y_resolution;
212
213 gdev->plnSizeX = vesa->x_resolution;
214 gdev->plnSizeY = vesa->y_resolution;
215
216 gdev->gdfBytesPP = vesa->bits_per_pixel / 8;
217
218 switch (vesa->bits_per_pixel) {
Jian Luo0e98a142015-07-06 16:31:29 +0800219 case 32:
Simon Glass6854f872014-11-14 20:56:33 -0700220 case 24:
221 gdev->gdfIndex = GDF_32BIT_X888RGB;
222 break;
223 case 16:
224 gdev->gdfIndex = GDF_16BIT_565RGB;
225 break;
226 default:
227 gdev->gdfIndex = GDF__8BIT_INDEX;
228 break;
229 }
230
231 gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
232 gdev->pciBase = vesa->phys_base_ptr;
233
234 gdev->frameAdrs = vesa->phys_base_ptr;
235 gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution;
236
237 gdev->vprBase = vesa->phys_base_ptr;
238 gdev->cprBase = vesa->phys_base_ptr;
239
Simon Glass23609c72015-01-01 16:18:00 -0700240 return gdev->winSizeX ? 0 : -ENOSYS;
Simon Glass6854f872014-11-14 20:56:33 -0700241#else
242 return -ENOSYS;
243#endif
244}
245
Bin Menga4520022015-07-06 16:31:36 +0800246void setup_video(struct screen_info *screen_info)
247{
Bin Menga4520022015-07-06 16:31:36 +0800248 struct vesa_mode_info *vesa = &mode_info.vesa;
249
Bin Meng1e7a0472015-07-30 03:49:13 -0700250 /* Sanity test on VESA parameters */
251 if (!vesa->x_resolution || !vesa->y_resolution)
252 return;
253
Bin Menga4520022015-07-06 16:31:36 +0800254 screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB;
255
256 screen_info->lfb_width = vesa->x_resolution;
257 screen_info->lfb_height = vesa->y_resolution;
258 screen_info->lfb_depth = vesa->bits_per_pixel;
259 screen_info->lfb_linelength = vesa->bytes_per_scanline;
260 screen_info->lfb_base = vesa->phys_base_ptr;
261 screen_info->lfb_size =
262 ALIGN(screen_info->lfb_linelength * screen_info->lfb_height,
263 65536);
264 screen_info->lfb_size >>= 16;
265 screen_info->red_size = vesa->red_mask_size;
266 screen_info->red_pos = vesa->red_mask_pos;
267 screen_info->green_size = vesa->green_mask_size;
268 screen_info->green_pos = vesa->green_mask_pos;
269 screen_info->blue_size = vesa->blue_mask_size;
270 screen_info->blue_pos = vesa->blue_mask_pos;
271 screen_info->rsvd_size = vesa->reserved_mask_size;
272 screen_info->rsvd_pos = vesa->reserved_mask_pos;
Bin Menga4520022015-07-06 16:31:36 +0800273}
274
Simon Glass3f4e1e82015-11-29 13:17:57 -0700275int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
276 int exec_method)
Simon Glass6854f872014-11-14 20:56:33 -0700277{
Simon Glass3f4e1e82015-11-29 13:17:57 -0700278 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
Andreas Bießmanned488992016-02-16 23:29:31 +0100279 struct pci_rom_header *rom = NULL, *ram = NULL;
Simon Glass6854f872014-11-14 20:56:33 -0700280 int vesa_mode = -1;
Simon Glassd830b152016-01-15 05:23:22 -0700281 bool emulate, alloced;
Simon Glass6854f872014-11-14 20:56:33 -0700282 int ret;
283
284 /* Only execute VGA ROMs */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700285 if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
286 debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
Simon Glass6854f872014-11-14 20:56:33 -0700287 PCI_CLASS_DISPLAY_VGA);
288 return -ENODEV;
289 }
290
Bin Mengf698baa2016-06-14 02:02:40 -0700291 if (!board_should_load_oprom(dev))
Simon Glass6854f872014-11-14 20:56:33 -0700292 return -ENXIO;
293
Simon Glass3f4e1e82015-11-29 13:17:57 -0700294 ret = pci_rom_probe(dev, &rom);
Simon Glass6854f872014-11-14 20:56:33 -0700295 if (ret)
296 return ret;
297
Simon Glassd830b152016-01-15 05:23:22 -0700298 ret = pci_rom_load(rom, &ram, &alloced);
Simon Glass6854f872014-11-14 20:56:33 -0700299 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700300 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700301
Simon Glassd830b152016-01-15 05:23:22 -0700302 if (!board_should_run_oprom(dev)) {
303 ret = -ENXIO;
304 goto err;
305 }
Simon Glass6854f872014-11-14 20:56:33 -0700306
307#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
308 defined(CONFIG_FRAMEBUFFER_VESA_MODE)
309 vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
310#endif
Simon Glass9a99caf2015-01-01 16:18:05 -0700311 debug("Selected vesa mode %#x\n", vesa_mode);
Simon Glassbc17d8f2015-01-27 22:13:34 -0700312
313 if (exec_method & PCI_ROM_USE_NATIVE) {
314#ifdef CONFIG_X86
315 emulate = false;
316#else
317 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
318 printf("BIOS native execution is only available on x86\n");
Simon Glassd830b152016-01-15 05:23:22 -0700319 ret = -ENOSYS;
320 goto err;
Simon Glassbc17d8f2015-01-27 22:13:34 -0700321 }
322 emulate = true;
323#endif
324 } else {
325#ifdef CONFIG_BIOSEMU
326 emulate = true;
327#else
328 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
329 printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
Simon Glassd830b152016-01-15 05:23:22 -0700330 ret = -ENOSYS;
331 goto err;
Simon Glassbc17d8f2015-01-27 22:13:34 -0700332 }
333 emulate = false;
334#endif
335 }
336
Simon Glass6854f872014-11-14 20:56:33 -0700337 if (emulate) {
338#ifdef CONFIG_BIOSEMU
339 BE_VGAInfo *info;
340
Simon Glass72826722016-01-17 16:11:09 -0700341 ret = biosemu_setup(dev, &info);
Simon Glass6854f872014-11-14 20:56:33 -0700342 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700343 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700344 biosemu_set_interrupt_handler(0x15, int15_handler);
Simon Glass72826722016-01-17 16:11:09 -0700345 ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
346 true, vesa_mode, &mode_info);
Simon Glass6854f872014-11-14 20:56:33 -0700347 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700348 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700349#endif
350 } else {
Simon Glass05cbd982017-01-16 07:04:09 -0700351#if defined(CONFIG_X86) && CONFIG_IS_ENABLED(X86_32BIT_INIT)
Simon Glass6854f872014-11-14 20:56:33 -0700352 bios_set_interrupt_handler(0x15, int15_handler);
353
Simon Glass8beb0bd2015-11-29 13:17:58 -0700354 bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
355 &mode_info);
Simon Glass6854f872014-11-14 20:56:33 -0700356#endif
357 }
Simon Glass9a99caf2015-01-01 16:18:05 -0700358 debug("Final vesa mode %#x\n", mode_info.video_mode);
Simon Glassd830b152016-01-15 05:23:22 -0700359 ret = 0;
Simon Glass6854f872014-11-14 20:56:33 -0700360
Simon Glassd830b152016-01-15 05:23:22 -0700361err:
362 if (alloced)
363 free(ram);
364 return ret;
Simon Glass6854f872014-11-14 20:56:33 -0700365}
Simon Glassee87ee82016-10-05 20:42:17 -0600366
367#ifdef CONFIG_DM_VIDEO
Bin Meng5f6ad022016-10-09 04:14:15 -0700368int vbe_setup_video_priv(struct vesa_mode_info *vesa,
369 struct video_priv *uc_priv,
370 struct video_uc_platdata *plat)
Simon Glassee87ee82016-10-05 20:42:17 -0600371{
372 if (!vesa->x_resolution)
373 return -ENXIO;
374 uc_priv->xsize = vesa->x_resolution;
375 uc_priv->ysize = vesa->y_resolution;
376 switch (vesa->bits_per_pixel) {
377 case 32:
378 case 24:
379 uc_priv->bpix = VIDEO_BPP32;
380 break;
381 case 16:
382 uc_priv->bpix = VIDEO_BPP16;
383 break;
384 default:
385 return -EPROTONOSUPPORT;
386 }
387 plat->base = vesa->phys_base_ptr;
388 plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
389
390 return 0;
391}
392
393int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
394{
395 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
396 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
397 int ret;
398
Bin Mengf0920e42016-10-09 04:14:12 -0700399 printf("Video: ");
400
Simon Glassee87ee82016-10-05 20:42:17 -0600401 /* If we are running from EFI or coreboot, this can't work */
Bin Mengf0920e42016-10-09 04:14:12 -0700402 if (!ll_boot_init()) {
403 printf("Not available (previous bootloader prevents it)\n");
Simon Glassee87ee82016-10-05 20:42:17 -0600404 return -EPERM;
Bin Mengf0920e42016-10-09 04:14:12 -0700405 }
Simon Glassee87ee82016-10-05 20:42:17 -0600406 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
407 ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
408 PCI_ROM_ALLOW_FALLBACK);
409 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
410 if (ret) {
411 debug("failed to run video BIOS: %d\n", ret);
412 return ret;
413 }
414
415 ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat);
416 if (ret) {
417 debug("No video mode configured\n");
418 return ret;
419 }
420
Bin Mengf0920e42016-10-09 04:14:12 -0700421 printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
422 mode_info.vesa.bits_per_pixel);
423
Simon Glassee87ee82016-10-05 20:42:17 -0600424 return 0;
425}
426#endif