Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| 4 | * |
| 5 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <asm/arch/clock.h> |
| 9 | #include <asm/arch/iomux.h> |
Peng Fan | e7d3b21 | 2015-08-17 16:11:05 +0800 | [diff] [blame] | 10 | #include <asm/arch/crm_regs.h> |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 11 | #include <asm/arch/imx-regs.h> |
Peng Fan | e7d3b21 | 2015-08-17 16:11:05 +0800 | [diff] [blame] | 12 | #include <asm/arch/mx6-ddr.h> |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 13 | #include <asm/arch/mx6-pins.h> |
| 14 | #include <asm/arch/sys_proto.h> |
| 15 | #include <asm/gpio.h> |
Stefano Babic | 552a848 | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 16 | #include <asm/mach-imx/iomux-v3.h> |
| 17 | #include <asm/mach-imx/mxc_i2c.h> |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 18 | #include <asm/io.h> |
Alexey Brodkin | 1ace402 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 19 | #include <linux/sizes.h> |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 20 | #include <common.h> |
Yangbo Lu | e37ac71 | 2019-06-21 11:42:28 +0800 | [diff] [blame] | 21 | #include <fsl_esdhc_imx.h> |
Peng Fan | af38bf6 | 2015-02-12 09:36:29 +0800 | [diff] [blame] | 22 | #include <i2c.h> |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 23 | #include <mmc.h> |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 24 | #include <netdev.h> |
Peng Fan | af38bf6 | 2015-02-12 09:36:29 +0800 | [diff] [blame] | 25 | #include <power/pmic.h> |
| 26 | #include <power/pfuze100_pmic.h> |
| 27 | #include "../common/pfuze.h" |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 28 | |
| 29 | DECLARE_GLOBAL_DATA_PTR; |
| 30 | |
Benoît Thébaudeau | 7e2173c | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 31 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 32 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 33 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 34 | |
Benoît Thébaudeau | 7e2173c | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 35 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ |
| 36 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 37 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 38 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 39 | #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 40 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| 41 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 42 | |
Fabio Estevam | 16edd34 | 2015-02-28 14:25:46 -0300 | [diff] [blame] | 43 | #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 44 | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ |
| 45 | PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ |
| 46 | PAD_CTL_SRE_FAST) |
| 47 | |
Fabio Estevam | ae765f3 | 2016-03-11 10:50:22 -0300 | [diff] [blame] | 48 | #define ETH_PHY_POWER IMX_GPIO_NR(4, 21) |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 49 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 50 | int dram_init(void) |
| 51 | { |
Vanessa Maegima | 8259e9c | 2016-06-09 15:28:31 -0300 | [diff] [blame] | 52 | gd->ram_size = imx_ddr_size(); |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 53 | |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | static iomux_v3_cfg_t const uart1_pads[] = { |
| 58 | MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 59 | MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 60 | }; |
| 61 | |
Tom Rini | 61ebeb9 | 2017-05-08 22:14:23 -0400 | [diff] [blame] | 62 | #ifdef CONFIG_SPL_BUILD |
Ye.Li | 36255d6 | 2014-10-30 18:30:54 +0800 | [diff] [blame] | 63 | static iomux_v3_cfg_t const usdhc1_pads[] = { |
| 64 | /* 8 bit SD */ |
| 65 | MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 66 | MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 67 | MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 68 | MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 69 | MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 70 | MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 71 | MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 72 | MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 73 | MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 74 | MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 75 | |
| 76 | /*CD pin*/ |
| 77 | MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 78 | }; |
| 79 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 80 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
| 81 | MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 82 | MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 83 | MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 84 | MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 85 | MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 86 | MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
Ye.Li | 36255d6 | 2014-10-30 18:30:54 +0800 | [diff] [blame] | 87 | |
| 88 | /*CD pin*/ |
| 89 | MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 90 | }; |
| 91 | |
| 92 | static iomux_v3_cfg_t const usdhc3_pads[] = { |
| 93 | MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 94 | MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 95 | MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 96 | MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 97 | MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 98 | MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 99 | |
| 100 | /*CD pin*/ |
| 101 | MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 102 | }; |
Tom Rini | 61ebeb9 | 2017-05-08 22:14:23 -0400 | [diff] [blame] | 103 | #endif |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 104 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 105 | static iomux_v3_cfg_t const fec_pads[] = { |
| 106 | MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 107 | MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 108 | MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 109 | MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 110 | MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 111 | MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 112 | MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 113 | MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 114 | MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 115 | MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 116 | MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 117 | }; |
| 118 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 119 | static void setup_iomux_uart(void) |
| 120 | { |
| 121 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 122 | } |
| 123 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 124 | static void setup_iomux_fec(void) |
| 125 | { |
| 126 | imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
| 127 | |
Fabio Estevam | ae765f3 | 2016-03-11 10:50:22 -0300 | [diff] [blame] | 128 | /* Power up LAN8720 PHY */ |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 129 | gpio_request(ETH_PHY_POWER, "eth_pwr"); |
Fabio Estevam | ae765f3 | 2016-03-11 10:50:22 -0300 | [diff] [blame] | 130 | gpio_direction_output(ETH_PHY_POWER , 1); |
| 131 | udelay(15000); |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 132 | } |
| 133 | |
Peng Fan | fb0d042 | 2016-01-28 16:51:27 +0800 | [diff] [blame] | 134 | int board_mmc_get_env_dev(int devno) |
| 135 | { |
| 136 | return devno; |
| 137 | } |
| 138 | |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 139 | #ifdef CONFIG_DM_PMIC_PFUZE100 |
Peng Fan | af38bf6 | 2015-02-12 09:36:29 +0800 | [diff] [blame] | 140 | int power_init_board(void) |
| 141 | { |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 142 | struct udevice *dev; |
| 143 | int ret; |
| 144 | u32 dev_id, rev_id, i; |
| 145 | u32 switch_num = 6; |
| 146 | u32 offset = PFUZE100_SW1CMODE; |
Peng Fan | af38bf6 | 2015-02-12 09:36:29 +0800 | [diff] [blame] | 147 | |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 148 | ret = pmic_get("pfuze100", &dev); |
| 149 | if (ret == -ENODEV) |
| 150 | return 0; |
Peng Fan | af38bf6 | 2015-02-12 09:36:29 +0800 | [diff] [blame] | 151 | |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 152 | if (ret != 0) |
| 153 | return ret; |
| 154 | |
| 155 | dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); |
| 156 | rev_id = pmic_reg_read(dev, PFUZE100_REVID); |
| 157 | printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); |
| 158 | |
| 159 | /* set SW1AB staby volatage 0.975V */ |
| 160 | pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); |
| 161 | |
| 162 | /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ |
| 163 | pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); |
| 164 | |
| 165 | /* set SW1C staby volatage 0.975V */ |
| 166 | pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); |
| 167 | |
| 168 | /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ |
| 169 | pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); |
| 170 | |
| 171 | /* Init mode to APS_PFM */ |
| 172 | pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); |
| 173 | |
| 174 | for (i = 0; i < switch_num - 1; i++) |
| 175 | pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); |
| 176 | |
| 177 | return 0; |
Peng Fan | af38bf6 | 2015-02-12 09:36:29 +0800 | [diff] [blame] | 178 | } |
| 179 | #endif |
| 180 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 181 | #ifdef CONFIG_FEC_MXC |
| 182 | int board_eth_init(bd_t *bis) |
| 183 | { |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 184 | setup_iomux_fec(); |
| 185 | |
Fabio Estevam | 12c20c0 | 2014-01-04 17:36:33 -0200 | [diff] [blame] | 186 | return cpu_eth_init(bis); |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | static int setup_fec(void) |
| 190 | { |
Fabio Estevam | 0a11d6f | 2014-07-09 17:59:54 -0300 | [diff] [blame] | 191 | struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 192 | |
| 193 | /* clear gpr1[14], gpr1[18:17] to select anatop clock */ |
| 194 | clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); |
| 195 | |
Peng Fan | 6d97dc1 | 2015-08-12 17:46:50 +0800 | [diff] [blame] | 196 | return enable_fec_anatop_clock(0, ENET_50MHZ); |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 197 | } |
| 198 | #endif |
| 199 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 200 | int board_early_init_f(void) |
| 201 | { |
| 202 | setup_iomux_uart(); |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 203 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 204 | return 0; |
| 205 | } |
| 206 | |
| 207 | int board_init(void) |
| 208 | { |
| 209 | /* address of boot parameters */ |
| 210 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 211 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 212 | #ifdef CONFIG_FEC_MXC |
| 213 | setup_fec(); |
| 214 | #endif |
Peng Fan | 3b9c1a5 | 2014-11-10 08:50:41 +0800 | [diff] [blame] | 215 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 216 | return 0; |
| 217 | } |
| 218 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 219 | int checkboard(void) |
| 220 | { |
| 221 | puts("Board: MX6SLEVK\n"); |
| 222 | |
| 223 | return 0; |
| 224 | } |
Peng Fan | e7d3b21 | 2015-08-17 16:11:05 +0800 | [diff] [blame] | 225 | |
| 226 | #ifdef CONFIG_SPL_BUILD |
| 227 | #include <spl.h> |
Masahiro Yamada | b08c8c4 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 228 | #include <linux/libfdt.h> |
Peng Fan | e7d3b21 | 2015-08-17 16:11:05 +0800 | [diff] [blame] | 229 | |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 230 | #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) |
| 231 | #define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) |
| 232 | #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) |
| 233 | |
| 234 | static struct fsl_esdhc_cfg usdhc_cfg[3] = { |
| 235 | {USDHC1_BASE_ADDR}, |
| 236 | {USDHC2_BASE_ADDR, 0, 4}, |
| 237 | {USDHC3_BASE_ADDR, 0, 4}, |
| 238 | }; |
| 239 | |
| 240 | int board_mmc_getcd(struct mmc *mmc) |
| 241 | { |
| 242 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 243 | int ret = 0; |
| 244 | |
| 245 | switch (cfg->esdhc_base) { |
| 246 | case USDHC1_BASE_ADDR: |
Fabio Estevam | 40b0dae | 2017-10-10 13:43:42 -0300 | [diff] [blame] | 247 | gpio_request(USDHC1_CD_GPIO, "cd1_gpio"); |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 248 | ret = !gpio_get_value(USDHC1_CD_GPIO); |
| 249 | break; |
| 250 | case USDHC2_BASE_ADDR: |
Fabio Estevam | 40b0dae | 2017-10-10 13:43:42 -0300 | [diff] [blame] | 251 | gpio_request(USDHC2_CD_GPIO, "cd2_gpio"); |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 252 | ret = !gpio_get_value(USDHC2_CD_GPIO); |
| 253 | break; |
| 254 | case USDHC3_BASE_ADDR: |
Fabio Estevam | 40b0dae | 2017-10-10 13:43:42 -0300 | [diff] [blame] | 255 | gpio_request(USDHC3_CD_GPIO, "cd3_gpio"); |
Peng Fan | 001cdbb | 2017-03-04 10:45:44 +0800 | [diff] [blame] | 256 | ret = !gpio_get_value(USDHC3_CD_GPIO); |
| 257 | break; |
| 258 | } |
| 259 | |
| 260 | return ret; |
| 261 | } |
| 262 | |
| 263 | int board_mmc_init(bd_t *bis) |
| 264 | { |
| 265 | struct src *src_regs = (struct src *)SRC_BASE_ADDR; |
| 266 | u32 val; |
| 267 | u32 port; |
| 268 | |
| 269 | val = readl(&src_regs->sbmr1); |
| 270 | |
| 271 | /* Boot from USDHC */ |
| 272 | port = (val >> 11) & 0x3; |
| 273 | switch (port) { |
| 274 | case 0: |
| 275 | imx_iomux_v3_setup_multiple_pads(usdhc1_pads, |
| 276 | ARRAY_SIZE(usdhc1_pads)); |
| 277 | gpio_direction_input(USDHC1_CD_GPIO); |
| 278 | usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; |
| 279 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| 280 | break; |
| 281 | case 1: |
| 282 | imx_iomux_v3_setup_multiple_pads(usdhc2_pads, |
| 283 | ARRAY_SIZE(usdhc2_pads)); |
| 284 | gpio_direction_input(USDHC2_CD_GPIO); |
| 285 | usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; |
| 286 | usdhc_cfg[0].max_bus_width = 4; |
| 287 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 288 | break; |
| 289 | case 2: |
| 290 | imx_iomux_v3_setup_multiple_pads(usdhc3_pads, |
| 291 | ARRAY_SIZE(usdhc3_pads)); |
| 292 | gpio_direction_input(USDHC3_CD_GPIO); |
| 293 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
| 294 | usdhc_cfg[0].max_bus_width = 4; |
| 295 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 296 | break; |
| 297 | } |
| 298 | |
| 299 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| 300 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| 301 | } |
| 302 | |
Peng Fan | e7d3b21 | 2015-08-17 16:11:05 +0800 | [diff] [blame] | 303 | const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = { |
| 304 | .dram_sdqs0 = 0x00003030, |
| 305 | .dram_sdqs1 = 0x00003030, |
| 306 | .dram_sdqs2 = 0x00003030, |
| 307 | .dram_sdqs3 = 0x00003030, |
| 308 | .dram_dqm0 = 0x00000030, |
| 309 | .dram_dqm1 = 0x00000030, |
| 310 | .dram_dqm2 = 0x00000030, |
| 311 | .dram_dqm3 = 0x00000030, |
| 312 | .dram_cas = 0x00000030, |
| 313 | .dram_ras = 0x00000030, |
| 314 | .dram_sdclk_0 = 0x00000028, |
| 315 | .dram_reset = 0x00000030, |
| 316 | .dram_sdba2 = 0x00000000, |
| 317 | .dram_odt0 = 0x00000008, |
| 318 | .dram_odt1 = 0x00000008, |
| 319 | }; |
| 320 | |
| 321 | const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = { |
| 322 | .grp_b0ds = 0x00000030, |
| 323 | .grp_b1ds = 0x00000030, |
| 324 | .grp_b2ds = 0x00000030, |
| 325 | .grp_b3ds = 0x00000030, |
| 326 | .grp_addds = 0x00000030, |
| 327 | .grp_ctlds = 0x00000030, |
| 328 | .grp_ddrmode_ctl = 0x00020000, |
| 329 | .grp_ddrpke = 0x00000000, |
| 330 | .grp_ddrmode = 0x00020000, |
| 331 | .grp_ddr_type = 0x00080000, |
| 332 | }; |
| 333 | |
| 334 | const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
| 335 | .p0_mpdgctrl0 = 0x20000000, |
| 336 | .p0_mpdgctrl1 = 0x00000000, |
| 337 | .p0_mprddlctl = 0x4241444a, |
| 338 | .p0_mpwrdlctl = 0x3030312b, |
| 339 | .mpzqlp2ctl = 0x1b4700c7, |
| 340 | }; |
| 341 | |
| 342 | static struct mx6_lpddr2_cfg mem_ddr = { |
| 343 | .mem_speed = 800, |
| 344 | .density = 4, |
| 345 | .width = 32, |
| 346 | .banks = 8, |
| 347 | .rowaddr = 14, |
| 348 | .coladdr = 10, |
| 349 | .trcd_lp = 2000, |
| 350 | .trppb_lp = 2000, |
| 351 | .trpab_lp = 2250, |
| 352 | .trasmin = 4200, |
| 353 | }; |
| 354 | |
| 355 | static void ccgr_init(void) |
| 356 | { |
| 357 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 358 | |
| 359 | writel(0xFFFFFFFF, &ccm->CCGR0); |
| 360 | writel(0xFFFFFFFF, &ccm->CCGR1); |
| 361 | writel(0xFFFFFFFF, &ccm->CCGR2); |
| 362 | writel(0xFFFFFFFF, &ccm->CCGR3); |
| 363 | writel(0xFFFFFFFF, &ccm->CCGR4); |
| 364 | writel(0xFFFFFFFF, &ccm->CCGR5); |
| 365 | writel(0xFFFFFFFF, &ccm->CCGR6); |
| 366 | |
| 367 | writel(0x00260324, &ccm->cbcmr); |
| 368 | } |
| 369 | |
| 370 | static void spl_dram_init(void) |
| 371 | { |
| 372 | struct mx6_ddr_sysinfo sysinfo = { |
| 373 | .dsize = mem_ddr.width / 32, |
| 374 | .cs_density = 20, |
| 375 | .ncs = 2, |
| 376 | .cs1_mirror = 0, |
| 377 | .walat = 0, |
| 378 | .ralat = 2, |
| 379 | .mif3_mode = 3, |
| 380 | .bi_on = 1, |
| 381 | .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ |
| 382 | .rtt_nom = 0, |
| 383 | .sde_to_rst = 0, /* LPDDR2 does not need this field */ |
| 384 | .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ |
| 385 | .ddr_type = DDR_TYPE_LPDDR2, |
Fabio Estevam | edf0093 | 2016-08-29 20:37:15 -0300 | [diff] [blame] | 386 | .refsel = 0, /* Refresh cycles at 64KHz */ |
| 387 | .refr = 3, /* 4 refresh commands per refresh cycle */ |
Peng Fan | e7d3b21 | 2015-08-17 16:11:05 +0800 | [diff] [blame] | 388 | }; |
| 389 | mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
| 390 | mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
| 391 | } |
| 392 | |
| 393 | void board_init_f(ulong dummy) |
| 394 | { |
| 395 | /* setup AIPS and disable watchdog */ |
| 396 | arch_cpu_init(); |
| 397 | |
| 398 | ccgr_init(); |
| 399 | |
| 400 | /* iomux and setup of i2c */ |
| 401 | board_early_init_f(); |
| 402 | |
| 403 | /* setup GP timer */ |
| 404 | timer_init(); |
| 405 | |
| 406 | /* UART clocks enabled and gd valid - init serial console */ |
| 407 | preloader_console_init(); |
| 408 | |
| 409 | /* DDR initialization */ |
| 410 | spl_dram_init(); |
| 411 | |
| 412 | /* Clear the BSS. */ |
| 413 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 414 | |
| 415 | /* load/boot image from boot device */ |
| 416 | board_init_r(NULL, 0); |
| 417 | } |
Peng Fan | e7d3b21 | 2015-08-17 16:11:05 +0800 | [diff] [blame] | 418 | #endif |