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Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +02001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +02006 */
7
8#include <common.h>
9#include <asm/system.h>
R Sricharan96fdbec2013-03-04 20:04:44 +000010#include <asm/cache.h>
11#include <linux/compiler.h>
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020012
Aneesh Ve47f2db2011-06-16 23:30:48 +000013#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
Heiko Schocher880eff52010-09-17 13:10:29 +020014
Heiko Schocher880eff52010-09-17 13:10:29 +020015DECLARE_GLOBAL_DATA_PTR;
16
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020017__weak void arm_init_before_mmu(void)
Aneesh Vc2dd0d42011-06-16 23:30:49 +000018{
19}
Aneesh Vc2dd0d42011-06-16 23:30:49 +000020
R Sricharande63ac22013-03-04 20:04:45 +000021__weak void arm_init_domains(void)
22{
23}
24
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020025static void cp_delay (void)
26{
27 volatile int i;
28
29 /* copro seems to need some delay between reading and writing */
30 for (i = 0; i < 100; i++)
31 nop();
Heiko Schocher880eff52010-09-17 13:10:29 +020032 asm volatile("" : : : "memory");
33}
34
Simon Glass0dde7f52012-10-17 13:24:53 +000035void set_section_dcache(int section, enum dcache_option option)
Heiko Schocherf1d2b312010-09-17 13:10:39 +020036{
Simon Glass34fd5d22012-12-13 20:48:39 +000037 u32 *page_table = (u32 *)gd->arch.tlb_addr;
Simon Glass0dde7f52012-10-17 13:24:53 +000038 u32 value;
39
40 value = (section << MMU_SECTION_SHIFT) | (3 << 10);
41 value |= option;
42 page_table[section] = value;
43}
44
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020045__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
Simon Glass0dde7f52012-10-17 13:24:53 +000046{
47 debug("%s: Warning: not implemented\n", __func__);
48}
49
Thierry Reding25026fa2014-08-26 17:34:21 +020050void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
Simon Glass0dde7f52012-10-17 13:24:53 +000051 enum dcache_option option)
52{
Simon Glass34fd5d22012-12-13 20:48:39 +000053 u32 *page_table = (u32 *)gd->arch.tlb_addr;
Thierry Reding25026fa2014-08-26 17:34:21 +020054 unsigned long upto, end;
Simon Glass0dde7f52012-10-17 13:24:53 +000055
56 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
57 start = start >> MMU_SECTION_SHIFT;
Thierry Reding25026fa2014-08-26 17:34:21 +020058 debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
Simon Glass0dde7f52012-10-17 13:24:53 +000059 option);
60 for (upto = start; upto < end; upto++)
61 set_section_dcache(upto, option);
62 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
63}
64
R Sricharan96fdbec2013-03-04 20:04:44 +000065__weak void dram_bank_mmu_setup(int bank)
Simon Glass0dde7f52012-10-17 13:24:53 +000066{
Heiko Schocherf1d2b312010-09-17 13:10:39 +020067 bd_t *bd = gd->bd;
68 int i;
69
70 debug("%s: bank: %d\n", __func__, bank);
71 for (i = bd->bi_dram[bank].start >> 20;
Marek Vasut221a49d2014-08-04 01:45:46 +020072 i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
Heiko Schocherf1d2b312010-09-17 13:10:39 +020073 i++) {
Simon Glass0dde7f52012-10-17 13:24:53 +000074#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
75 set_section_dcache(i, DCACHE_WRITETHROUGH);
Marek Vasutff7e9702014-09-15 02:44:36 +020076#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
77 set_section_dcache(i, DCACHE_WRITEALLOC);
Simon Glass0dde7f52012-10-17 13:24:53 +000078#else
79 set_section_dcache(i, DCACHE_WRITEBACK);
80#endif
Heiko Schocherf1d2b312010-09-17 13:10:39 +020081 }
82}
Heiko Schocherf1d2b312010-09-17 13:10:39 +020083
84/* to activate the MMU we need to set up virtual memory: use 1M areas */
Heiko Schocher880eff52010-09-17 13:10:29 +020085static inline void mmu_setup(void)
86{
Heiko Schocherf1d2b312010-09-17 13:10:39 +020087 int i;
Heiko Schocher880eff52010-09-17 13:10:29 +020088 u32 reg;
89
Aneesh Vc2dd0d42011-06-16 23:30:49 +000090 arm_init_before_mmu();
Heiko Schocher880eff52010-09-17 13:10:29 +020091 /* Set up an identity-mapping for all 4GB, rw for everyone */
92 for (i = 0; i < 4096; i++)
Simon Glass0dde7f52012-10-17 13:24:53 +000093 set_section_dcache(i, DCACHE_OFF);
Heiko Schocherf1d2b312010-09-17 13:10:39 +020094
Heiko Schocherf1d2b312010-09-17 13:10:39 +020095 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
96 dram_bank_mmu_setup(i);
97 }
Heiko Schocher880eff52010-09-17 13:10:29 +020098
Marek Vasuta592e6f2015-12-29 19:44:01 +010099#ifdef CONFIG_CPU_V7
Bryan Brinsko97840b52015-03-24 11:25:12 -0500100 /* Set TTBR0 */
101 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
102#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
103 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
104#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
105 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
106#else
107 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
108#endif
109 asm volatile("mcr p15, 0, %0, c2, c0, 0"
110 : : "r" (reg) : "memory");
111#else
Heiko Schocher880eff52010-09-17 13:10:29 +0200112 /* Copy the page table address to cp15 */
113 asm volatile("mcr p15, 0, %0, c2, c0, 0"
Simon Glass34fd5d22012-12-13 20:48:39 +0000114 : : "r" (gd->arch.tlb_addr) : "memory");
Bryan Brinsko97840b52015-03-24 11:25:12 -0500115#endif
Heiko Schocher880eff52010-09-17 13:10:29 +0200116 /* Set the access control to all-supervisor */
117 asm volatile("mcr p15, 0, %0, c3, c0, 0"
118 : : "r" (~0));
R Sricharande63ac22013-03-04 20:04:45 +0000119
120 arm_init_domains();
121
Heiko Schocher880eff52010-09-17 13:10:29 +0200122 /* and enable the mmu */
123 reg = get_cr(); /* get control reg. */
124 cp_delay();
125 set_cr(reg | CR_M);
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200126}
127
Aneesh Ve05f0072011-06-16 23:30:50 +0000128static int mmu_enabled(void)
129{
130 return get_cr() & CR_M;
131}
132
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200133/* cache_bit must be either CR_I or CR_C */
134static void cache_enable(uint32_t cache_bit)
135{
136 uint32_t reg;
137
Heiko Schocher880eff52010-09-17 13:10:29 +0200138 /* The data cache is not active unless the mmu is enabled too */
Aneesh Ve05f0072011-06-16 23:30:50 +0000139 if ((cache_bit == CR_C) && !mmu_enabled())
Heiko Schocher880eff52010-09-17 13:10:29 +0200140 mmu_setup();
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200141 reg = get_cr(); /* get control reg. */
142 cp_delay();
143 set_cr(reg | cache_bit);
144}
145
146/* cache_bit must be either CR_I or CR_C */
147static void cache_disable(uint32_t cache_bit)
148{
149 uint32_t reg;
150
SRICHARAN Rd702b082012-05-16 23:52:54 +0000151 reg = get_cr();
152 cp_delay();
153
Heiko Schocher880eff52010-09-17 13:10:29 +0200154 if (cache_bit == CR_C) {
Heiko Schocherf1d2b312010-09-17 13:10:39 +0200155 /* if cache isn;t enabled no need to disable */
Heiko Schocherf1d2b312010-09-17 13:10:39 +0200156 if ((reg & CR_C) != CR_C)
157 return;
Heiko Schocher880eff52010-09-17 13:10:29 +0200158 /* if disabling data cache, disable mmu too */
159 cache_bit |= CR_M;
Heiko Schocher880eff52010-09-17 13:10:29 +0200160 }
Arun Mankuzhi44df5e82012-11-30 13:01:14 +0000161 reg = get_cr();
162 cp_delay();
163 if (cache_bit == (CR_C | CR_M))
164 flush_dcache_all();
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200165 set_cr(reg & ~cache_bit);
166}
167#endif
168
Aneesh Ve47f2db2011-06-16 23:30:48 +0000169#ifdef CONFIG_SYS_ICACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200170void icache_enable (void)
171{
172 return;
173}
174
175void icache_disable (void)
176{
177 return;
178}
179
180int icache_status (void)
181{
182 return 0; /* always off */
183}
184#else
185void icache_enable(void)
186{
187 cache_enable(CR_I);
188}
189
190void icache_disable(void)
191{
192 cache_disable(CR_I);
193}
194
195int icache_status(void)
196{
197 return (get_cr() & CR_I) != 0;
198}
199#endif
200
Aneesh Ve47f2db2011-06-16 23:30:48 +0000201#ifdef CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +0200202void dcache_enable (void)
203{
204 return;
205}
206
207void dcache_disable (void)
208{
209 return;
210}
211
212int dcache_status (void)
213{
214 return 0; /* always off */
215}
216#else
217void dcache_enable(void)
218{
219 cache_enable(CR_C);
220}
221
222void dcache_disable(void)
223{
224 cache_disable(CR_C);
225}
226
227int dcache_status(void)
228{
229 return (get_cr() & CR_C) != 0;
230}
231#endif