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wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf4675562002-10-02 14:20:15 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
21#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
22
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenkf4675562002-10-02 14:20:15 +000025#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020026#define CONFIG_SYS_SMC_RXBUFLEN 128
27#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000028#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
29
wdenkae3af052003-08-07 22:18:11 +000030#define CONFIG_BOOTCOUNT_LIMIT
wdenkf4675562002-10-02 14:20:15 +000031
wdenkae3af052003-08-07 22:18:11 +000032#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000033
34#define CONFIG_BOARD_TYPES 1 /* support board types */
35
36#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010037 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk6aff3112002-12-17 01:51:00 +000038 "echo"
wdenkf4675562002-10-02 14:20:15 +000039
40#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000041
42#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000043 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000044 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010045 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000046 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010047 "addip=setenv bootargs ${bootargs} " \
48 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
49 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000050 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000052 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010053 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
54 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000055 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020056 "hostname=TQM860L\0" \
57 "bootfile=TQM860L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020058 "fdt_addr=40040000\0" \
59 "kernel_addr=40060000\0" \
60 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020061 "u-boot=TQM860L/u-image.bin\0" \
62 "load=tftp 200000 ${u-boot}\0" \
63 "update=prot off 40000000 +${filesize};" \
64 "era 40000000 +${filesize};" \
65 "cp.b 200000 40000000 ${filesize};" \
66 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000067 ""
68#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000069
70#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000072
73#undef CONFIG_WATCHDOG /* watchdog disabled */
74
75#define CONFIG_STATUS_LED 1 /* Status LED enabled */
76
77#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
78
Jon Loeliger37d4bb72007-07-09 21:38:02 -050079/*
80 * BOOTP options
81 */
82#define CONFIG_BOOTP_SUBNETMASK
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85#define CONFIG_BOOTP_BOOTPATH
86#define CONFIG_BOOTP_BOOTFILESIZE
87
wdenkf4675562002-10-02 14:20:15 +000088
89#define CONFIG_MAC_PARTITION
90#define CONFIG_DOS_PARTITION
91
92#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
93
Jon Loeliger26946902007-07-04 22:30:50 -050094
95/*
96 * Command line configuration.
97 */
98#include <config_cmd_default.h>
99
100#define CONFIG_CMD_ASKENV
101#define CONFIG_CMD_DATE
102#define CONFIG_CMD_DHCP
103#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100104#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500105#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200106#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500107#define CONFIG_CMD_NFS
108#define CONFIG_CMD_SNTP
109
wdenkf4675562002-10-02 14:20:15 +0000110
wdenk68ceb292004-08-02 21:11:11 +0000111#define CONFIG_NETCONSOLE
112
wdenkf4675562002-10-02 14:20:15 +0000113/*
114 * Miscellaneous configurable options
115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkf4675562002-10-02 14:20:15 +0000117
Wolfgang Denk2751a952006-10-28 02:29:14 +0200118#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf4675562002-10-02 14:20:15 +0000120
Jon Loeliger26946902007-07-04 22:30:50 -0500121#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000123#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000125#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
127#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
131#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000134
wdenkf4675562002-10-02 14:20:15 +0000135/*
136 * Low Level Configuration Settings
137 * (address mappings, register initial values, etc.)
138 * You should know what you are doing if you make changes here.
139 */
140/*-----------------------------------------------------------------------
141 * Internal Memory Mapped Register
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000144
145/*-----------------------------------------------------------------------
146 * Definitions for initial stack pointer and data area (in DPRAM)
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200149#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200150#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000152
153/*-----------------------------------------------------------------------
154 * Start addresses for the final memory configuration
155 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_SDRAM_BASE 0x00000000
159#define CONFIG_SYS_FLASH_BASE 0x40000000
160#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
161#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
162#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000163
164/*
165 * For booting Linux, the board info and command line data
166 * have to be in the first 8 MB of memory, since this is
167 * the maximum mapped by the Linux kernel during initialization.
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000170
171/*-----------------------------------------------------------------------
172 * FLASH organization
173 */
wdenkf4675562002-10-02 14:20:15 +0000174
Martin Krausee318d9e2007-09-27 11:10:08 +0200175/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200177#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
179#define CONFIG_SYS_FLASH_EMPTY_INFO
180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
181#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
182#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000183
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200184#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200185#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
186#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000187
188/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200189#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
190#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200193
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200194#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
195
wdenkf4675562002-10-02 14:20:15 +0000196/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200197 * Dynamic MTD partition support
198 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100199#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200200#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
201#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200202#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
203
204#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
205 "128k(dtb)," \
206 "1664k(kernel)," \
207 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200208 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200209
210/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000211 * Hardware Information Block
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
214#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
215#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000216
217/*-----------------------------------------------------------------------
218 * Cache Configuration
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500221#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000223#endif
224
225/*-----------------------------------------------------------------------
226 * SYPCR - System Protection Control 11-9
227 * SYPCR can only be written once after reset!
228 *-----------------------------------------------------------------------
229 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
230 */
231#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000233 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
234#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000236#endif
237
238/*-----------------------------------------------------------------------
239 * SIUMCR - SIU Module Configuration 11-6
240 *-----------------------------------------------------------------------
241 * PCMCIA config., multi-function pin tri-state
242 */
243#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000245#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000247#endif /* CONFIG_CAN_DRIVER */
248
249/*-----------------------------------------------------------------------
250 * TBSCR - Time Base Status and Control 11-26
251 *-----------------------------------------------------------------------
252 * Clear Reference Interrupt Status, Timebase freezing enabled
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000255
256/*-----------------------------------------------------------------------
257 * RTCSC - Real-Time Clock Status and Control Register 11-27
258 *-----------------------------------------------------------------------
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000261
262/*-----------------------------------------------------------------------
263 * PISCR - Periodic Interrupt Status and Control 11-31
264 *-----------------------------------------------------------------------
265 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000268
269/*-----------------------------------------------------------------------
270 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
271 *-----------------------------------------------------------------------
272 * Reset PLL lock status sticky bit, timer expired status bit and timer
273 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000276
277/*-----------------------------------------------------------------------
278 * SCCR - System Clock and reset Control Register 15-27
279 *-----------------------------------------------------------------------
280 * Set clock output, timebase and RTC source and divider,
281 * power management and some other internal clocks
282 */
283#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000285 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
286 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000287
288/*-----------------------------------------------------------------------
289 * PCMCIA stuff
290 *-----------------------------------------------------------------------
291 *
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
294#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
295#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
296#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
297#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
298#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
299#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
300#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000301
302/*-----------------------------------------------------------------------
303 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
304 *-----------------------------------------------------------------------
305 */
306
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000307#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf4675562002-10-02 14:20:15 +0000308#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
309
310#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
311#undef CONFIG_IDE_LED /* LED for ide not supported */
312#undef CONFIG_IDE_RESET /* reset for ide not supported */
313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
315#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000318
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000320
321/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000323
324/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000326
327/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000329
330/*-----------------------------------------------------------------------
331 *
332 *-----------------------------------------------------------------------
333 *
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000336
337/*
338 * Init Memory Controller:
339 *
340 * BR0/1 and OR0/1 (FLASH)
341 */
342
343#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
344#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
345
346/* used to re-map FLASH both when starting from SRAM or FLASH:
347 * restrict access enough to keep SRAM working (if any)
348 * but not too much to meddle with FLASH accesses
349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
351#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000352
353/*
354 * FLASH timing:
355 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000357 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
360#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
361#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
364#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
365#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000366
367/*
368 * BR2/3 and OR2/3 (SDRAM)
369 *
370 */
371#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
372#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
373#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
374
375/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
379#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000380
381#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
383#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000384#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
386#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
387#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
388#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000389 BR_PS_8 | BR_MS_UPMB | BR_V )
390#endif /* CONFIG_CAN_DRIVER */
391
392/*
393 * Memory Periodic Timer Prescaler
394 *
395 * The Divider for PTA (refresh timer) configuration is based on an
396 * example SDRAM configuration (64 MBit, one bank). The adjustment to
397 * the number of chip selects (NCS) and the actually needed refresh
398 * rate is done by setting MPTPR.
399 *
400 * PTA is calculated from
401 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
402 *
403 * gclk CPU clock (not bus clock!)
404 * Trefresh Refresh cycle * 4 (four word bursts used)
405 *
406 * 4096 Rows from SDRAM example configuration
407 * 1000 factor s -> ms
408 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
409 * 4 Number of refresh cycles per period
410 * 64 Refresh cycle in ms per number of rows
411 * --------------------------------------------
412 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
413 *
414 * 50 MHz => 50.000.000 / Divider = 98
415 * 66 Mhz => 66.000.000 / Divider = 129
416 * 80 Mhz => 80.000.000 / Divider = 156
417 */
wdenke9132ea2004-04-24 23:23:30 +0000418
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
420#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000421
422/*
423 * For 16 MBit, refresh rates could be 31.3 us
424 * (= 64 ms / 2K = 125 / quad bursts).
425 * For a simpler initialization, 15.6 us is used instead.
426 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
428 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000429 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
431#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000432
433/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
435#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000436
437/*
438 * MAMR settings for SDRAM
439 */
440
441/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000443 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
444 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
445/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000447 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
449
wdenkf4675562002-10-02 14:20:15 +0000450#define CONFIG_SCC1_ENET
451#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200452#define CONFIG_ETHPRIME "SCC"
wdenkf4675562002-10-02 14:20:15 +0000453
Heiko Schocher7026ead2010-02-09 15:50:27 +0100454/* pass open firmware flat tree */
455#define CONFIG_OF_LIBFDT 1
456#define CONFIG_OF_BOARD_SETUP 1
457#define CONFIG_HWCONFIG 1
458
wdenkf4675562002-10-02 14:20:15 +0000459#endif /* __CONFIG_H */