blob: f2361560e9ade62c4e3608c954c1dc9b60d8bd3d [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "mpc85xx CPU"
2 depends on MPC85xx
3
4config SYS_CPU
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mpc85xx"
6
Simon Glass230ecd72017-05-17 03:25:15 -06007config CMD_ERRATA
8 bool "Enable the 'errata' command"
9 depends on MPC85xx
10 default y
11 help
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
14
Pali Rohár786d9f12022-05-11 20:57:31 +020015config FSL_PREPBL_ESDHC_BOOT_SECTOR
16 bool "Generate QorIQ pre-PBL eSDHC boot sector"
17 depends on MPC85xx
Marek Behún1e1d12a2022-09-15 16:08:27 +020018 depends on SDCARD
Pali Rohár786d9f12022-05-11 20:57:31 +020019 help
20 With this option final image would have prepended QorIQ pre-PBL eSDHC
21 boot sector suitable for SD card images. This boot sector instruct
22 BootROM to configure L2 SRAM and eSDHC then load image from SD card
23 into L2 SRAM and finally jump to image entry point.
24
25 This is alternative to Freescale boot_format tool, but works only for
26 SD card images and only for L2 SRAM booting. U-Boot images generated
27 with this option should not passed to boot_format tool.
28
29 For other configuration like booting from eSPI or configuring SDRAM
30 please use Freescale boot_format tool without this option. See file
31 doc/README.mpc85xx-sd-spi-boot
32
33config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
34 int "QorIQ pre-PBL eSDHC boot sector start offset"
35 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
36 range 0 23
37 default 0
38 help
39 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
40 24 SD card sectors. Select SD card sector on which final U-Boot
41 image (with this boot sector) would be installed.
42
43 By default first SD card sector (0) is used. But this may be changed
44 to allow installing U-Boot image on some partition (with fixed start
45 sector).
46
47 Please note that any sector on SD card prior this boot sector must
48 not contain ASCII "BOOT" bytes at sector offset 0x40.
49
50config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
51 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
52 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
53 default 1
54 range 1 8388607
55 help
56 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
57 sector on which would be stored raw U-Boot image.
58
59 By default is it second sector (1) which is the first available free
60 sector (on the first sector is stored boot sector). It can be any
61 sector number which offset in bytes can be expressed by 32-bit number.
62
63 In case this final U-Boot image (with this boot sector) is put on
64 the FAT32 partition into reserved boot area, this data sector needs
65 to be at least 2 (third sector) because FAT32 use second sector for
66 its data.
67
Masahiro Yamadadd840582014-07-30 14:08:14 +090068choice
69 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050070 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090071
Masahiro Yamadadd840582014-07-30 14:08:14 +090072config TARGET_SOCRATES
73 bool "Support socrates"
York Sun25cb74b2016-11-15 13:57:15 -080074 select ARCH_MPC8544
Masahiro Yamadadd840582014-07-30 14:08:14 +090075
Masahiro Yamadadd840582014-07-30 14:08:14 +090076config TARGET_P3041DS
77 bool "Support P3041DS"
Masahiro Yamadabb6b1422016-07-25 19:56:03 +090078 select PHYS_64BIT
York Sun5e5fdd22016-11-18 11:20:40 -080079 select ARCH_P3041
Tom Rinie5ec4812017-01-22 19:43:11 -050080 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Tom Riniff4e87c2022-07-31 21:08:29 -040081 select FSL_NGPIXIS
Simon Glass3bf926c2017-06-14 21:28:24 -060082 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +090083 imply PANIC_HANG
Masahiro Yamadadd840582014-07-30 14:08:14 +090084
85config TARGET_P4080DS
86 bool "Support P4080DS"
Masahiro Yamadabb6b1422016-07-25 19:56:03 +090087 select PHYS_64BIT
York Sune71372c2016-11-18 11:24:40 -080088 select ARCH_P4080
Tom Rinie5ec4812017-01-22 19:43:11 -050089 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Tom Riniff4e87c2022-07-31 21:08:29 -040090 select FSL_NGPIXIS
Simon Glass3bf926c2017-06-14 21:28:24 -060091 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +090092 imply PANIC_HANG
Masahiro Yamadadd840582014-07-30 14:08:14 +090093
Masahiro Yamadadd840582014-07-30 14:08:14 +090094config TARGET_P5040DS
95 bool "Support P5040DS"
Masahiro Yamadabb6b1422016-07-25 19:56:03 +090096 select PHYS_64BIT
York Sun95390362016-11-18 11:39:36 -080097 select ARCH_P5040
Tom Rinie5ec4812017-01-22 19:43:11 -050098 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Tom Riniff4e87c2022-07-31 21:08:29 -040099 select FSL_NGPIXIS
100 select SYS_FSL_RAID_ENGINE
Simon Glass3bf926c2017-06-14 21:28:24 -0600101 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900102 imply PANIC_HANG
Masahiro Yamadadd840582014-07-30 14:08:14 +0900103
Masahiro Yamadadd840582014-07-30 14:08:14 +0900104config TARGET_MPC8548CDS
105 bool "Support MPC8548CDS"
York Sun281ed4c2016-11-15 13:52:34 -0800106 select ARCH_MPC8548
Rajesh Bhagatc8c01702021-02-15 09:46:14 +0100107 select FSL_VIA
Tom Riniab92b382021-08-26 11:47:59 -0400108 select SYS_CACHE_SHIFT_5
Masahiro Yamadadd840582014-07-30 14:08:14 +0900109
York Sun76016862016-11-16 13:30:06 -0800110config TARGET_P1010RDB_PA
111 bool "Support P1010RDB_PA"
112 select ARCH_P1010
Tom Rinie5ec4812017-01-22 19:43:11 -0500113 select BOARD_LATE_INIT if CHAIN_OF_TRUST
York Sun76016862016-11-16 13:30:06 -0800114 select SUPPORT_SPL
115 select SUPPORT_TPL
Tom Rini22a22832022-10-28 20:27:00 -0400116 select SYS_L2_SIZE_256KB
Simon Glassa1dc9802017-05-17 03:25:10 -0600117 imply CMD_EEPROM
Simon Glass3bf926c2017-06-14 21:28:24 -0600118 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900119 imply PANIC_HANG
York Sun76016862016-11-16 13:30:06 -0800120
121config TARGET_P1010RDB_PB
122 bool "Support P1010RDB_PB"
York Sun7d5f9f82016-11-16 13:08:52 -0800123 select ARCH_P1010
Tom Rinie5ec4812017-01-22 19:43:11 -0500124 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Masahiro Yamada02627352014-10-20 17:45:56 +0900125 select SUPPORT_SPL
Masahiro Yamadacf6bbe42014-10-20 17:45:57 +0900126 select SUPPORT_TPL
Tom Rini22a22832022-10-28 20:27:00 -0400127 select SYS_L2_SIZE_256KB
Simon Glassa1dc9802017-05-17 03:25:10 -0600128 imply CMD_EEPROM
Simon Glass3bf926c2017-06-14 21:28:24 -0600129 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900130 imply PANIC_HANG
Masahiro Yamadadd840582014-07-30 14:08:14 +0900131
York Sunaa146202016-11-17 13:52:44 -0800132config TARGET_P1020RDB_PC
133 bool "Support P1020RDB-PC"
134 select SUPPORT_SPL
135 select SUPPORT_TPL
York Sun484fff62016-11-18 10:02:14 -0800136 select ARCH_P1020
Tom Rini22a22832022-10-28 20:27:00 -0400137 select SYS_L2_SIZE_256KB
Simon Glassa1dc9802017-05-17 03:25:10 -0600138 imply CMD_EEPROM
Simon Glass3bf926c2017-06-14 21:28:24 -0600139 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900140 imply PANIC_HANG
York Sunaa146202016-11-17 13:52:44 -0800141
York Sunf404b662016-11-17 13:53:33 -0800142config TARGET_P1020RDB_PD
143 bool "Support P1020RDB-PD"
144 select SUPPORT_SPL
145 select SUPPORT_TPL
York Sun484fff62016-11-18 10:02:14 -0800146 select ARCH_P1020
Tom Rini22a22832022-10-28 20:27:00 -0400147 select SYS_L2_SIZE_256KB
Simon Glassa1dc9802017-05-17 03:25:10 -0600148 imply CMD_EEPROM
Simon Glass3bf926c2017-06-14 21:28:24 -0600149 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900150 imply PANIC_HANG
York Sunf404b662016-11-17 13:53:33 -0800151
York Sun8435aa72016-11-17 14:19:18 -0800152config TARGET_P2020RDB
153 bool "Support P2020RDB-PC"
154 select SUPPORT_SPL
155 select SUPPORT_TPL
York Sun45936372016-11-18 11:08:43 -0800156 select ARCH_P2020
Tom Rini22a22832022-10-28 20:27:00 -0400157 select SYS_L2_SIZE_512KB
Simon Glassa1dc9802017-05-17 03:25:10 -0600158 imply CMD_EEPROM
Simon Glass3bf926c2017-06-14 21:28:24 -0600159 imply CMD_SATA
Tuomas Tynkkynenc88ecf42017-12-08 15:36:14 +0200160 imply SATA_SIL
York Sun8435aa72016-11-17 14:19:18 -0800161
Masahiro Yamadadd840582014-07-30 14:08:14 +0900162config TARGET_P2041RDB
163 bool "Support P2041RDB"
York Sunce040c82016-11-18 11:15:21 -0800164 select ARCH_P2041
Tom Rinie5ec4812017-01-22 19:43:11 -0500165 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Tom Rini6f6b9702022-07-23 13:05:08 -0400166 select FSL_CORENET
Masahiro Yamadabb6b1422016-07-25 19:56:03 +0900167 select PHYS_64BIT
Tom Rinib85d7592022-10-28 20:27:01 -0400168 select SYS_L3_SIZE_1024KB
Simon Glass3bf926c2017-06-14 21:28:24 -0600169 imply CMD_SATA
Tuomas Tynkkynen9920d152017-12-08 15:36:17 +0200170 imply FSL_SATA
Masahiro Yamadadd840582014-07-30 14:08:14 +0900171
172config TARGET_QEMU_PPCE500
173 bool "Support qemu-ppce500"
York Sun10343402016-11-18 12:29:51 -0800174 select ARCH_QEMU_E500
Masahiro Yamadabb6b1422016-07-25 19:56:03 +0900175 select PHYS_64BIT
Tom Rini5a446182022-06-25 11:02:44 -0400176 select SYS_RAMBOOT
Simon Glass239d22c2021-12-16 20:59:36 -0700177 imply OF_HAS_PRIOR_STAGE
Masahiro Yamadadd840582014-07-30 14:08:14 +0900178
York Sun08c75292016-11-18 12:45:44 -0800179config TARGET_T1024RDB
180 bool "Support T1024RDB"
York Sune5d5f5a2016-11-18 13:01:34 -0800181 select ARCH_T1024
Tom Rinie5ec4812017-01-22 19:43:11 -0500182 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800183 select SUPPORT_SPL
Masahiro Yamadabb6b1422016-07-25 19:56:03 +0900184 select PHYS_64BIT
Rajesh Bhagat32413122019-02-01 05:22:01 +0000185 select FSL_DDR_INTERACTIVE
Tom Rinib85d7592022-10-28 20:27:01 -0400186 select SYS_L3_SIZE_256KB
Simon Glassa1dc9802017-05-17 03:25:10 -0600187 imply CMD_EEPROM
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900188 imply PANIC_HANG
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800189
York Sun95a809b2016-11-18 13:19:39 -0800190config TARGET_T1042RDB
191 bool "Support T1042RDB"
York Sun5449c982016-11-18 13:36:39 -0800192 select ARCH_T1042
Tom Rinie5ec4812017-01-22 19:43:11 -0500193 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Masahiro Yamada02627352014-10-20 17:45:56 +0900194 select SUPPORT_SPL
Masahiro Yamadabb6b1422016-07-25 19:56:03 +0900195 select PHYS_64BIT
Tom Rinib85d7592022-10-28 20:27:01 -0400196 select SYS_L3_SIZE_256KB
Masahiro Yamadadd840582014-07-30 14:08:14 +0900197
York Sun319ed242016-11-21 11:04:34 -0800198config TARGET_T1042D4RDB
199 bool "Support T1042D4RDB"
200 select ARCH_T1042
Tom Rinie5ec4812017-01-22 19:43:11 -0500201 select BOARD_LATE_INIT if CHAIN_OF_TRUST
York Sun319ed242016-11-21 11:04:34 -0800202 select SUPPORT_SPL
203 select PHYS_64BIT
Tom Rinib85d7592022-10-28 20:27:01 -0400204 select SYS_L3_SIZE_256KB
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900205 imply PANIC_HANG
York Sun319ed242016-11-21 11:04:34 -0800206
York Sun55ed8ae2016-11-18 13:44:00 -0800207config TARGET_T1042RDB_PI
208 bool "Support T1042RDB_PI"
209 select ARCH_T1042
Tom Rinie5ec4812017-01-22 19:43:11 -0500210 select BOARD_LATE_INIT if CHAIN_OF_TRUST
York Sun55ed8ae2016-11-18 13:44:00 -0800211 select SUPPORT_SPL
212 select PHYS_64BIT
Tom Rinib85d7592022-10-28 20:27:01 -0400213 select SYS_L3_SIZE_256KB
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900214 imply PANIC_HANG
York Sun55ed8ae2016-11-18 13:44:00 -0800215
York Sun638d5be2016-11-21 12:46:58 -0800216config TARGET_T2080QDS
217 bool "Support T2080QDS"
York Sun0f3d80e2016-11-21 12:54:19 -0800218 select ARCH_T2080
Tom Rinie5ec4812017-01-22 19:43:11 -0500219 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Masahiro Yamada02627352014-10-20 17:45:56 +0900220 select SUPPORT_SPL
Masahiro Yamadabb6b1422016-07-25 19:56:03 +0900221 select PHYS_64BIT
Rajesh Bhagat32413122019-02-01 05:22:01 +0000222 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
223 select FSL_DDR_INTERACTIVE
Tom Rinib85d7592022-10-28 20:27:01 -0400224 select SYS_L3_SIZE_512KB
Peng Maa2d4cb22019-12-23 09:28:12 +0000225 imply CMD_SATA
Masahiro Yamadadd840582014-07-30 14:08:14 +0900226
York Sun01671e62016-11-21 12:57:22 -0800227config TARGET_T2080RDB
228 bool "Support T2080RDB"
York Sun0f3d80e2016-11-21 12:54:19 -0800229 select ARCH_T2080
Tom Rinie5ec4812017-01-22 19:43:11 -0500230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
Masahiro Yamada02627352014-10-20 17:45:56 +0900231 select SUPPORT_SPL
Masahiro Yamadabb6b1422016-07-25 19:56:03 +0900232 select PHYS_64BIT
Tom Rinib85d7592022-10-28 20:27:01 -0400233 select SYS_L3_SIZE_512KB
Simon Glass3bf926c2017-06-14 21:28:24 -0600234 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900235 imply PANIC_HANG
Masahiro Yamadadd840582014-07-30 14:08:14 +0900236
Masahiro Yamadadd840582014-07-30 14:08:14 +0900237config TARGET_T4240RDB
238 bool "Support T4240RDB"
York Sun26bc57d2016-11-21 13:35:41 -0800239 select ARCH_T4240
Chunhe Lan373762c2015-03-20 17:08:54 +0800240 select SUPPORT_SPL
Masahiro Yamadabb6b1422016-07-25 19:56:03 +0900241 select PHYS_64BIT
Rajesh Bhagat32413122019-02-01 05:22:01 +0000242 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
Tom Rinib85d7592022-10-28 20:27:01 -0400243 select SYS_L3_SIZE_512KB
Simon Glass3bf926c2017-06-14 21:28:24 -0600244 imply CMD_SATA
Masahiro Yamada7e3caa82017-12-04 12:37:00 +0900245 imply PANIC_HANG
Masahiro Yamadadd840582014-07-30 14:08:14 +0900246
Masahiro Yamadadd840582014-07-30 14:08:14 +0900247config TARGET_KMP204X
248 bool "Support kmp204x"
Pascal Linderc0fed3a2019-06-18 13:27:47 +0200249 select VENDOR_KM
Masahiro Yamadadd840582014-07-30 14:08:14 +0900250
Niel Fourie37bfd9c2021-01-21 13:19:20 +0100251config TARGET_KMCENT2
252 bool "Support kmcent2"
253 select VENDOR_KM
Tom Rini6f6b9702022-07-23 13:05:08 -0400254 select FSL_CORENET
Tom Rini2db82bf2022-11-16 13:10:34 -0500255 select SYS_DPAA_FMAN
256 select SYS_DPAA_PME
Tom Rinib85d7592022-10-28 20:27:01 -0400257 select SYS_L3_SIZE_256KB
Niel Fourie37bfd9c2021-01-21 13:19:20 +0100258
Masahiro Yamadadd840582014-07-30 14:08:14 +0900259endchoice
260
York Sunb41f1922016-11-18 11:56:57 -0800261config ARCH_B4420
262 bool
York Sunf8dee362016-12-28 08:43:27 -0800263 select E500MC
York Sun9ec10102016-12-28 08:43:48 -0800264 select E6500
Tom Rini6f6b9702022-07-23 13:05:08 -0400265 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800266 select FSL_LAW
Tom Rini1e7750f2022-06-16 14:04:34 -0400267 select HETROGENOUS_CLUSTERS
York Sun22120f12016-12-28 08:43:46 -0800268 select SYS_FSL_DDR_VER_47
York Sun63659ff2016-12-28 08:43:43 -0800269 select SYS_FSL_ERRATUM_A004477
270 select SYS_FSL_ERRATUM_A005871
271 select SYS_FSL_ERRATUM_A006379
272 select SYS_FSL_ERRATUM_A006384
273 select SYS_FSL_ERRATUM_A006475
274 select SYS_FSL_ERRATUM_A006593
275 select SYS_FSL_ERRATUM_A007075
Tom Rini601483f2022-06-16 14:04:40 -0400276 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
York Sun63659ff2016-12-28 08:43:43 -0800277 select SYS_FSL_ERRATUM_A007212
278 select SYS_FSL_ERRATUM_A009942
York Sund26e34c2016-12-28 08:43:40 -0800279 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800280 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800281 select SYS_FSL_QORIQ_CHASSIS2
Tom Rini4143a232022-07-31 21:08:28 -0400282 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
York Sun90b80382016-12-28 08:43:31 -0800283 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800284 select SYS_FSL_SEC_COMPAT_4
Tom Riniff4e87c2022-07-31 21:08:29 -0400285 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
286 select SYS_FSL_USB1_PHY_ENABLE
York Sun48512782016-12-28 08:43:50 -0800287 select SYS_PPC64
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530288 select FSL_IFC
Simon Glassa1dc9802017-05-17 03:25:10 -0600289 imply CMD_EEPROM
Tom Rini8f1a80e2017-07-28 21:31:42 -0400290 imply CMD_NAND
Christophe Leroyfa379222017-08-04 16:34:40 -0600291 imply CMD_REGINFO
York Sunb41f1922016-11-18 11:56:57 -0800292
York Sun3006ebc2016-11-18 11:44:43 -0800293config ARCH_B4860
294 bool
York Sunf8dee362016-12-28 08:43:27 -0800295 select E500MC
York Sun9ec10102016-12-28 08:43:48 -0800296 select E6500
Tom Rini6f6b9702022-07-23 13:05:08 -0400297 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800298 select FSL_LAW
Tom Rini1e7750f2022-06-16 14:04:34 -0400299 select HETROGENOUS_CLUSTERS
York Sun22120f12016-12-28 08:43:46 -0800300 select SYS_FSL_DDR_VER_47
York Sun63659ff2016-12-28 08:43:43 -0800301 select SYS_FSL_ERRATUM_A004477
302 select SYS_FSL_ERRATUM_A005871
303 select SYS_FSL_ERRATUM_A006379
304 select SYS_FSL_ERRATUM_A006384
305 select SYS_FSL_ERRATUM_A006475
306 select SYS_FSL_ERRATUM_A006593
307 select SYS_FSL_ERRATUM_A007075
Tom Rini601483f2022-06-16 14:04:40 -0400308 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
York Sun63659ff2016-12-28 08:43:43 -0800309 select SYS_FSL_ERRATUM_A007212
Darwin Dingel06ad9702016-10-25 09:48:01 +1300310 select SYS_FSL_ERRATUM_A007907
York Sun63659ff2016-12-28 08:43:43 -0800311 select SYS_FSL_ERRATUM_A009942
York Sund26e34c2016-12-28 08:43:40 -0800312 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800313 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800314 select SYS_FSL_QORIQ_CHASSIS2
Tom Rini4143a232022-07-31 21:08:28 -0400315 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
York Sun90b80382016-12-28 08:43:31 -0800316 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800317 select SYS_FSL_SEC_COMPAT_4
Tom Riniff4e87c2022-07-31 21:08:29 -0400318 select SYS_FSL_SRIO_LIODN
319 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
320 select SYS_FSL_USB1_PHY_ENABLE
York Sun48512782016-12-28 08:43:50 -0800321 select SYS_PPC64
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530322 select FSL_IFC
Simon Glassa1dc9802017-05-17 03:25:10 -0600323 imply CMD_EEPROM
Tom Rini8f1a80e2017-07-28 21:31:42 -0400324 imply CMD_NAND
Christophe Leroyfa379222017-08-04 16:34:40 -0600325 imply CMD_REGINFO
York Sun3006ebc2016-11-18 11:44:43 -0800326
York Sun115d60c2016-11-15 14:09:50 -0800327config ARCH_BSC9131
328 bool
York Sun05cb79a2016-12-02 10:44:34 -0800329 select FSL_LAW
York Sun22120f12016-12-28 08:43:46 -0800330 select SYS_FSL_DDR_VER_44
York Sun63659ff2016-12-28 08:43:43 -0800331 select SYS_FSL_ERRATUM_A004477
332 select SYS_FSL_ERRATUM_A005125
York Sunc01e4a12016-12-28 08:43:42 -0800333 select SYS_FSL_ERRATUM_ESDHC111
York Sund26e34c2016-12-28 08:43:40 -0800334 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800335 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800336 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800337 select SYS_FSL_SEC_COMPAT_4
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530338 select FSL_IFC
Simon Glassa1dc9802017-05-17 03:25:10 -0600339 imply CMD_EEPROM
Tom Rini8f1a80e2017-07-28 21:31:42 -0400340 imply CMD_NAND
Christophe Leroyfa379222017-08-04 16:34:40 -0600341 imply CMD_REGINFO
York Sun115d60c2016-11-15 14:09:50 -0800342
343config ARCH_BSC9132
344 bool
York Sun05cb79a2016-12-02 10:44:34 -0800345 select FSL_LAW
York Sun22120f12016-12-28 08:43:46 -0800346 select SYS_FSL_DDR_VER_46
York Sun63659ff2016-12-28 08:43:43 -0800347 select SYS_FSL_ERRATUM_A004477
348 select SYS_FSL_ERRATUM_A005125
349 select SYS_FSL_ERRATUM_A005434
York Sunc01e4a12016-12-28 08:43:42 -0800350 select SYS_FSL_ERRATUM_ESDHC111
York Sun63659ff2016-12-28 08:43:43 -0800351 select SYS_FSL_ERRATUM_I2C_A004447
352 select SYS_FSL_ERRATUM_IFC_A002769
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800353 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800354 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800355 select SYS_FSL_HAS_SEC
Tom Rini4143a232022-07-31 21:08:28 -0400356 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
York Sun90b80382016-12-28 08:43:31 -0800357 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800358 select SYS_FSL_SEC_COMPAT_4
York Sun53c95382016-12-28 08:43:29 -0800359 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530360 select FSL_IFC
Simon Glassa1dc9802017-05-17 03:25:10 -0600361 imply CMD_EEPROM
Tom Rinid56b4b12017-07-22 18:36:16 -0400362 imply CMD_MTDPARTS
Tom Rini8f1a80e2017-07-28 21:31:42 -0400363 imply CMD_NAND
Simon Glass6500ec72017-08-04 16:34:34 -0600364 imply CMD_PCI
Christophe Leroyfa379222017-08-04 16:34:40 -0600365 imply CMD_REGINFO
York Sun115d60c2016-11-15 14:09:50 -0800366
York Sun4fd64742016-11-15 18:44:22 -0800367config ARCH_C29X
368 bool
York Sun05cb79a2016-12-02 10:44:34 -0800369 select FSL_LAW
York Sun22120f12016-12-28 08:43:46 -0800370 select SYS_FSL_DDR_VER_46
York Sun63659ff2016-12-28 08:43:43 -0800371 select SYS_FSL_ERRATUM_A005125
York Sunc01e4a12016-12-28 08:43:42 -0800372 select SYS_FSL_ERRATUM_ESDHC111
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800373 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800374 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800375 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800376 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800377 select SYS_FSL_SEC_COMPAT_6
York Sun53c95382016-12-28 08:43:29 -0800378 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530379 select FSL_IFC
Tom Rini8f1a80e2017-07-28 21:31:42 -0400380 imply CMD_NAND
Simon Glass6500ec72017-08-04 16:34:34 -0600381 imply CMD_PCI
Christophe Leroyfa379222017-08-04 16:34:40 -0600382 imply CMD_REGINFO
York Sun4fd64742016-11-15 18:44:22 -0800383
York Sun24ad75a2016-11-16 11:06:47 -0800384config ARCH_MPC8536
385 bool
York Sun05cb79a2016-12-02 10:44:34 -0800386 select FSL_LAW
York Sun63659ff2016-12-28 08:43:43 -0800387 select SYS_FSL_ERRATUM_A004508
388 select SYS_FSL_ERRATUM_A005125
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800389 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800390 select SYS_FSL_HAS_DDR2
391 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800392 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800393 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800394 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800395 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530396 select FSL_ELBC
Tom Rini8f1a80e2017-07-28 21:31:42 -0400397 imply CMD_NAND
Simon Glass3bf926c2017-06-14 21:28:24 -0600398 imply CMD_SATA
Christophe Leroyfa379222017-08-04 16:34:40 -0600399 imply CMD_REGINFO
York Sun24ad75a2016-11-16 11:06:47 -0800400
York Sun7f825212016-11-16 11:13:06 -0800401config ARCH_MPC8540
402 bool
York Sun05cb79a2016-12-02 10:44:34 -0800403 select FSL_LAW
York Sund26e34c2016-12-28 08:43:40 -0800404 select SYS_FSL_HAS_DDR1
York Sun7f825212016-11-16 11:13:06 -0800405
York Sun25cb74b2016-11-15 13:57:15 -0800406config ARCH_MPC8544
407 bool
Tom Rinia3041d92022-02-23 12:28:15 -0500408 select BTB
York Sun05cb79a2016-12-02 10:44:34 -0800409 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400410 select SYS_CACHE_SHIFT_5
York Sun63659ff2016-12-28 08:43:43 -0800411 select SYS_FSL_ERRATUM_A005125
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800412 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800413 select SYS_FSL_HAS_DDR2
York Sun2c2e2c92016-12-28 08:43:30 -0800414 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800415 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800416 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800417 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530418 select FSL_ELBC
York Sun25cb74b2016-11-15 13:57:15 -0800419
York Sun281ed4c2016-11-15 13:52:34 -0800420config ARCH_MPC8548
421 bool
Tom Rinia3041d92022-02-23 12:28:15 -0500422 select BTB
York Sun05cb79a2016-12-02 10:44:34 -0800423 select FSL_LAW
York Sun63659ff2016-12-28 08:43:43 -0800424 select SYS_FSL_ERRATUM_A005125
425 select SYS_FSL_ERRATUM_NMG_DDR120
426 select SYS_FSL_ERRATUM_NMG_LBC103
427 select SYS_FSL_ERRATUM_NMG_ETSEC129
428 select SYS_FSL_ERRATUM_I2C_A004447
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800429 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800430 select SYS_FSL_HAS_DDR2
431 select SYS_FSL_HAS_DDR1
York Sun2c2e2c92016-12-28 08:43:30 -0800432 select SYS_FSL_HAS_SEC
Tom Riniff4e87c2022-07-31 21:08:29 -0400433 select SYS_FSL_RMU
York Sun90b80382016-12-28 08:43:31 -0800434 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800435 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800436 select SYS_PPC_E500_USE_DEBUG_TLB
Christophe Leroyfa379222017-08-04 16:34:40 -0600437 imply CMD_REGINFO
York Sun281ed4c2016-11-15 13:52:34 -0800438
York Sun99d0a312016-11-16 11:26:45 -0800439config ARCH_MPC8560
440 bool
York Sun05cb79a2016-12-02 10:44:34 -0800441 select FSL_LAW
York Sund26e34c2016-12-28 08:43:40 -0800442 select SYS_FSL_HAS_DDR1
York Sun99d0a312016-11-16 11:26:45 -0800443
York Sun7d5f9f82016-11-16 13:08:52 -0800444config ARCH_P1010
445 bool
Tom Rinifdd0da42022-03-11 09:11:59 -0500446 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
Tom Rinia3041d92022-02-23 12:28:15 -0500447 select BTB
York Sun05cb79a2016-12-02 10:44:34 -0800448 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400449 select SYS_CACHE_SHIFT_5
Tom Rinif76750d2021-12-11 14:55:51 -0500450 select SYS_HAS_SERDES
York Sun63659ff2016-12-28 08:43:43 -0800451 select SYS_FSL_ERRATUM_A004477
452 select SYS_FSL_ERRATUM_A004508
453 select SYS_FSL_ERRATUM_A005125
Chris Packham4eaf7f52018-10-04 20:03:53 +1300454 select SYS_FSL_ERRATUM_A005275
York Sun63659ff2016-12-28 08:43:43 -0800455 select SYS_FSL_ERRATUM_A006261
456 select SYS_FSL_ERRATUM_A007075
York Sunc01e4a12016-12-28 08:43:42 -0800457 select SYS_FSL_ERRATUM_ESDHC111
York Sun63659ff2016-12-28 08:43:43 -0800458 select SYS_FSL_ERRATUM_I2C_A004447
459 select SYS_FSL_ERRATUM_IFC_A002769
460 select SYS_FSL_ERRATUM_P1010_A003549
461 select SYS_FSL_ERRATUM_SEC_A003571
462 select SYS_FSL_ERRATUM_IFC_A003399
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800463 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800464 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800465 select SYS_FSL_HAS_SEC
Tom Rini4143a232022-07-31 21:08:28 -0400466 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
York Sun90b80382016-12-28 08:43:31 -0800467 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800468 select SYS_FSL_SEC_COMPAT_4
Tom Riniff4e87c2022-07-31 21:08:29 -0400469 select SYS_FSL_USB1_PHY_ENABLE
York Sun53c95382016-12-28 08:43:29 -0800470 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530471 select FSL_IFC
Simon Glassa1dc9802017-05-17 03:25:10 -0600472 imply CMD_EEPROM
Tom Rinid56b4b12017-07-22 18:36:16 -0400473 imply CMD_MTDPARTS
Tom Rini8f1a80e2017-07-28 21:31:42 -0400474 imply CMD_NAND
Simon Glass3bf926c2017-06-14 21:28:24 -0600475 imply CMD_SATA
Simon Glass6500ec72017-08-04 16:34:34 -0600476 imply CMD_PCI
Christophe Leroyfa379222017-08-04 16:34:40 -0600477 imply CMD_REGINFO
Tuomas Tynkkynen9920d152017-12-08 15:36:17 +0200478 imply FSL_SATA
Simon Glassd6b318d2021-12-18 11:27:50 -0700479 imply TIMESTAMP
York Sun7d5f9f82016-11-16 13:08:52 -0800480
York Sun1cdd96f2016-11-16 15:54:15 -0800481config ARCH_P1011
482 bool
York Sun05cb79a2016-12-02 10:44:34 -0800483 select FSL_LAW
York Sun63659ff2016-12-28 08:43:43 -0800484 select SYS_FSL_ERRATUM_A004508
485 select SYS_FSL_ERRATUM_A005125
486 select SYS_FSL_ERRATUM_ELBC_A001
York Sunc01e4a12016-12-28 08:43:42 -0800487 select SYS_FSL_ERRATUM_ESDHC111
Hou Zhiqiangc16dfd02019-05-22 22:46:03 +0800488 select FSL_PCIE_DISABLE_ASPM
York Sund26e34c2016-12-28 08:43:40 -0800489 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800490 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800491 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800492 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800493 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530494 select FSL_ELBC
York Sun1cdd96f2016-11-16 15:54:15 -0800495
York Sun484fff62016-11-18 10:02:14 -0800496config ARCH_P1020
497 bool
Tom Rinia3041d92022-02-23 12:28:15 -0500498 select BTB
York Sun05cb79a2016-12-02 10:44:34 -0800499 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400500 select SYS_CACHE_SHIFT_5
York Sun63659ff2016-12-28 08:43:43 -0800501 select SYS_FSL_ERRATUM_A004508
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_ELBC_A001
York Sunc01e4a12016-12-28 08:43:42 -0800504 select SYS_FSL_ERRATUM_ESDHC111
Hou Zhiqiangc16dfd02019-05-22 22:46:03 +0800505 select FSL_PCIE_DISABLE_ASPM
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800506 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800507 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800508 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800509 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800510 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800511 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530512 select FSL_ELBC
Tom Rini8f1a80e2017-07-28 21:31:42 -0400513 imply CMD_NAND
Simon Glass3bf926c2017-06-14 21:28:24 -0600514 imply CMD_SATA
Simon Glass6500ec72017-08-04 16:34:34 -0600515 imply CMD_PCI
Christophe Leroyfa379222017-08-04 16:34:40 -0600516 imply CMD_REGINFO
Tuomas Tynkkynenc88ecf42017-12-08 15:36:14 +0200517 imply SATA_SIL
York Sun484fff62016-11-18 10:02:14 -0800518
York Suna9907992016-11-18 10:59:02 -0800519config ARCH_P1021
520 bool
York Sun05cb79a2016-12-02 10:44:34 -0800521 select FSL_LAW
York Sun63659ff2016-12-28 08:43:43 -0800522 select SYS_FSL_ERRATUM_A004508
523 select SYS_FSL_ERRATUM_A005125
524 select SYS_FSL_ERRATUM_ELBC_A001
York Sunc01e4a12016-12-28 08:43:42 -0800525 select SYS_FSL_ERRATUM_ESDHC111
Hou Zhiqiangc16dfd02019-05-22 22:46:03 +0800526 select FSL_PCIE_DISABLE_ASPM
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800527 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800528 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800529 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800530 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800531 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800532 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530533 select FSL_ELBC
Christophe Leroyfa379222017-08-04 16:34:40 -0600534 imply CMD_REGINFO
Tom Rini8f1a80e2017-07-28 21:31:42 -0400535 imply CMD_NAND
Simon Glass3bf926c2017-06-14 21:28:24 -0600536 imply CMD_SATA
Christophe Leroyfa379222017-08-04 16:34:40 -0600537 imply CMD_REGINFO
Tuomas Tynkkynenc88ecf42017-12-08 15:36:14 +0200538 imply SATA_SIL
York Suna9907992016-11-18 10:59:02 -0800539
York Sun9bb1d6b2016-11-16 15:45:31 -0800540config ARCH_P1023
541 bool
York Sun05cb79a2016-12-02 10:44:34 -0800542 select FSL_LAW
York Sun63659ff2016-12-28 08:43:43 -0800543 select SYS_FSL_ERRATUM_A004508
544 select SYS_FSL_ERRATUM_A005125
545 select SYS_FSL_ERRATUM_I2C_A004447
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800546 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800547 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800548 select SYS_FSL_HAS_SEC
Tom Rini4143a232022-07-31 21:08:28 -0400549 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
York Sun90b80382016-12-28 08:43:31 -0800550 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800551 select SYS_FSL_SEC_COMPAT_4
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530552 select FSL_ELBC
York Sun9bb1d6b2016-11-16 15:45:31 -0800553
York Sun52b6f132016-11-18 11:00:57 -0800554config ARCH_P1024
555 bool
York Sun05cb79a2016-12-02 10:44:34 -0800556 select FSL_LAW
York Sun63659ff2016-12-28 08:43:43 -0800557 select SYS_FSL_ERRATUM_A004508
558 select SYS_FSL_ERRATUM_A005125
559 select SYS_FSL_ERRATUM_ELBC_A001
York Sunc01e4a12016-12-28 08:43:42 -0800560 select SYS_FSL_ERRATUM_ESDHC111
Hou Zhiqiangc16dfd02019-05-22 22:46:03 +0800561 select FSL_PCIE_DISABLE_ASPM
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800562 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800563 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800564 select SYS_FSL_HAS_SEC
Tom Riniff4e87c2022-07-31 21:08:29 -0400565 select SYS_FSL_RMU
York Sun90b80382016-12-28 08:43:31 -0800566 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800567 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800568 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530569 select FSL_ELBC
Simon Glassa1dc9802017-05-17 03:25:10 -0600570 imply CMD_EEPROM
Tom Rini8f1a80e2017-07-28 21:31:42 -0400571 imply CMD_NAND
Simon Glass3bf926c2017-06-14 21:28:24 -0600572 imply CMD_SATA
Simon Glass6500ec72017-08-04 16:34:34 -0600573 imply CMD_PCI
Christophe Leroyfa379222017-08-04 16:34:40 -0600574 imply CMD_REGINFO
Tuomas Tynkkynenc88ecf42017-12-08 15:36:14 +0200575 imply SATA_SIL
York Sun52b6f132016-11-18 11:00:57 -0800576
York Sun4167a672016-11-18 11:05:38 -0800577config ARCH_P1025
578 bool
York Sun05cb79a2016-12-02 10:44:34 -0800579 select FSL_LAW
York Sun63659ff2016-12-28 08:43:43 -0800580 select SYS_FSL_ERRATUM_A004508
581 select SYS_FSL_ERRATUM_A005125
582 select SYS_FSL_ERRATUM_ELBC_A001
York Sunc01e4a12016-12-28 08:43:42 -0800583 select SYS_FSL_ERRATUM_ESDHC111
Hou Zhiqiangc16dfd02019-05-22 22:46:03 +0800584 select FSL_PCIE_DISABLE_ASPM
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800585 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800586 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800587 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800588 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800589 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800590 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530591 select FSL_ELBC
Simon Glass3bf926c2017-06-14 21:28:24 -0600592 imply CMD_SATA
Christophe Leroyfa379222017-08-04 16:34:40 -0600593 imply CMD_REGINFO
York Sun4167a672016-11-18 11:05:38 -0800594
York Sun45936372016-11-18 11:08:43 -0800595config ARCH_P2020
596 bool
Tom Rinia3041d92022-02-23 12:28:15 -0500597 select BTB
York Sun05cb79a2016-12-02 10:44:34 -0800598 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400599 select SYS_CACHE_SHIFT_5
York Sun63659ff2016-12-28 08:43:43 -0800600 select SYS_FSL_ERRATUM_A004477
601 select SYS_FSL_ERRATUM_A004508
602 select SYS_FSL_ERRATUM_A005125
York Sunc01e4a12016-12-28 08:43:42 -0800603 select SYS_FSL_ERRATUM_ESDHC111
604 select SYS_FSL_ERRATUM_ESDHC_A001
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800605 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800606 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800607 select SYS_FSL_HAS_SEC
York Sun90b80382016-12-28 08:43:31 -0800608 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800609 select SYS_FSL_SEC_COMPAT_2
York Sun53c95382016-12-28 08:43:29 -0800610 select SYS_PPC_E500_USE_DEBUG_TLB
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530611 select FSL_ELBC
Simon Glassa1dc9802017-05-17 03:25:10 -0600612 imply CMD_EEPROM
Tom Rini8f1a80e2017-07-28 21:31:42 -0400613 imply CMD_NAND
Christophe Leroyfa379222017-08-04 16:34:40 -0600614 imply CMD_REGINFO
Simon Glassd6b318d2021-12-18 11:27:50 -0700615 imply TIMESTAMP
York Sun45936372016-11-18 11:08:43 -0800616
York Sunce040c82016-11-18 11:15:21 -0800617config ARCH_P2041
618 bool
Tom Rinib40d2b22022-03-18 08:38:32 -0400619 select BACKSIDE_L2_CACHE
York Sunf8dee362016-12-28 08:43:27 -0800620 select E500MC
York Sun05cb79a2016-12-02 10:44:34 -0800621 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400622 select SYS_CACHE_SHIFT_6
Tom Rini2db82bf2022-11-16 13:10:34 -0500623 select SYS_DPAA_FMAN
624 select SYS_DPAA_PME
625 select SYS_DPAA_RMAN
York Sun63659ff2016-12-28 08:43:43 -0800626 select SYS_FSL_ERRATUM_A004510
627 select SYS_FSL_ERRATUM_A004849
Chris Packham4eaf7f52018-10-04 20:03:53 +1300628 select SYS_FSL_ERRATUM_A005275
York Sun63659ff2016-12-28 08:43:43 -0800629 select SYS_FSL_ERRATUM_A006261
630 select SYS_FSL_ERRATUM_CPU_A003999
631 select SYS_FSL_ERRATUM_DDR_A003
632 select SYS_FSL_ERRATUM_DDR_A003474
York Sunc01e4a12016-12-28 08:43:42 -0800633 select SYS_FSL_ERRATUM_ESDHC111
York Sun63659ff2016-12-28 08:43:43 -0800634 select SYS_FSL_ERRATUM_I2C_A004447
635 select SYS_FSL_ERRATUM_NMG_CPU_A011
636 select SYS_FSL_ERRATUM_SRIO_A004034
637 select SYS_FSL_ERRATUM_USB14
York Sund26e34c2016-12-28 08:43:40 -0800638 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800639 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800640 select SYS_FSL_QORIQ_CHASSIS1
Tom Rini4143a232022-07-31 21:08:28 -0400641 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
York Sun90b80382016-12-28 08:43:31 -0800642 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800643 select SYS_FSL_SEC_COMPAT_4
Tom Riniff4e87c2022-07-31 21:08:29 -0400644 select SYS_FSL_USB1_PHY_ENABLE
645 select SYS_FSL_USB2_PHY_ENABLE
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530646 select FSL_ELBC
Tom Rini8f1a80e2017-07-28 21:31:42 -0400647 imply CMD_NAND
York Sunce040c82016-11-18 11:15:21 -0800648
York Sun5e5fdd22016-11-18 11:20:40 -0800649config ARCH_P3041
650 bool
Tom Rinib40d2b22022-03-18 08:38:32 -0400651 select BACKSIDE_L2_CACHE
York Sunf8dee362016-12-28 08:43:27 -0800652 select E500MC
Tom Rini6f6b9702022-07-23 13:05:08 -0400653 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800654 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400655 select SYS_CACHE_SHIFT_6
York Sun22120f12016-12-28 08:43:46 -0800656 select SYS_FSL_DDR_VER_44
York Sun63659ff2016-12-28 08:43:43 -0800657 select SYS_FSL_ERRATUM_A004510
658 select SYS_FSL_ERRATUM_A004849
Chris Packham4eaf7f52018-10-04 20:03:53 +1300659 select SYS_FSL_ERRATUM_A005275
York Sun63659ff2016-12-28 08:43:43 -0800660 select SYS_FSL_ERRATUM_A005812
661 select SYS_FSL_ERRATUM_A006261
662 select SYS_FSL_ERRATUM_CPU_A003999
663 select SYS_FSL_ERRATUM_DDR_A003
664 select SYS_FSL_ERRATUM_DDR_A003474
York Sunc01e4a12016-12-28 08:43:42 -0800665 select SYS_FSL_ERRATUM_ESDHC111
York Sun63659ff2016-12-28 08:43:43 -0800666 select SYS_FSL_ERRATUM_I2C_A004447
667 select SYS_FSL_ERRATUM_NMG_CPU_A011
668 select SYS_FSL_ERRATUM_SRIO_A004034
669 select SYS_FSL_ERRATUM_USB14
York Sund26e34c2016-12-28 08:43:40 -0800670 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800671 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800672 select SYS_FSL_QORIQ_CHASSIS1
Tom Rini4143a232022-07-31 21:08:28 -0400673 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
York Sun90b80382016-12-28 08:43:31 -0800674 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800675 select SYS_FSL_SEC_COMPAT_4
Tom Riniff4e87c2022-07-31 21:08:29 -0400676 select SYS_FSL_USB1_PHY_ENABLE
677 select SYS_FSL_USB2_PHY_ENABLE
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530678 select FSL_ELBC
Tom Rini8f1a80e2017-07-28 21:31:42 -0400679 imply CMD_NAND
Simon Glass3bf926c2017-06-14 21:28:24 -0600680 imply CMD_SATA
Christophe Leroyfa379222017-08-04 16:34:40 -0600681 imply CMD_REGINFO
Tuomas Tynkkynen9920d152017-12-08 15:36:17 +0200682 imply FSL_SATA
York Sun5e5fdd22016-11-18 11:20:40 -0800683
York Sune71372c2016-11-18 11:24:40 -0800684config ARCH_P4080
685 bool
Tom Rinib40d2b22022-03-18 08:38:32 -0400686 select BACKSIDE_L2_CACHE
York Sunf8dee362016-12-28 08:43:27 -0800687 select E500MC
Tom Rini6f6b9702022-07-23 13:05:08 -0400688 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800689 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400690 select SYS_CACHE_SHIFT_6
York Sun22120f12016-12-28 08:43:46 -0800691 select SYS_FSL_DDR_VER_44
York Sun63659ff2016-12-28 08:43:43 -0800692 select SYS_FSL_ERRATUM_A004510
693 select SYS_FSL_ERRATUM_A004580
694 select SYS_FSL_ERRATUM_A004849
695 select SYS_FSL_ERRATUM_A005812
696 select SYS_FSL_ERRATUM_A007075
697 select SYS_FSL_ERRATUM_CPC_A002
698 select SYS_FSL_ERRATUM_CPC_A003
699 select SYS_FSL_ERRATUM_CPU_A003999
700 select SYS_FSL_ERRATUM_DDR_A003
701 select SYS_FSL_ERRATUM_DDR_A003474
702 select SYS_FSL_ERRATUM_ELBC_A001
York Sunc01e4a12016-12-28 08:43:42 -0800703 select SYS_FSL_ERRATUM_ESDHC111
704 select SYS_FSL_ERRATUM_ESDHC13
705 select SYS_FSL_ERRATUM_ESDHC135
York Sun63659ff2016-12-28 08:43:43 -0800706 select SYS_FSL_ERRATUM_I2C_A004447
707 select SYS_FSL_ERRATUM_NMG_CPU_A011
708 select SYS_FSL_ERRATUM_SRIO_A004034
Tom Rini4143a232022-07-31 21:08:28 -0400709 select SYS_FSL_PCIE_COMPAT_P4080_PCIE
York Sun63659ff2016-12-28 08:43:43 -0800710 select SYS_P4080_ERRATUM_CPU22
711 select SYS_P4080_ERRATUM_PCIE_A003
712 select SYS_P4080_ERRATUM_SERDES8
713 select SYS_P4080_ERRATUM_SERDES9
714 select SYS_P4080_ERRATUM_SERDES_A001
715 select SYS_P4080_ERRATUM_SERDES_A005
York Sund26e34c2016-12-28 08:43:40 -0800716 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800717 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800718 select SYS_FSL_QORIQ_CHASSIS1
Tom Riniff4e87c2022-07-31 21:08:29 -0400719 select SYS_FSL_RMU
York Sun90b80382016-12-28 08:43:31 -0800720 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800721 select SYS_FSL_SEC_COMPAT_4
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530722 select FSL_ELBC
Simon Glass3bf926c2017-06-14 21:28:24 -0600723 imply CMD_SATA
Christophe Leroyfa379222017-08-04 16:34:40 -0600724 imply CMD_REGINFO
Tuomas Tynkkynenc88ecf42017-12-08 15:36:14 +0200725 imply SATA_SIL
York Sune71372c2016-11-18 11:24:40 -0800726
York Sun95390362016-11-18 11:39:36 -0800727config ARCH_P5040
728 bool
Tom Rinib40d2b22022-03-18 08:38:32 -0400729 select BACKSIDE_L2_CACHE
York Sunf8dee362016-12-28 08:43:27 -0800730 select E500MC
Tom Rini6f6b9702022-07-23 13:05:08 -0400731 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800732 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400733 select SYS_CACHE_SHIFT_6
York Sun22120f12016-12-28 08:43:46 -0800734 select SYS_FSL_DDR_VER_44
York Sun63659ff2016-12-28 08:43:43 -0800735 select SYS_FSL_ERRATUM_A004510
736 select SYS_FSL_ERRATUM_A004699
Chris Packham4eaf7f52018-10-04 20:03:53 +1300737 select SYS_FSL_ERRATUM_A005275
York Sun63659ff2016-12-28 08:43:43 -0800738 select SYS_FSL_ERRATUM_A005812
739 select SYS_FSL_ERRATUM_A006261
740 select SYS_FSL_ERRATUM_DDR_A003
741 select SYS_FSL_ERRATUM_DDR_A003474
York Sunc01e4a12016-12-28 08:43:42 -0800742 select SYS_FSL_ERRATUM_ESDHC111
York Sun63659ff2016-12-28 08:43:43 -0800743 select SYS_FSL_ERRATUM_USB14
York Sund26e34c2016-12-28 08:43:40 -0800744 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800745 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800746 select SYS_FSL_QORIQ_CHASSIS1
Tom Rini4143a232022-07-31 21:08:28 -0400747 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
York Sun90b80382016-12-28 08:43:31 -0800748 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800749 select SYS_FSL_SEC_COMPAT_4
Tom Riniff4e87c2022-07-31 21:08:29 -0400750 select SYS_FSL_USB1_PHY_ENABLE
751 select SYS_FSL_USB2_PHY_ENABLE
York Sun48512782016-12-28 08:43:50 -0800752 select SYS_PPC64
Prabhakar Kushwaha06878972017-02-02 15:01:48 +0530753 select FSL_ELBC
Simon Glass3bf926c2017-06-14 21:28:24 -0600754 imply CMD_SATA
Christophe Leroyfa379222017-08-04 16:34:40 -0600755 imply CMD_REGINFO
Tuomas Tynkkynen9920d152017-12-08 15:36:17 +0200756 imply FSL_SATA
York Sun95390362016-11-18 11:39:36 -0800757
York Sun10343402016-11-18 12:29:51 -0800758config ARCH_QEMU_E500
759 bool
Tom Riniab92b382021-08-26 11:47:59 -0400760 select SYS_CACHE_SHIFT_5
York Sun10343402016-11-18 12:29:51 -0800761
York Sune5d5f5a2016-11-18 13:01:34 -0800762config ARCH_T1024
763 bool
Tom Rinib40d2b22022-03-18 08:38:32 -0400764 select BACKSIDE_L2_CACHE
York Sunf8dee362016-12-28 08:43:27 -0800765 select E500MC
Tom Rinif2428ac2022-03-24 17:18:01 -0400766 select E5500
Tom Rini6f6b9702022-07-23 13:05:08 -0400767 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800768 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400769 select SYS_CACHE_SHIFT_6
Tom Rini2db82bf2022-11-16 13:10:34 -0500770 select SYS_DPAA_FMAN
York Sun22120f12016-12-28 08:43:46 -0800771 select SYS_FSL_DDR_VER_50
York Sun63659ff2016-12-28 08:43:43 -0800772 select SYS_FSL_ERRATUM_A008378
Jaiprakash Singh164a5af2020-06-02 12:44:02 +0530773 select SYS_FSL_ERRATUM_A008109
York Sun63659ff2016-12-28 08:43:43 -0800774 select SYS_FSL_ERRATUM_A009663
775 select SYS_FSL_ERRATUM_A009942
York Sunc01e4a12016-12-28 08:43:42 -0800776 select SYS_FSL_ERRATUM_ESDHC111
York Sund26e34c2016-12-28 08:43:40 -0800777 select SYS_FSL_HAS_DDR3
778 select SYS_FSL_HAS_DDR4
York Sun2c2e2c92016-12-28 08:43:30 -0800779 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800780 select SYS_FSL_QORIQ_CHASSIS2
Tom Rini4143a232022-07-31 21:08:28 -0400781 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
York Sun90b80382016-12-28 08:43:31 -0800782 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800783 select SYS_FSL_SEC_COMPAT_5
Tom Riniff4e87c2022-07-31 21:08:29 -0400784 select SYS_FSL_SINGLE_SOURCE_CLK
785 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
786 select SYS_FSL_USB_DUAL_PHY_ENABLE
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530787 select FSL_IFC
Simon Glassa1dc9802017-05-17 03:25:10 -0600788 imply CMD_EEPROM
Tom Rini8f1a80e2017-07-28 21:31:42 -0400789 imply CMD_NAND
Tom Rinid56b4b12017-07-22 18:36:16 -0400790 imply CMD_MTDPARTS
Christophe Leroyfa379222017-08-04 16:34:40 -0600791 imply CMD_REGINFO
York Sune5d5f5a2016-11-18 13:01:34 -0800792
York Sun5d737012016-11-18 13:11:12 -0800793config ARCH_T1040
794 bool
Tom Rinib40d2b22022-03-18 08:38:32 -0400795 select BACKSIDE_L2_CACHE
York Sunf8dee362016-12-28 08:43:27 -0800796 select E500MC
Tom Rinif2428ac2022-03-24 17:18:01 -0400797 select E5500
Tom Rini6f6b9702022-07-23 13:05:08 -0400798 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800799 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400800 select SYS_CACHE_SHIFT_6
Tom Rini2db82bf2022-11-16 13:10:34 -0500801 select SYS_DPAA_FMAN
802 select SYS_DPAA_PME
York Sun22120f12016-12-28 08:43:46 -0800803 select SYS_FSL_DDR_VER_50
York Sun63659ff2016-12-28 08:43:43 -0800804 select SYS_FSL_ERRATUM_A008044
805 select SYS_FSL_ERRATUM_A008378
Joakim Tjernlund73af0942019-11-20 17:07:34 +0100806 select SYS_FSL_ERRATUM_A008109
York Sun63659ff2016-12-28 08:43:43 -0800807 select SYS_FSL_ERRATUM_A009663
808 select SYS_FSL_ERRATUM_A009942
York Sunc01e4a12016-12-28 08:43:42 -0800809 select SYS_FSL_ERRATUM_ESDHC111
York Sund26e34c2016-12-28 08:43:40 -0800810 select SYS_FSL_HAS_DDR3
811 select SYS_FSL_HAS_DDR4
York Sun2c2e2c92016-12-28 08:43:30 -0800812 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800813 select SYS_FSL_QORIQ_CHASSIS2
Tom Rini4143a232022-07-31 21:08:28 -0400814 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
York Sun90b80382016-12-28 08:43:31 -0800815 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800816 select SYS_FSL_SEC_COMPAT_5
Tom Riniff4e87c2022-07-31 21:08:29 -0400817 select SYS_FSL_SINGLE_SOURCE_CLK
818 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
819 select SYS_FSL_USB_DUAL_PHY_ENABLE
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530820 select FSL_IFC
Tom Rinid56b4b12017-07-22 18:36:16 -0400821 imply CMD_MTDPARTS
Tom Rini8f1a80e2017-07-28 21:31:42 -0400822 imply CMD_NAND
Christophe Leroyfa379222017-08-04 16:34:40 -0600823 imply CMD_REGINFO
York Sun5d737012016-11-18 13:11:12 -0800824
York Sun5449c982016-11-18 13:36:39 -0800825config ARCH_T1042
826 bool
Tom Rinib40d2b22022-03-18 08:38:32 -0400827 select BACKSIDE_L2_CACHE
York Sunf8dee362016-12-28 08:43:27 -0800828 select E500MC
Tom Rinif2428ac2022-03-24 17:18:01 -0400829 select E5500
Tom Rini6f6b9702022-07-23 13:05:08 -0400830 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800831 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400832 select SYS_CACHE_SHIFT_6
Tom Rini2db82bf2022-11-16 13:10:34 -0500833 select SYS_DPAA_FMAN
834 select SYS_DPAA_PME
York Sun22120f12016-12-28 08:43:46 -0800835 select SYS_FSL_DDR_VER_50
York Sun63659ff2016-12-28 08:43:43 -0800836 select SYS_FSL_ERRATUM_A008044
837 select SYS_FSL_ERRATUM_A008378
Joakim Tjernlund73af0942019-11-20 17:07:34 +0100838 select SYS_FSL_ERRATUM_A008109
York Sun63659ff2016-12-28 08:43:43 -0800839 select SYS_FSL_ERRATUM_A009663
840 select SYS_FSL_ERRATUM_A009942
York Sunc01e4a12016-12-28 08:43:42 -0800841 select SYS_FSL_ERRATUM_ESDHC111
York Sund26e34c2016-12-28 08:43:40 -0800842 select SYS_FSL_HAS_DDR3
843 select SYS_FSL_HAS_DDR4
York Sun2c2e2c92016-12-28 08:43:30 -0800844 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800845 select SYS_FSL_QORIQ_CHASSIS2
Tom Rini4143a232022-07-31 21:08:28 -0400846 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
York Sun90b80382016-12-28 08:43:31 -0800847 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800848 select SYS_FSL_SEC_COMPAT_5
Tom Riniff4e87c2022-07-31 21:08:29 -0400849 select SYS_FSL_SINGLE_SOURCE_CLK
850 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
851 select SYS_FSL_USB_DUAL_PHY_ENABLE
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530852 select FSL_IFC
Tom Rinid56b4b12017-07-22 18:36:16 -0400853 imply CMD_MTDPARTS
Tom Rini8f1a80e2017-07-28 21:31:42 -0400854 imply CMD_NAND
Christophe Leroyfa379222017-08-04 16:34:40 -0600855 imply CMD_REGINFO
York Sun5449c982016-11-18 13:36:39 -0800856
York Sun0f3d80e2016-11-21 12:54:19 -0800857config ARCH_T2080
858 bool
York Sunf8dee362016-12-28 08:43:27 -0800859 select E500MC
York Sun9ec10102016-12-28 08:43:48 -0800860 select E6500
Tom Rini6f6b9702022-07-23 13:05:08 -0400861 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800862 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400863 select SYS_CACHE_SHIFT_6
Tom Rini2db82bf2022-11-16 13:10:34 -0500864 select SYS_DPAA_DCE if !NOBQFMAN
865 select SYS_DPAA_FMAN if !NOBQFMAN
866 select SYS_DPAA_PME if !NOBQFMAN
867 select SYS_DPAA_RMAN if !NOBQFMAN
York Sun22120f12016-12-28 08:43:46 -0800868 select SYS_FSL_DDR_VER_47
York Sun63659ff2016-12-28 08:43:43 -0800869 select SYS_FSL_ERRATUM_A006379
870 select SYS_FSL_ERRATUM_A006593
Tom Rini601483f2022-06-16 14:04:40 -0400871 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
York Sun63659ff2016-12-28 08:43:43 -0800872 select SYS_FSL_ERRATUM_A007212
Tony O'Brien09bfd962016-12-02 09:22:34 +1300873 select SYS_FSL_ERRATUM_A007815
Darwin Dingel06ad9702016-10-25 09:48:01 +1300874 select SYS_FSL_ERRATUM_A007907
Jaiprakash Singh164a5af2020-06-02 12:44:02 +0530875 select SYS_FSL_ERRATUM_A008109
York Sun63659ff2016-12-28 08:43:43 -0800876 select SYS_FSL_ERRATUM_A009942
York Sunc01e4a12016-12-28 08:43:42 -0800877 select SYS_FSL_ERRATUM_ESDHC111
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +0800878 select FSL_PCIE_RESET
York Sund26e34c2016-12-28 08:43:40 -0800879 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800880 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800881 select SYS_FSL_QORIQ_CHASSIS2
Tom Rini4143a232022-07-31 21:08:28 -0400882 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
York Sun90b80382016-12-28 08:43:31 -0800883 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800884 select SYS_FSL_SEC_COMPAT_4
Tom Riniff4e87c2022-07-31 21:08:29 -0400885 select SYS_FSL_SRIO_LIODN
886 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
887 select SYS_FSL_USB_DUAL_PHY_ENABLE
Tom Rini2db82bf2022-11-16 13:10:34 -0500888 select SYS_PMAN if !NOBQFMAN
York Sun48512782016-12-28 08:43:50 -0800889 select SYS_PPC64
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530890 select FSL_IFC
Peng Maa2d4cb22019-12-23 09:28:12 +0000891 imply CMD_SATA
Tom Rini8f1a80e2017-07-28 21:31:42 -0400892 imply CMD_NAND
Christophe Leroyfa379222017-08-04 16:34:40 -0600893 imply CMD_REGINFO
Peng Maa2d4cb22019-12-23 09:28:12 +0000894 imply FSL_SATA
Tom Rinid7d40f62021-08-17 17:59:41 -0400895 imply ID_EEPROM
York Sun0f3d80e2016-11-21 12:54:19 -0800896
York Sun26bc57d2016-11-21 13:35:41 -0800897config ARCH_T4240
898 bool
York Sunf8dee362016-12-28 08:43:27 -0800899 select E500MC
York Sun9ec10102016-12-28 08:43:48 -0800900 select E6500
Tom Rini6f6b9702022-07-23 13:05:08 -0400901 select FSL_CORENET
York Sun05cb79a2016-12-02 10:44:34 -0800902 select FSL_LAW
Tom Riniab92b382021-08-26 11:47:59 -0400903 select SYS_CACHE_SHIFT_6
Tom Rini2db82bf2022-11-16 13:10:34 -0500904 select SYS_DPAA_DCE if !NOBQFMAN
905 select SYS_DPAA_FMAN if !NOBQFMAN
906 select SYS_DPAA_PME if !NOBQFMAN
907 select SYS_DPAA_RMAN if !NOBQFMAN
York Sun22120f12016-12-28 08:43:46 -0800908 select SYS_FSL_DDR_VER_47
York Sun63659ff2016-12-28 08:43:43 -0800909 select SYS_FSL_ERRATUM_A004468
910 select SYS_FSL_ERRATUM_A005871
911 select SYS_FSL_ERRATUM_A006261
912 select SYS_FSL_ERRATUM_A006379
913 select SYS_FSL_ERRATUM_A006593
Tom Rini601483f2022-06-16 14:04:40 -0400914 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
York Sun63659ff2016-12-28 08:43:43 -0800915 select SYS_FSL_ERRATUM_A007798
Tony O'Brien09bfd962016-12-02 09:22:34 +1300916 select SYS_FSL_ERRATUM_A007815
Darwin Dingel06ad9702016-10-25 09:48:01 +1300917 select SYS_FSL_ERRATUM_A007907
Jaiprakash Singh164a5af2020-06-02 12:44:02 +0530918 select SYS_FSL_ERRATUM_A008109
York Sun63659ff2016-12-28 08:43:43 -0800919 select SYS_FSL_ERRATUM_A009942
York Sund26e34c2016-12-28 08:43:40 -0800920 select SYS_FSL_HAS_DDR3
York Sun2c2e2c92016-12-28 08:43:30 -0800921 select SYS_FSL_HAS_SEC
York Sun73717742016-12-28 08:43:49 -0800922 select SYS_FSL_QORIQ_CHASSIS2
Tom Rini4143a232022-07-31 21:08:28 -0400923 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
York Sun90b80382016-12-28 08:43:31 -0800924 select SYS_FSL_SEC_BE
York Sun2c2e2c92016-12-28 08:43:30 -0800925 select SYS_FSL_SEC_COMPAT_4
Tom Riniff4e87c2022-07-31 21:08:29 -0400926 select SYS_FSL_SRIO_LIODN
927 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
928 select SYS_FSL_USB_DUAL_PHY_ENABLE
Tom Rini2db82bf2022-11-16 13:10:34 -0500929 select SYS_PMAN if !NOBQFMAN
York Sun48512782016-12-28 08:43:50 -0800930 select SYS_PPC64
Prabhakar Kushwahad98b98d2017-02-02 15:01:13 +0530931 select FSL_IFC
Simon Glass3bf926c2017-06-14 21:28:24 -0600932 imply CMD_SATA
Tom Rini8f1a80e2017-07-28 21:31:42 -0400933 imply CMD_NAND
Christophe Leroyfa379222017-08-04 16:34:40 -0600934 imply CMD_REGINFO
Tuomas Tynkkynen9920d152017-12-08 15:36:17 +0200935 imply FSL_SATA
York Sun05cb79a2016-12-02 10:44:34 -0800936
Jagdish Gediya96699f02018-09-03 21:35:10 +0530937config MPC85XX_HAVE_RESET_VECTOR
938 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
939 depends on MPC85xx
940
Tom Rinia3041d92022-02-23 12:28:15 -0500941config BTB
942 bool "toggle branch predition"
943
York Sunf8dee362016-12-28 08:43:27 -0800944config BOOKE
945 bool
946 default y
947
948config E500
949 bool
950 default y
951 help
952 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
953
954config E500MC
955 bool
Tom Rinia3041d92022-02-23 12:28:15 -0500956 select BTB
Simon Glass6500ec72017-08-04 16:34:34 -0600957 imply CMD_PCI
York Sunf8dee362016-12-28 08:43:27 -0800958 help
959 Enble PowerPC E500MC core
960
Tom Rinif2428ac2022-03-24 17:18:01 -0400961config E5500
962 bool
963
York Sun9ec10102016-12-28 08:43:48 -0800964config E6500
965 bool
Tom Rinia3041d92022-02-23 12:28:15 -0500966 select BTB
York Sun9ec10102016-12-28 08:43:48 -0800967 help
968 Enable PowerPC E6500 core
969
Tom Rini2db82bf2022-11-16 13:10:34 -0500970config NOBQFMAN
971 bool
972
York Sun05cb79a2016-12-02 10:44:34 -0800973config FSL_LAW
974 bool
975 help
976 Use Freescale common code for Local Access Window
York Sun26bc57d2016-11-21 13:35:41 -0800977
Tom Rini1e7750f2022-06-16 14:04:34 -0400978config HETROGENOUS_CLUSTERS
979 bool
980
York Sun3f82b562016-11-23 12:30:40 -0800981config MAX_CPUS
982 int "Maximum number of CPUs permitted for MPC85xx"
983 default 12 if ARCH_T4240
Tom Riniec6b37c2021-05-23 10:58:05 -0400984 default 8 if ARCH_P4080
York Sun3f82b562016-11-23 12:30:40 -0800985 default 4 if ARCH_B4860 || \
986 ARCH_P2041 || \
987 ARCH_P3041 || \
988 ARCH_P5040 || \
989 ARCH_T1040 || \
990 ARCH_T1042 || \
Tom Rini2322b952021-02-20 20:06:21 -0500991 ARCH_T2080
York Sun3f82b562016-11-23 12:30:40 -0800992 default 2 if ARCH_B4420 || \
993 ARCH_BSC9132 || \
York Sun3f82b562016-11-23 12:30:40 -0800994 ARCH_P1020 || \
995 ARCH_P1021 || \
York Sun3f82b562016-11-23 12:30:40 -0800996 ARCH_P1023 || \
997 ARCH_P1024 || \
998 ARCH_P1025 || \
999 ARCH_P2020 || \
York Sun3f82b562016-11-23 12:30:40 -08001000 ARCH_T1024
1001 default 1
1002 help
1003 Set this number to the maximum number of possible CPUs in the SoC.
1004 SoCs may have multiple clusters with each cluster may have multiple
1005 ports. If some ports are reserved but higher ports are used for
1006 cores, count the reserved ports. This will allocate enough memory
1007 in spin table to properly handle all cores.
1008
York Sun830fc1b2016-12-01 13:26:06 -08001009config SYS_CCSRBAR_DEFAULT
1010 hex "Default CCSRBAR address"
1011 default 0xff700000 if ARCH_BSC9131 || \
1012 ARCH_BSC9132 || \
1013 ARCH_C29X || \
1014 ARCH_MPC8536 || \
1015 ARCH_MPC8540 || \
York Sun830fc1b2016-12-01 13:26:06 -08001016 ARCH_MPC8544 || \
1017 ARCH_MPC8548 || \
York Sun830fc1b2016-12-01 13:26:06 -08001018 ARCH_MPC8560 || \
York Sun830fc1b2016-12-01 13:26:06 -08001019 ARCH_P1010 || \
1020 ARCH_P1011 || \
1021 ARCH_P1020 || \
1022 ARCH_P1021 || \
York Sun830fc1b2016-12-01 13:26:06 -08001023 ARCH_P1024 || \
1024 ARCH_P1025 || \
1025 ARCH_P2020
1026 default 0xff600000 if ARCH_P1023
1027 default 0xfe000000 if ARCH_B4420 || \
1028 ARCH_B4860 || \
1029 ARCH_P2041 || \
1030 ARCH_P3041 || \
1031 ARCH_P4080 || \
York Sun830fc1b2016-12-01 13:26:06 -08001032 ARCH_P5040 || \
York Sun830fc1b2016-12-01 13:26:06 -08001033 ARCH_T1024 || \
1034 ARCH_T1040 || \
1035 ARCH_T1042 || \
1036 ARCH_T2080 || \
York Sun830fc1b2016-12-01 13:26:06 -08001037 ARCH_T4240
1038 default 0xe0000000 if ARCH_QEMU_E500
1039 help
1040 Default value of CCSRBAR comes from power-on-reset. It
1041 is fixed on each SoC. Some SoCs can have different value
1042 if changed by pre-boot regime. The value here must match
1043 the current value in SoC. If not sure, do not change.
1044
Tom Rini2db82bf2022-11-16 13:10:34 -05001045config SYS_DPAA_PME
1046 bool
1047
1048config SYS_DPAA_DCE
1049 bool
1050
1051config SYS_DPAA_RMAN
1052 bool
1053
Tom Rinifdd0da42022-03-11 09:11:59 -05001054config A003399_NOR_WORKAROUND
1055 bool
1056 help
1057 Enables a workaround for IFC erratum A003399. It is only required
1058 during NOR boot.
1059
Tom Rini5f7c8862022-03-11 09:12:00 -05001060config A008044_WORKAROUND
1061 bool
1062 help
1063 Enables a workaround for T1040/T1042 erratum A008044. It is only
1064 required during NAND boot and valid for Rev 1.0 SoC revision
1065
York Sun63659ff2016-12-28 08:43:43 -08001066config SYS_FSL_ERRATUM_A004468
1067 bool
1068
1069config SYS_FSL_ERRATUM_A004477
1070 bool
1071
1072config SYS_FSL_ERRATUM_A004508
1073 bool
1074
1075config SYS_FSL_ERRATUM_A004580
1076 bool
1077
1078config SYS_FSL_ERRATUM_A004699
1079 bool
1080
1081config SYS_FSL_ERRATUM_A004849
1082 bool
1083
1084config SYS_FSL_ERRATUM_A004510
1085 bool
1086
1087config SYS_FSL_ERRATUM_A004510_SVR_REV
1088 hex
1089 depends on SYS_FSL_ERRATUM_A004510
1090 default 0x20 if ARCH_P4080
1091 default 0x10
1092
1093config SYS_FSL_ERRATUM_A004510_SVR_REV2
1094 hex
1095 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1096 default 0x11
1097
1098config SYS_FSL_ERRATUM_A005125
1099 bool
1100
1101config SYS_FSL_ERRATUM_A005434
1102 bool
1103
1104config SYS_FSL_ERRATUM_A005812
1105 bool
1106
1107config SYS_FSL_ERRATUM_A005871
1108 bool
1109
Chris Packham4eaf7f52018-10-04 20:03:53 +13001110config SYS_FSL_ERRATUM_A005275
1111 bool
1112
York Sun63659ff2016-12-28 08:43:43 -08001113config SYS_FSL_ERRATUM_A006261
1114 bool
1115
1116config SYS_FSL_ERRATUM_A006379
1117 bool
1118
1119config SYS_FSL_ERRATUM_A006384
1120 bool
1121
1122config SYS_FSL_ERRATUM_A006475
1123 bool
1124
1125config SYS_FSL_ERRATUM_A006593
1126 bool
1127
1128config SYS_FSL_ERRATUM_A007075
1129 bool
1130
1131config SYS_FSL_ERRATUM_A007186
1132 bool
1133
1134config SYS_FSL_ERRATUM_A007212
1135 bool
1136
Tony O'Brien09bfd962016-12-02 09:22:34 +13001137config SYS_FSL_ERRATUM_A007815
1138 bool
1139
York Sun63659ff2016-12-28 08:43:43 -08001140config SYS_FSL_ERRATUM_A007798
1141 bool
1142
Darwin Dingel06ad9702016-10-25 09:48:01 +13001143config SYS_FSL_ERRATUM_A007907
1144 bool
1145
York Sun63659ff2016-12-28 08:43:43 -08001146config SYS_FSL_ERRATUM_A008044
1147 bool
Tom Rini5f7c8862022-03-11 09:12:00 -05001148 select A008044_WORKAROUND if MTD_RAW_NAND
York Sun63659ff2016-12-28 08:43:43 -08001149
1150config SYS_FSL_ERRATUM_CPC_A002
1151 bool
1152
1153config SYS_FSL_ERRATUM_CPC_A003
1154 bool
1155
1156config SYS_FSL_ERRATUM_CPU_A003999
1157 bool
1158
1159config SYS_FSL_ERRATUM_ELBC_A001
1160 bool
1161
1162config SYS_FSL_ERRATUM_I2C_A004447
1163 bool
1164
1165config SYS_FSL_A004447_SVR_REV
1166 hex
1167 depends on SYS_FSL_ERRATUM_I2C_A004447
1168 default 0x00 if ARCH_MPC8548
1169 default 0x10 if ARCH_P1010
1170 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
Tom Rinia99dab12021-02-20 20:06:30 -05001171 default 0x20 if ARCH_P3041 || ARCH_P4080
York Sun63659ff2016-12-28 08:43:43 -08001172
1173config SYS_FSL_ERRATUM_IFC_A002769
1174 bool
1175
1176config SYS_FSL_ERRATUM_IFC_A003399
1177 bool
1178
1179config SYS_FSL_ERRATUM_NMG_CPU_A011
1180 bool
1181
1182config SYS_FSL_ERRATUM_NMG_ETSEC129
1183 bool
1184
1185config SYS_FSL_ERRATUM_NMG_LBC103
1186 bool
1187
1188config SYS_FSL_ERRATUM_P1010_A003549
1189 bool
1190
1191config SYS_FSL_ERRATUM_SATA_A001
1192 bool
1193
1194config SYS_FSL_ERRATUM_SEC_A003571
1195 bool
1196
1197config SYS_FSL_ERRATUM_SRIO_A004034
1198 bool
1199
1200config SYS_FSL_ERRATUM_USB14
1201 bool
1202
Tom Rinif76750d2021-12-11 14:55:51 -05001203config SYS_HAS_SERDES
1204 bool
1205
York Sun63659ff2016-12-28 08:43:43 -08001206config SYS_P4080_ERRATUM_CPU22
1207 bool
1208
1209config SYS_P4080_ERRATUM_PCIE_A003
1210 bool
1211
1212config SYS_P4080_ERRATUM_SERDES8
1213 bool
1214
1215config SYS_P4080_ERRATUM_SERDES9
1216 bool
1217
1218config SYS_P4080_ERRATUM_SERDES_A001
1219 bool
1220
1221config SYS_P4080_ERRATUM_SERDES_A005
1222 bool
1223
Hou Zhiqiangc16dfd02019-05-22 22:46:03 +08001224config FSL_PCIE_DISABLE_ASPM
1225 bool
1226
Hou Zhiqiang2b12f6c2019-05-23 11:52:44 +08001227config FSL_PCIE_RESET
1228 bool
1229
Tom Rini2db82bf2022-11-16 13:10:34 -05001230config SYS_PMAN
1231 bool
1232
Tom Riniff4e87c2022-07-31 21:08:29 -04001233config SYS_FSL_RAID_ENGINE
1234 bool
1235
1236config SYS_FSL_RMU
1237 bool
1238
York Sun73717742016-12-28 08:43:49 -08001239config SYS_FSL_QORIQ_CHASSIS1
1240 bool
1241
1242config SYS_FSL_QORIQ_CHASSIS2
1243 bool
1244
York Sun8303acb2016-12-01 14:05:02 -08001245config SYS_FSL_NUM_LAWS
1246 int "Number of local access windows"
1247 depends on FSL_LAW
1248 default 32 if ARCH_B4420 || \
1249 ARCH_B4860 || \
1250 ARCH_P2041 || \
1251 ARCH_P3041 || \
1252 ARCH_P4080 || \
York Sun8303acb2016-12-01 14:05:02 -08001253 ARCH_P5040 || \
1254 ARCH_T2080 || \
York Sun8303acb2016-12-01 14:05:02 -08001255 ARCH_T4240
Tom Rini6c3d9932021-05-14 21:34:22 -04001256 default 16 if ARCH_T1024 || \
York Sun8303acb2016-12-01 14:05:02 -08001257 ARCH_T1040 || \
1258 ARCH_T1042
1259 default 12 if ARCH_BSC9131 || \
1260 ARCH_BSC9132 || \
1261 ARCH_C29X || \
1262 ARCH_MPC8536 || \
York Sun8303acb2016-12-01 14:05:02 -08001263 ARCH_P1010 || \
1264 ARCH_P1011 || \
1265 ARCH_P1020 || \
1266 ARCH_P1021 || \
York Sun8303acb2016-12-01 14:05:02 -08001267 ARCH_P1023 || \
1268 ARCH_P1024 || \
1269 ARCH_P1025 || \
1270 ARCH_P2020
1271 default 10 if ARCH_MPC8544 || \
Tom Rini80696892021-05-14 21:34:23 -04001272 ARCH_MPC8548
York Sun8303acb2016-12-01 14:05:02 -08001273 default 8 if ARCH_MPC8540 || \
York Sun8303acb2016-12-01 14:05:02 -08001274 ARCH_MPC8560
1275 help
1276 Number of local access windows. This is fixed per SoC.
1277 If not sure, do not change.
1278
Tom Rini7da6a9e2022-07-23 13:05:11 -04001279config SYS_FSL_CORES_PER_CLUSTER
1280 int
1281 depends on SYS_FSL_QORIQ_CHASSIS2
1282 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
1283 default 2 if ARCH_B4420
1284 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
1285
York Sun9ec10102016-12-28 08:43:48 -08001286config SYS_FSL_THREADS_PER_CORE
1287 int
Tom Rini7da6a9e2022-07-23 13:05:11 -04001288 depends on SYS_FSL_QORIQ_CHASSIS2
York Sun9ec10102016-12-28 08:43:48 -08001289 default 2 if E6500
1290 default 1
1291
York Sun26e79b62016-12-28 08:43:28 -08001292config SYS_NUM_TLBCAMS
1293 int "Number of TLB CAM entries"
1294 default 64 if E500MC
1295 default 16
1296 help
1297 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1298 16 for other E500 SoCs.
1299
Tom Rini1e7750f2022-06-16 14:04:34 -04001300if HETROGENOUS_CLUSTERS
1301
1302config SYS_MAPLE
1303 def_bool y
1304
1305config SYS_CPRI
1306 def_bool y
1307
1308config PPC_CLUSTER_START
1309 int
1310 default 0
1311
1312config DSP_CLUSTER_START
1313 int
1314 default 1
1315
1316config SYS_CPRI_CLK
1317 int
1318 default 3
1319
1320config SYS_ULB_CLK
1321 int
1322 default 4
1323
1324config SYS_ETVPE_CLK
1325 int
1326 default 1
1327endif
1328
Tom Rini22a22832022-10-28 20:27:00 -04001329config SYS_L2_SIZE_256KB
1330 bool
1331
1332config SYS_L2_SIZE_512KB
1333 bool
1334
1335config SYS_L2_SIZE
1336 int
1337 default 262144 if SYS_L2_SIZE_256KB
1338 default 524288 if SYS_L2_SIZE_512KB
1339
Tom Rinib40d2b22022-03-18 08:38:32 -04001340config BACKSIDE_L2_CACHE
1341 bool
1342
Tom Rinib85d7592022-10-28 20:27:01 -04001343config SYS_L3_SIZE_256KB
1344 bool
1345
1346config SYS_L3_SIZE_512KB
1347 bool
1348
1349config SYS_L3_SIZE_1024KB
1350 bool
1351
1352config SYS_L3_SIZE
1353 int
1354 default 262144 if SYS_L3_SIZE_256KB
1355 default 524288 if SYS_L3_SIZE_512KB
1356 default 1048576 if SYS_L3_SIZE_512KB
1357
York Sun48512782016-12-28 08:43:50 -08001358config SYS_PPC64
1359 bool
1360
York Sun53c95382016-12-28 08:43:29 -08001361config SYS_PPC_E500_USE_DEBUG_TLB
1362 bool
1363
Prabhakar Kushwaha06878972017-02-02 15:01:48 +05301364config FSL_ELBC
1365 bool
1366
York Sun53c95382016-12-28 08:43:29 -08001367config SYS_PPC_E500_DEBUG_TLB
1368 int "Temporary TLB entry for external debugger"
1369 depends on SYS_PPC_E500_USE_DEBUG_TLB
1370 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1371 default 1 if ARCH_MPC8536
Tom Rinied7fe2b2021-05-14 21:34:25 -04001372 default 2 if ARCH_P1011 || \
York Sun53c95382016-12-28 08:43:29 -08001373 ARCH_P1020 || \
1374 ARCH_P1021 || \
York Sun53c95382016-12-28 08:43:29 -08001375 ARCH_P1024 || \
1376 ARCH_P1025 || \
1377 ARCH_P2020
1378 default 3 if ARCH_P1010 || \
1379 ARCH_BSC9132 || \
1380 ARCH_C29X
1381 help
1382 Select a temporary TLB entry to be used during boot to work
1383 around limitations in e500v1 and e500v2 external debugger
1384 support. This reduces the portions of the boot code where
1385 breakpoints and single stepping do not work. The value of this
1386 symbol should be set to the TLB1 entry to be used for this
1387 purpose. If unsure, do not change.
1388
Prabhakar Kushwaha1c407072017-02-02 15:01:26 +05301389config SYS_FSL_IFC_CLK_DIV
1390 int "Divider of platform clock"
1391 depends on FSL_IFC
1392 default 2 if ARCH_B4420 || \
1393 ARCH_B4860 || \
1394 ARCH_T1024 || \
Prabhakar Kushwaha1c407072017-02-02 15:01:26 +05301395 ARCH_T1040 || \
1396 ARCH_T1042 || \
Prabhakar Kushwaha1c407072017-02-02 15:01:26 +05301397 ARCH_T4240
1398 default 1
1399 help
1400 Defines divider of platform clock(clock input to
1401 IFC controller).
1402
Prabhakar Kushwahaadd63f92017-02-02 15:02:00 +05301403config SYS_FSL_LBC_CLK_DIV
1404 int "Divider of platform clock"
1405 depends on FSL_ELBC || ARCH_MPC8540 || \
Tom Rinia8571332021-05-14 21:34:20 -04001406 ARCH_MPC8548 || \
Tom Rini80696892021-05-14 21:34:23 -04001407 ARCH_MPC8560
Prabhakar Kushwahaadd63f92017-02-02 15:02:00 +05301408
1409 default 2 if ARCH_P2041 || \
1410 ARCH_P3041 || \
1411 ARCH_P4080 || \
Prabhakar Kushwahaadd63f92017-02-02 15:02:00 +05301412 ARCH_P5040
1413 default 1
1414
1415 help
1416 Defines divider of platform clock(clock input to
1417 eLBC controller).
1418
Tom Rinifbc36212022-06-15 12:03:45 -04001419config ENABLE_36BIT_PHYS
1420 bool "Enable 36bit physical address space support"
1421
Tom Rini3dab4052022-06-25 11:02:43 -04001422config SYS_BOOK3E_HV
1423 bool "Category E.HV is supported"
1424 depends on BOOKE
1425
Tom Rini6f6b9702022-07-23 13:05:08 -04001426config FSL_CORENET
1427 bool
1428 select SYS_FSL_CPC
1429
Tom Riniff4e87c2022-07-31 21:08:29 -04001430config FSL_NGPIXIS
1431 bool
1432
Tom Rinif6c1f912022-06-25 11:02:45 -04001433config SYS_CPC_REINIT_F
1434 bool
1435 help
1436 The CPC is configured as SRAM at the time of U-Boot entry and is
1437 required to be re-initialized.
1438
1439config SYS_FSL_CPC
Tom Rini6f6b9702022-07-23 13:05:08 -04001440 bool
Tom Rinif6c1f912022-06-25 11:02:45 -04001441
Tom Rini38d091a2022-06-27 13:35:46 -04001442config SYS_CACHE_STASHING
1443 bool "Enable cache stashing"
1444
Tom Rini4143a232022-07-31 21:08:28 -04001445config SYS_FSL_PCIE_COMPAT_P4080_PCIE
1446 bool
1447
1448config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1449 bool
1450
1451config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1452 bool
1453
1454config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1455 bool
1456
1457config SYS_FSL_PCIE_COMPAT
1458 string
1459 depends on FSL_CORENET
1460 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
1461 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1462 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1463 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1464 help
1465 Defines the string to utilize when trying to match PCIe device tree
1466 nodes for the given platform.
1467
Tom Riniff4e87c2022-07-31 21:08:29 -04001468config SYS_FSL_SINGLE_SOURCE_CLK
1469 bool
1470
1471config SYS_FSL_SRIO_LIODN
1472 bool
1473
1474config SYS_FSL_TBCLK_DIV
1475 int
1476 default 32 if ARCH_P2041 || ARCH_P3041
1477 default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
1478 ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
1479 ARCH_T1024 || ARCH_T2080
1480 default 8
1481 help
1482 Defines the core time base clock divider ratio compared to the system
1483 clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
1484 be 16 or 32. The ratio varies from SoC to Soc.
1485
1486config SYS_FSL_USB1_PHY_ENABLE
1487 bool
1488
1489config SYS_FSL_USB2_PHY_ENABLE
1490 bool
1491
1492config SYS_FSL_USB_DUAL_PHY_ENABLE
1493 bool
1494
Tom Rinide47ff52022-06-10 22:59:37 -04001495config SYS_MPC85XX_NO_RESETVEC
1496 bool "Discard resetvec section and move bootpg section up"
1497 depends on MPC85xx
1498 help
1499 If this variable is specified, the section .resetvec is not kept and
1500 the section .bootpg is placed in the previous 4k of the .text section.
1501
1502config SPL_SYS_MPC85XX_NO_RESETVEC
1503 bool "Discard resetvec section and move bootpg section up, in SPL"
1504 depends on MPC85xx && SPL
1505 help
1506 If this variable is specified, the section .resetvec is not kept and
1507 the section .bootpg is placed in the previous 4k of the .text section,
1508 of the SPL portion of the binary.
1509
1510config TPL_SYS_MPC85XX_NO_RESETVEC
1511 bool "Discard resetvec section and move bootpg section up, in TPL"
1512 depends on MPC85xx && TPL
1513 help
1514 If this variable is specified, the section .resetvec is not kept and
1515 the section .bootpg is placed in the previous 4k of the .text section,
1516 of the SPL portion of the binary.
1517
Rajesh Bhagatc8c01702021-02-15 09:46:14 +01001518config FSL_VIA
1519 bool
1520
Bin Meng1d636a02021-02-25 17:22:58 +08001521source "board/emulation/qemu-ppce500/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +09001522source "board/freescale/mpc8548cds/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +09001523source "board/freescale/p1010rdb/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +09001524source "board/freescale/p1_p2_rdb_pc/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +09001525source "board/freescale/p2041rdb/Kconfig"
Shengzhou Liu48c6f322014-11-24 17:11:56 +08001526source "board/freescale/t102xrdb/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +09001527source "board/freescale/t104xrdb/Kconfig"
1528source "board/freescale/t208xqds/Kconfig"
1529source "board/freescale/t208xrdb/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +09001530source "board/freescale/t4rdb/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +09001531source "board/socrates/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +09001532
1533endmenu