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Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# I2C subsystem configuration
3#
4
Simon Glass59e11eb2021-07-10 21:14:35 -06005menuconfig I2C
6 bool "I2C support"
7 default y
8 help
9 Note:
10 This is a stand-in for an option to enable I2C support. In fact this
11 simply enables building of the I2C directory for U-Boot. The actual
12 I2C feature is enabled by DM_I2C (for driver model) and
13 the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack).
14
15 So at present there is no need to ever disable this option.
16
17 Eventually it will:
18
19 Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot.
20 I2C works with a clock and data line which can be driven by a
21 one or more masters or slaves. It is a fairly complex bus but is
22 widely used as it only needs two lines for communication. Speeds of
23 400kbps are typical but up to 3.4Mbps is supported by some
24 hardware. Enable this option to build the drivers in drivers/i2c as
25 part of a U-Boot build.
26
27if I2C
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +090028
Masahiro Yamadab6036bc2015-01-13 12:44:35 +090029config DM_I2C
30 bool "Enable Driver Model for I2C drivers"
31 depends on DM
32 help
Przemyslaw Marczak705fcf42015-03-31 18:57:17 +020033 Enable driver model for I2C. The I2C uclass interface: probe, read,
34 write and speed, is implemented with the bus drivers operations,
35 which provide methods for bus setting and data transfer. Each chip
Simon Glasscaa4daa2020-12-03 16:55:18 -070036 device (bus child) info is kept as parent plat. The interface
Bartosz Golaszewskie3114822019-07-29 08:58:00 +020037 is defined in include/i2c.h.
Simon Glass4bba9d32015-02-13 12:20:48 -070038
Igor Opaniukd1f3abe2021-02-09 13:52:43 +020039config SPL_DM_I2C
40 bool "Enable Driver Model for I2C drivers in SPL"
41 depends on SPL_DM && DM_I2C
42 default y
43 help
44 Enable driver model for I2C. The I2C uclass interface: probe, read,
45 write and speed, is implemented with the bus drivers operations,
46 which provide methods for bus setting and data transfer. Each chip
47 device (bus child) info is kept as parent platdata. The interface
48 is defined in include/i2c.h.
49
Tom Rini55dabcc2021-08-18 23:12:24 -040050config SYS_I2C_LEGACY
51 bool "Enable legacy I2C subsystem and drivers"
52 depends on !DM_I2C
53 help
54 Enable the legacy I2C subsystem and drivers. While this is
55 deprecated in U-Boot itself, this can be useful in some situations
56 in SPL or TPL.
57
58config SPL_SYS_I2C_LEGACY
59 bool "Enable legacy I2C subsystem and drivers in SPL"
60 depends on SUPPORT_SPL && !SPL_DM_I2C
61 help
62 Enable the legacy I2C subsystem and drivers in SPL. This is useful
63 in some size constrained situations.
64
65config TPL_SYS_I2C_LEGACY
66 bool "Enable legacy I2C subsystem and drivers in TPL"
67 depends on SUPPORT_TPL && !SPL_DM_I2C
68 help
69 Enable the legacy I2C subsystem and drivers in TPL. This is useful
70 in some size constrained situations.
71
Tom Rini52c7e372021-08-18 23:12:25 -040072config SYS_I2C_EARLY_INIT
73 bool "Enable legacy I2C subsystem early in boot"
74 depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
75 help
76 Add the function prototype for i2c_early_init_f which is called in
77 board_early_init_f.
78
Simon Glasscc456bd2015-08-03 08:19:23 -060079config I2C_CROS_EC_TUNNEL
80 tristate "Chrome OS EC tunnel I2C bus"
81 depends on CROS_EC
82 help
83 This provides an I2C bus that will tunnel i2c commands through to
84 the other side of the Chrome OS EC to the I2C bus connected there.
85 This will work whatever the interface used to talk to the EC (SPI,
86 I2C or LPC). Some Chromebooks use this when the hardware design
87 does not allow direct access to the main PMIC from the AP.
88
Simon Glassf48eaf02015-08-03 08:19:24 -060089config I2C_CROS_EC_LDO
90 bool "Provide access to LDOs on the Chrome OS EC"
91 depends on CROS_EC
92 ---help---
93 On many Chromebooks the main PMIC is inaccessible to the AP. This is
94 often dealt with by using an I2C pass-through interface provided by
95 the EC. On some unfortunate models (e.g. Spring) the pass-through
96 is not available, and an LDO message is available instead. This
97 option enables a driver which provides very basic access to those
98 regulators, via the EC. We implement this as an I2C bus which
99 emulates just the TPS65090 messages we know about. This is done to
100 avoid duplicating the logic in the TPS65090 regulator driver for
101 enabling/disabling an LDO.
Simon Glasscc456bd2015-08-03 08:19:23 -0600102
Lukasz Majewskie46f8a32017-03-21 12:08:25 +0100103config I2C_SET_DEFAULT_BUS_NUM
104 bool "Set default I2C bus number"
105 depends on DM_I2C
106 help
107 Set default number of I2C bus to be accessed. This option provides
108 behaviour similar to old (i.e. pre DM) I2C bus driver.
109
110config I2C_DEFAULT_BUS_NUMBER
111 hex "I2C default bus number"
112 depends on I2C_SET_DEFAULT_BUS_NUM
113 default 0x0
114 help
115 Number of default I2C bus to use
116
Przemyslaw Marczakc54473c2015-03-31 18:57:18 +0200117config DM_I2C_GPIO
118 bool "Enable Driver Model for software emulated I2C bus driver"
119 depends on DM_I2C && DM_GPIO
120 help
121 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
122 configuration is given by the device tree. Kernel-style device tree
123 bindings are supported.
124 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
125
Igor Opaniukd1f3abe2021-02-09 13:52:43 +0200126config SPL_DM_I2C_GPIO
127 bool "Enable Driver Model for software emulated I2C bus driver in SPL"
Simon Glass83061db2021-07-10 21:14:30 -0600128 depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO
Igor Opaniukd1f3abe2021-02-09 13:52:43 +0200129 default y
130 help
131 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
132 configuration is given by the device tree. Kernel-style device tree
133 bindings are supported.
134 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
135
Songjun Wu8800e0f2016-06-20 13:22:38 +0800136config SYS_I2C_AT91
137 bool "Atmel I2C driver"
138 depends on DM_I2C && ARCH_AT91
139 help
140 Add support for the Atmel I2C driver. A serious problem is that there
141 is no documented way to issue repeated START conditions for more than
142 two messages, as needed to support combined I2C messages. Use the
143 i2c-gpio driver unless your system can cope with this limitation.
144 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
145
Rayagonda Kokatanur956d57a2020-04-08 11:12:27 +0530146config SYS_I2C_IPROC
147 bool "Broadcom I2C driver"
148 depends on DM_I2C
149 help
150 Broadcom I2C driver.
151 Add support for Broadcom I2C driver.
152 Say yes here to to enable the Broadco I2C driver.
153
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200154config SYS_I2C_FSL
155 bool "Freescale I2C bus driver"
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200156 help
157 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
158 MPC85xx processors.
159
Tom Rini6d5d0c92021-08-18 23:12:35 -0400160if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
161config SYS_FSL_I2C_OFFSET
162 hex "Offset from the IMMR of the address of the first I2C controller"
163
164config SYS_FSL_HAS_I2C2_OFFSET
165 bool "Support a second I2C controller"
166
167config SYS_FSL_I2C2_OFFSET
168 hex "Offset from the IMMR of the address of the second I2C controller"
169 depends on SYS_FSL_HAS_I2C2_OFFSET
170
171config SYS_FSL_HAS_I2C3_OFFSET
172 bool "Support a third I2C controller"
173
174config SYS_FSL_I2C3_OFFSET
175 hex "Offset from the IMMR of the address of the third I2C controller"
176 depends on SYS_FSL_HAS_I2C3_OFFSET
177
178config SYS_FSL_HAS_I2C4_OFFSET
179 bool "Support a fourth I2C controller"
180
181config SYS_FSL_I2C4_OFFSET
182 hex "Offset from the IMMR of the address of the fourth I2C controller"
183 depends on SYS_FSL_HAS_I2C4_OFFSET
184endif
185
Moritz Fischerfdec2d22015-12-28 09:47:11 -0800186config SYS_I2C_CADENCE
187 tristate "Cadence I2C Controller"
Michal Simek664e16c2020-08-06 15:18:36 +0200188 depends on DM_I2C
Moritz Fischerfdec2d22015-12-28 09:47:11 -0800189 help
190 Say yes here to select Cadence I2C Host Controller. This controller is
191 e.g. used by Xilinx Zynq.
192
Arthur Li7f5ea252020-06-01 12:56:31 -0700193config SYS_I2C_CA
194 tristate "Cortina-Access I2C Controller"
195 depends on DM_I2C && CORTINA_PLATFORM
Arthur Li7f5ea252020-06-01 12:56:31 -0700196 help
197 Add support for the Cortina Access I2C host controller.
198 Say yes here to select Cortina-Access I2C Host Controller.
199
Adam Ford9f8cf762018-08-10 05:05:22 -0500200config SYS_I2C_DAVINCI
201 bool "Davinci I2C Controller"
202 depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
203 help
204 Say yes here to add support for Davinci and Keystone I2C controller
205
Stefan Roesee32d0db2016-04-28 09:47:17 +0200206config SYS_I2C_DW
207 bool "Designware I2C Controller"
Stefan Roesee32d0db2016-04-28 09:47:17 +0200208 help
209 Say yes here to select the Designware I2C Host Controller. This
210 controller is used in various SoCs, e.g. the ST SPEAr, Altera
211 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
212
maxims@google.com4dc038f2017-04-17 12:00:30 -0700213config SYS_I2C_ASPEED
214 bool "Aspeed I2C Controller"
215 depends on DM_I2C && ARCH_ASPEED
216 help
217 Say yes here to select Aspeed I2C Host Controller. The driver
218 supports AST2500 and AST2400 controllers, but is very limited.
219 Only single master mode is supported and only byte-by-byte
220 synchronous reads and writes are supported, no Pool Buffers or DMA.
221
Simon Glassabb0b012016-01-17 16:11:44 -0700222config SYS_I2C_INTEL
223 bool "Intel I2C/SMBUS driver"
224 depends on DM_I2C
225 help
226 Add support for the Intel SMBUS driver. So far this driver is just
227 a stub which perhaps some basic init. There is no implementation of
228 the I2C API meaning that any I2C operations will immediately fail
229 for now.
230
Peng Fan7ee3f142017-02-24 09:54:18 +0800231config SYS_I2C_IMX_LPI2C
232 bool "NXP i.MX LPI2C driver"
Peng Fan7ee3f142017-02-24 09:54:18 +0800233 help
234 Add support for the NXP i.MX LPI2C driver.
235
Trevor Woerner07055562021-06-10 22:37:08 -0400236config SYS_I2C_LPC32XX
237 bool "LPC32XX I2C driver"
238 depends on ARCH_LPC32XX
239 help
240 Enable support for the LPC32xx I2C driver.
241
Beniamino Galvanif8d9ca12017-10-29 10:09:00 +0100242config SYS_I2C_MESON
243 bool "Amlogic Meson I2C driver"
244 depends on DM_I2C && ARCH_MESON
245 help
Beniamino Galvani4ecbb8b2017-11-26 17:40:54 +0100246 Add support for the I2C controller available in Amlogic Meson
247 SoCs. The controller supports programmable bus speed including
248 standard (100kbits/s) and fast (400kbit/s) speed and allows the
249 software to define a flexible format of the bit streams. It has an
250 internal buffer holding up to 8 bytes for transfers and supports
251 both 7-bit and 10-bit addresses.
Beniamino Galvanif8d9ca12017-10-29 10:09:00 +0100252
Jagan Teki72c8c102016-12-06 00:00:57 +0100253config SYS_I2C_MXC
Sriram Dash942ecc82018-02-06 11:26:30 +0530254 bool "NXP MXC I2C driver"
Jagan Teki72c8c102016-12-06 00:00:57 +0100255 help
Chris Packham74751452019-01-13 22:13:25 +1300256 Add support for the NXP I2C driver. This supports up to four bus
257 channels and operating on standard mode up to 100 kbits/s and fast
258 mode up to 400 kbits/s.
Jagan Teki72c8c102016-12-06 00:00:57 +0100259
Tom Rini15e7b762021-08-18 23:12:33 -0400260if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
Sriram Dash942ecc82018-02-06 11:26:30 +0530261config SYS_I2C_MXC_I2C1
262 bool "NXP MXC I2C1"
263 help
264 Add support for NXP MXC I2C Controller 1.
265 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
266
267config SYS_I2C_MXC_I2C2
268 bool "NXP MXC I2C2"
269 help
270 Add support for NXP MXC I2C Controller 2.
271 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
272
273config SYS_I2C_MXC_I2C3
274 bool "NXP MXC I2C3"
275 help
276 Add support for NXP MXC I2C Controller 3.
277 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
278
279config SYS_I2C_MXC_I2C4
280 bool "NXP MXC I2C4"
281 help
282 Add support for NXP MXC I2C Controller 4.
283 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
Sriram Dashfa452192018-02-06 11:26:31 +0530284
285config SYS_I2C_MXC_I2C5
286 bool "NXP MXC I2C5"
287 help
288 Add support for NXP MXC I2C Controller 5.
289 Required for SoCs which have I2C MXC controller 5 eg LX2160A
290
291config SYS_I2C_MXC_I2C6
292 bool "NXP MXC I2C6"
293 help
294 Add support for NXP MXC I2C Controller 6.
295 Required for SoCs which have I2C MXC controller 6 eg LX2160A
296
297config SYS_I2C_MXC_I2C7
298 bool "NXP MXC I2C7"
299 help
300 Add support for NXP MXC I2C Controller 7.
301 Required for SoCs which have I2C MXC controller 7 eg LX2160A
302
303config SYS_I2C_MXC_I2C8
304 bool "NXP MXC I2C8"
305 help
306 Add support for NXP MXC I2C Controller 8.
307 Required for SoCs which have I2C MXC controller 8 eg LX2160A
Sriram Dash942ecc82018-02-06 11:26:30 +0530308endif
309
310if SYS_I2C_MXC_I2C1
311config SYS_MXC_I2C1_SPEED
312 int "I2C Channel 1 speed"
Tom Rini2ce7b652021-02-09 08:03:10 -0500313 default 40000000 if TARGET_LS2080A_EMU
Sriram Dash942ecc82018-02-06 11:26:30 +0530314 default 100000
315 help
316 MXC I2C Channel 1 speed
317
318config SYS_MXC_I2C1_SLAVE
Tom Rini15e7b762021-08-18 23:12:33 -0400319 hex "I2C1 Slave"
Sriram Dash942ecc82018-02-06 11:26:30 +0530320 default 0
321 help
322 MXC I2C1 Slave
323endif
324
325if SYS_I2C_MXC_I2C2
326config SYS_MXC_I2C2_SPEED
327 int "I2C Channel 2 speed"
Tom Rini2ce7b652021-02-09 08:03:10 -0500328 default 40000000 if TARGET_LS2080A_EMU
Sriram Dash942ecc82018-02-06 11:26:30 +0530329 default 100000
330 help
331 MXC I2C Channel 2 speed
332
333config SYS_MXC_I2C2_SLAVE
Tom Rini15e7b762021-08-18 23:12:33 -0400334 hex "I2C2 Slave"
Sriram Dash942ecc82018-02-06 11:26:30 +0530335 default 0
336 help
337 MXC I2C2 Slave
338endif
339
340if SYS_I2C_MXC_I2C3
341config SYS_MXC_I2C3_SPEED
342 int "I2C Channel 3 speed"
343 default 100000
344 help
345 MXC I2C Channel 3 speed
346
347config SYS_MXC_I2C3_SLAVE
Tom Rini15e7b762021-08-18 23:12:33 -0400348 hex "I2C3 Slave"
Sriram Dash942ecc82018-02-06 11:26:30 +0530349 default 0
350 help
351 MXC I2C3 Slave
352endif
353
354if SYS_I2C_MXC_I2C4
355config SYS_MXC_I2C4_SPEED
356 int "I2C Channel 4 speed"
357 default 100000
358 help
359 MXC I2C Channel 4 speed
360
361config SYS_MXC_I2C4_SLAVE
Tom Rini15e7b762021-08-18 23:12:33 -0400362 hex "I2C4 Slave"
Sriram Dash942ecc82018-02-06 11:26:30 +0530363 default 0
364 help
365 MXC I2C4 Slave
366endif
367
Sriram Dashfa452192018-02-06 11:26:31 +0530368if SYS_I2C_MXC_I2C5
369config SYS_MXC_I2C5_SPEED
370 int "I2C Channel 5 speed"
371 default 100000
372 help
373 MXC I2C Channel 5 speed
374
375config SYS_MXC_I2C5_SLAVE
Tom Rini15e7b762021-08-18 23:12:33 -0400376 hex "I2C5 Slave"
Sriram Dashfa452192018-02-06 11:26:31 +0530377 default 0
378 help
379 MXC I2C5 Slave
380endif
381
382if SYS_I2C_MXC_I2C6
383config SYS_MXC_I2C6_SPEED
384 int "I2C Channel 6 speed"
385 default 100000
386 help
387 MXC I2C Channel 6 speed
388
389config SYS_MXC_I2C6_SLAVE
Tom Rini15e7b762021-08-18 23:12:33 -0400390 hex "I2C6 Slave"
Sriram Dashfa452192018-02-06 11:26:31 +0530391 default 0
392 help
393 MXC I2C6 Slave
394endif
395
396if SYS_I2C_MXC_I2C7
397config SYS_MXC_I2C7_SPEED
398 int "I2C Channel 7 speed"
399 default 100000
400 help
401 MXC I2C Channel 7 speed
402
403config SYS_MXC_I2C7_SLAVE
Tom Rini15e7b762021-08-18 23:12:33 -0400404 hex "I2C7 Slave"
Sriram Dashfa452192018-02-06 11:26:31 +0530405 default 0
406 help
407 MXC I2C7 Slave
408endif
409
410if SYS_I2C_MXC_I2C8
411config SYS_MXC_I2C8_SPEED
412 int "I2C Channel 8 speed"
413 default 100000
414 help
415 MXC I2C Channel 8 speed
416
417config SYS_MXC_I2C8_SLAVE
Tom Rini15e7b762021-08-18 23:12:33 -0400418 hex "I2C8 Slave"
Sriram Dashfa452192018-02-06 11:26:31 +0530419 default 0
420 help
421 MXC I2C8 Slave
422endif
423
Stefan Boschc25e9e02020-07-10 19:07:28 +0200424config SYS_I2C_NEXELL
425 bool "Nexell I2C driver"
426 depends on DM_I2C
427 help
428 Add support for the Nexell I2C driver. This is used with various
429 Nexell parts such as S5Pxx18 series SoCs. All chips
430 have several I2C ports and all are provided, controlled by the
431 device tree.
432
Pragnesh Patelb2d4cbe2020-11-14 14:42:34 +0530433config SYS_I2C_OCORES
434 bool "ocores I2C driver"
435 depends on DM_I2C
436 help
437 Add support for ocores I2C controller. For details see
438 https://opencores.org/projects/i2c
439
Adam Forddaa0f052017-08-07 13:11:34 -0500440config SYS_I2C_OMAP24XX
441 bool "TI OMAP2+ I2C driver"
Vignesh R14106bc2019-06-04 18:08:11 -0500442 depends on ARCH_OMAP2PLUS || ARCH_K3
Adam Forddaa0f052017-08-07 13:11:34 -0500443 help
444 Add support for the OMAP2+ I2C driver.
445
Marek Vasuta06a0ac2018-04-21 18:57:28 +0200446config SYS_I2C_RCAR_I2C
447 bool "Renesas RCar I2C driver"
448 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
449 help
450 Support for Renesas RCar I2C controller.
451
Marek Vasut9e75ea42017-11-28 08:02:27 +0100452config SYS_I2C_RCAR_IIC
453 bool "Renesas RCar Gen3 IIC driver"
Marek Vasutf51155e2018-02-17 02:17:40 +0100454 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
Marek Vasut9e75ea42017-11-28 08:02:27 +0100455 help
456 Support for Renesas RCar Gen3 IIC controller.
457
Simon Glass34374692015-08-30 16:55:39 -0600458config SYS_I2C_ROCKCHIP
459 bool "Rockchip I2C driver"
460 depends on DM_I2C
461 help
462 Add support for the Rockchip I2C driver. This is used with various
463 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
Chris Packham74751452019-01-13 22:13:25 +1300464 have several I2C ports and all are provided, controlled by the
Simon Glass34374692015-08-30 16:55:39 -0600465 device tree.
466
Simon Glass1174aad2015-03-06 13:19:04 -0700467config SYS_I2C_SANDBOX
468 bool "Sandbox I2C driver"
469 depends on SANDBOX && DM_I2C
470 help
471 Enable I2C support for sandbox. This is an emulation of a real I2C
472 bus. Devices can be attached to the bus using the device tree
Masahiro Yamadac77c7db2017-02-11 12:39:55 +0900473 which specifies the driver to use. See sandbox.dts as an example.
Simon Glass1174aad2015-03-06 13:19:04 -0700474
Tom Rini6aa07542021-08-18 23:12:34 -0400475config SYS_I2C_SH
476 bool "Legacy SuperH I2C interface"
477 depends on ARCH_RMOBILE && SYS_I2C_LEGACY
478 help
479 Enable the legacy SuperH I2C interface.
480
481if SYS_I2C_SH
482config SYS_I2C_SH_NUM_CONTROLLERS
483 int
484 default 5
485
486config SYS_I2C_SH_BASE0
487 hex
488 default 0xE6820000
489
490config SYS_I2C_SH_BASE1
491 hex
492 default 0xE6822000
493
494config SYS_I2C_SH_BASE2
495 hex
496 default 0xE6824000
497
498config SYS_I2C_SH_BASE3
499 hex
500 default 0xE6826000
501
502config SYS_I2C_SH_BASE4
503 hex
504 default 0xE6828000
505
506config SH_I2C_8BIT
507 bool
508 default y
509
510config SH_I2C_DATA_HIGH
511 int
512 default 4
513
514config SH_I2C_DATA_LOW
515 int
516 default 5
517
518config SH_I2C_CLOCK
519 int
520 default 104000000
521endif
522
Tom Rinide695722021-08-17 17:59:46 -0400523config SYS_I2C_SOFT
524 bool "Legacy software I2C interface"
525 help
526 Enable the legacy software defined I2C interface
527
528config SYS_I2C_SOFT_SPEED
529 int "Software I2C bus speed"
530 depends on SYS_I2C_SOFT
531 default 100000
532 help
533 Speed of the software I2C bus
534
535config SYS_I2C_SOFT_SLAVE
536 hex "Software I2C slave address"
537 depends on SYS_I2C_SOFT
538 default 0xfe
539 help
540 Slave address of the software I2C bus
541
Suneel Garapati5c2c3e82020-05-26 14:13:07 +0200542config SYS_I2C_OCTEON
543 bool "Octeon II/III/TX/TX2 I2C driver"
544 depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
545 default y
546 help
547 Add support for the Marvell Octeon I2C driver. This is used with
548 various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
549 chips have several I2C ports and all are provided, controlled by
550 the device tree.
551
Jaehoon Chung1d61ad92017-01-09 14:47:52 +0900552config SYS_I2C_S3C24X0
553 bool "Samsung I2C driver"
Tom Rini0283da42021-08-17 17:59:42 -0400554 depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
Jaehoon Chung1d61ad92017-01-09 14:47:52 +0900555 help
556 Support for Samsung I2C controller as Samsung SoCs.
Simon Glass1174aad2015-03-06 13:19:04 -0700557
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200558config SYS_I2C_STM32F7
559 bool "STMicroelectronics STM32F7 I2C support"
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100560 depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
Patrice Chotard4fadcaf2017-08-09 14:45:27 +0200561 help
562 Enable this option to add support for STM32 I2C controller
563 introduced with STM32F7/H7 SoCs. This I2C controller supports :
564 _ Slave and master modes
565 _ Multimaster capability
566 _ Standard-mode (up to 100 kHz)
567 _ Fast-mode (up to 400 kHz)
568 _ Fast-mode Plus (up to 1 MHz)
569 _ 7-bit and 10-bit addressing mode
570 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
571 _ All 7-bit addresses acknowledge mode
572 _ General call
573 _ Programmable setup and hold times
574 _ Easy to use event management
575 _ Optional clock stretching
576 _ Software reset
577
Samuel Holland104950a2021-10-08 00:17:20 -0500578config SYS_I2C_SUN6I_P2WI
579 bool "Allwinner sun6i P2WI controller"
580 depends on ARCH_SUNXI
581 help
582 Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded
583 in the Allwinner A31 and A31s SOCs. This interface is used to connect
584 to specific devices like the X-Powers AXP221 PMIC.
585
Samuel Holland3227c852021-10-08 00:17:21 -0500586config SYS_I2C_SUN8I_RSB
587 bool "Allwinner sun8i Reduced Serial Bus controller"
588 depends on ARCH_SUNXI
589 help
590 Support for Allwinner's Reduced Serial Bus (RSB) controller. This
591 controller is responsible for communicating with various RSB based
592 devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs.
593
Jassi Brar4483fba2021-06-04 18:44:48 +0900594config SYS_I2C_SYNQUACER
595 bool "Socionext SynQuacer I2C controller"
596 depends on ARCH_SYNQUACER && DM_I2C
597 help
598 Support for Socionext Synquacer I2C controller. This I2C controller
599 will be used for RTC and LS-connector on DeveloperBox.
600
Peter Robinson02253d42019-02-20 12:17:26 +0000601config SYS_I2C_TEGRA
602 bool "NVIDIA Tegra internal I2C controller"
Trevor Woerner18138ab2020-05-06 08:02:41 -0400603 depends on ARCH_TEGRA
Peter Robinson02253d42019-02-20 12:17:26 +0000604 help
605 Support for NVIDIA I2C controller available in Tegra SoCs.
606
Masahiro Yamada26f820f2015-01-13 12:44:36 +0900607config SYS_I2C_UNIPHIER
608 bool "UniPhier I2C driver"
609 depends on ARCH_UNIPHIER && DM_I2C
610 default y
611 help
Masahiro Yamadab6ef3a32015-05-29 17:30:01 +0900612 Support for UniPhier I2C controller driver. This I2C controller
613 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900614
615config SYS_I2C_UNIPHIER_F
616 bool "UniPhier FIFO-builtin I2C driver"
617 depends on ARCH_UNIPHIER && DM_I2C
618 default y
619 help
Masahiro Yamadab6ef3a32015-05-29 17:30:01 +0900620 Support for UniPhier FIFO-builtin I2C controller driver.
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900621 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
Simon Glass3d1957f2015-08-03 08:19:21 -0600622
Heiko Schochere3bc4bb2018-10-11 07:26:33 +0200623config SYS_I2C_VERSATILE
624 bool "Arm Ltd Versatile I2C bus driver"
Tom Rinic6c26a02021-02-20 20:05:47 -0500625 depends on DM_I2C && TARGET_VEXPRESS64_JUNO
Heiko Schochere3bc4bb2018-10-11 07:26:33 +0200626 help
627 Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
628 controller is present in the development boards manufactured by Arm Ltd.
629
Marek BehĂșn999ac222021-10-09 19:33:37 +0200630config SYS_I2C_MV
631 bool "Marvell PXA (Armada 3720) I2C driver"
632 help
633 Support for PXA based I2C controller used on Armada 3720 SoC.
634 In Linux, this driver is called i2c-pxa.
635
mario.six@gdsys.cc14a6ff22016-07-21 11:57:10 +0200636config SYS_I2C_MVTWSI
637 bool "Marvell I2C driver"
mario.six@gdsys.cc14a6ff22016-07-21 11:57:10 +0200638 help
639 Support for Marvell I2C controllers as used on the orion5x and
640 kirkwood SoC families.
641
Stephen Warren34f1c9f2016-08-08 11:28:27 -0600642config TEGRA186_BPMP_I2C
643 bool "Enable Tegra186 BPMP-based I2C driver"
644 depends on TEGRA186_BPMP
645 help
646 Support for Tegra I2C controllers managed by the BPMP (Boot and
647 Power Management Processor). On Tegra186, some I2C controllers are
648 directly controlled by the main CPU, whereas others are controlled
649 by the BPMP, and can only be accessed by the main CPU via IPC
650 requests to the BPMP. This driver covers the latter case.
651
Tom Rinia5752f82021-08-18 23:12:32 -0400652config SYS_I2C_SLAVE
653 hex "I2C Slave address channel (all buses)"
654 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
655 default 0xfe
656 help
657 I2C Slave address channel 0 for all buses in the legacy drivers.
658 Many boards/controllers/drivers don't support an I2C slave
659 interface so provide a default slave address for them for use in
660 common code. A real value for CONFIG_SYS_I2C_SLAVE should be
661 defined for any board which does support a slave interface and
662 this default used otherwise.
663
664config SYS_I2C_SPEED
665 int "I2C Slave channel 0 speed (all buses)"
666 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
667 default 100000
668 help
669 I2C Slave speed channel 0 for all buses in the legacy drivers.
670
Adam Fordfc760cc2017-08-11 06:39:34 -0500671config SYS_I2C_BUS_MAX
672 int "Max I2C busses"
673 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
674 default 2 if TI816X
675 default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
676 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
677 default 5 if OMAP54XX
678 help
679 Define the maximum number of available I2C buses.
680
Marek Vasutad827a52018-12-19 12:26:27 +0100681config SYS_I2C_XILINX_XIIC
682 bool "Xilinx AXI I2C driver"
683 depends on DM_I2C
684 help
685 Support for Xilinx AXI I2C controller.
686
Mario Six92164212018-01-15 11:08:11 +0100687config SYS_I2C_IHS
688 bool "gdsys IHS I2C driver"
689 depends on DM_I2C
690 help
691 Support for gdsys IHS I2C driver on FPGA bus.
692
Simon Glass3d1957f2015-08-03 08:19:21 -0600693source "drivers/i2c/muxes/Kconfig"
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900694
Simon Glass59e11eb2021-07-10 21:14:35 -0600695endif