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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk71f95112003-06-15 22:40:42 +00002/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00003 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05004 * Andy Fleming
5 *
6 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00007 */
8
9#ifndef _MMC_H_
10#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000011
Andy Fleming272cc702008-10-30 16:41:01 -050012#include <linux/list.h>
Peng Fan3697e592016-09-01 11:13:38 +080013#include <linux/sizes.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000014#include <linux/compiler.h>
Mateusz Zalega07a2d422014-04-30 13:04:15 +020015#include <part.h>
Andy Fleming272cc702008-10-30 16:41:01 -050016
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010017#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
18#define MMC_SUPPORTS_TUNING
19#endif
20#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
21#define MMC_SUPPORTS_TUNING
22#endif
23
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020024/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
25#define SD_VERSION_SD (1U << 31)
26#define MMC_VERSION_MMC (1U << 30)
27
28#define MAKE_SDMMC_VERSION(a, b, c) \
29 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
30#define MAKE_SD_VERSION(a, b, c) \
31 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
32#define MAKE_MMC_VERSION(a, b, c) \
33 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
34
35#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
36 (((u32)(x) >> 16) & 0xff)
37#define EXTRACT_SDMMC_MINOR_VERSION(x) \
38 (((u32)(x) >> 8) & 0xff)
39#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
40 ((u32)(x) & 0xff)
41
42#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
43#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
44#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
45#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
46
47#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
48#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
49#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
50#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
51#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
52#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
53#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
54#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
55#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
Jean-Jacques Hiblotace1bed2018-02-09 12:09:28 +010056#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020057#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
58#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
59#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
Stefan Wahren1a3619c2016-06-16 17:54:06 +000060#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
Andy Fleming272cc702008-10-30 16:41:01 -050061
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020062#define MMC_CAP(mode) (1 << mode)
63#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
64#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
65#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +020066#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
Peng Fan3dd26262018-08-10 14:07:54 +080067#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
Peng Fan44acd492019-07-10 14:43:07 +080068#define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020069
T Karthik Reddy86a94e72019-06-25 13:39:02 +020070#define MMC_CAP_NONREMOVABLE BIT(14)
71#define MMC_CAP_NEEDS_POLL BIT(15)
72#define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
73
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020074#define MMC_MODE_8BIT BIT(30)
75#define MMC_MODE_4BIT BIT(29)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +020076#define MMC_MODE_1BIT BIT(28)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020077#define MMC_MODE_SPI BIT(27)
78
Ɓukasz Majewski62722032012-03-12 22:07:18 +000079
Andy Fleming272cc702008-10-30 16:41:01 -050080#define SD_DATA_4BIT 0x00040000
81
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020082#define IS_SD(x) ((x)->version & SD_VERSION_SD)
Andrew Gabbasov3f2da752015-03-19 07:44:02 -050083#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
Andy Fleming272cc702008-10-30 16:41:01 -050084
85#define MMC_DATA_READ 1
86#define MMC_DATA_WRITE 2
87
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020088#define MMC_CMD_GO_IDLE_STATE 0
89#define MMC_CMD_SEND_OP_COND 1
90#define MMC_CMD_ALL_SEND_CID 2
91#define MMC_CMD_SET_RELATIVE_ADDR 3
92#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050093#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020094#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050095#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020096#define MMC_CMD_SEND_CSD 9
97#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050098#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020099#define MMC_CMD_SEND_STATUS 13
100#define MMC_CMD_SET_BLOCKLEN 16
101#define MMC_CMD_READ_SINGLE_BLOCK 17
102#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200103#define MMC_CMD_SEND_TUNING_BLOCK 19
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200104#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200105#define MMC_CMD_SET_BLOCK_COUNT 23
Andy Fleming272cc702008-10-30 16:41:01 -0500106#define MMC_CMD_WRITE_SINGLE_BLOCK 24
107#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +0000108#define MMC_CMD_ERASE_GROUP_START 35
109#define MMC_CMD_ERASE_GROUP_END 36
110#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200111#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +0000112#define MMC_CMD_SPI_READ_OCR 58
113#define MMC_CMD_SPI_CRC_ON_OFF 59
Amar3690d6d2013-04-27 11:42:58 +0530114#define MMC_CMD_RES_MAN 62
115
116#define MMC_CMD62_ARG1 0xefac62ec
117#define MMC_CMD62_ARG2 0xcbaea7
118
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200119
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200120#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -0500121#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200122#define SD_CMD_SEND_IF_COND 8
Otavio Salvadorf022d362015-02-17 10:42:43 -0200123#define SD_CMD_SWITCH_UHS18V 11
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200124
125#define SD_CMD_APP_SET_BUS_WIDTH 6
Peng Fan3697e592016-09-01 11:13:38 +0800126#define SD_CMD_APP_SD_STATUS 13
Lei Wene6f99a52011-06-22 17:03:31 +0000127#define SD_CMD_ERASE_WR_BLK_START 32
128#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200129#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -0500130#define SD_CMD_APP_SEND_SCR 51
131
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200132static inline bool mmc_is_tuning_cmd(uint cmdidx)
133{
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200134 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
135 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200136 return true;
137 return false;
138}
139
Andy Fleming272cc702008-10-30 16:41:01 -0500140/* SCR definitions in different words */
141#define SD_HIGHSPEED_BUSY 0x00020000
142#define SD_HIGHSPEED_SUPPORTED 0x00020000
143
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200144#define UHS_SDR12_BUS_SPEED 0
145#define HIGH_SPEED_BUS_SPEED 1
146#define UHS_SDR25_BUS_SPEED 1
147#define UHS_SDR50_BUS_SPEED 2
148#define UHS_SDR104_BUS_SPEED 3
149#define UHS_DDR50_BUS_SPEED 4
150
151#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
152#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
153#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
154#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
155#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
156
Thomas Chouabe2c932011-04-19 03:48:31 +0000157#define OCR_BUSY 0x80000000
158#define OCR_HCS 0x40000000
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200159#define OCR_S18R 0x1000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000160#define OCR_VOLTAGE_MASK 0x007FFF80
161#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500162
Eric Nelson1aa2d072015-12-07 07:50:01 -0700163#define MMC_ERASE_ARG 0x00000000
164#define MMC_SECURE_ERASE_ARG 0x80000000
165#define MMC_TRIM_ARG 0x00000001
166#define MMC_DISCARD_ARG 0x00000003
167#define MMC_SECURE_TRIM1_ARG 0x80000001
168#define MMC_SECURE_TRIM2_ARG 0x80008000
Lei Wene6f99a52011-06-22 17:03:31 +0000169
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000170#define MMC_STATUS_MASK (~0x0206BF7F)
Andrew Gabbasov6b2221b2014-04-03 04:34:32 -0500171#define MMC_STATUS_SWITCH_ERROR (1 << 7)
Thomas Chouabe2c932011-04-19 03:48:31 +0000172#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
173#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000174#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000175
Jan Kloetzked617c422012-02-05 22:29:12 +0000176#define MMC_STATE_PRG (7 << 9)
177
Andy Fleming272cc702008-10-30 16:41:01 -0500178#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
179#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
180#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
181#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
182#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
183#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
184#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
185#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
186#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
187#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
188#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
189#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
190#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
191#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
192#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
193#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
194#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
195
196#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
197#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
198 addressed by index which are
199 1 in value field */
200#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
201 addressed by index, which are
202 1 in value field */
203#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
204
205#define SD_SWITCH_CHECK 0
206#define SD_SWITCH_SWITCH 1
207
208/*
209 * EXT_CSD fields
210 */
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100211#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
212#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600213#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Markus Niebeld7b29122014-11-18 15:11:42 +0100214#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
Oliver Metz1937e5a2013-10-01 20:32:07 +0200215#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100216#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
Lei Wen0560db12011-10-03 20:35:10 +0000217#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Tom Rini33ace362014-02-07 14:15:20 -0500218#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Tomas Melincd3d4882016-11-25 11:01:03 +0200219#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100220#define EXT_CSD_WR_REL_PARAM 166 /* R */
221#define EXT_CSD_WR_REL_SET 167 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600222#define EXT_CSD_RPMB_MULT 168 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000223#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Amar3690d6d2013-04-27 11:42:58 +0530224#define EXT_CSD_BOOT_BUS_WIDTH 177
Lei Wen0560db12011-10-03 20:35:10 +0000225#define EXT_CSD_PART_CONF 179 /* R/W */
226#define EXT_CSD_BUS_WIDTH 183 /* R/W */
Peng Fan44acd492019-07-10 14:43:07 +0800227#define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
Lei Wen0560db12011-10-03 20:35:10 +0000228#define EXT_CSD_HS_TIMING 185 /* R/W */
229#define EXT_CSD_REV 192 /* RO */
230#define EXT_CSD_CARD_TYPE 196 /* RO */
Jean-Jacques Hiblot513e00b2019-07-02 10:53:55 +0200231#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000232#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
Stephen Warrenf866a462013-06-11 15:14:01 -0600233#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000234#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000235#define EXT_CSD_BOOT_MULT 226 /* RO */
Jean-Jacques Hiblot39320c52019-07-02 10:53:54 +0200236#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
Tomas Melincd3d4882016-11-25 11:01:03 +0200237#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500238
239/*
240 * EXT_CSD field definitions
241 */
242
Thomas Chouabe2c932011-04-19 03:48:31 +0000243#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
244#define EXT_CSD_CMD_SET_SECURE (1 << 1)
245#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500246
Thomas Chouabe2c932011-04-19 03:48:31 +0000247#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
248#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900249#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
250#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
251#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
252 | EXT_CSD_CARD_TYPE_DDR_1_2V)
Andy Fleming272cc702008-10-30 16:41:01 -0500253
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200254#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
255 /* SDR mode @1.8V I/O */
256#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
257 /* SDR mode @1.2V I/O */
258#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
259 EXT_CSD_CARD_TYPE_HS200_1_2V)
Peng Fan3dd26262018-08-10 14:07:54 +0800260#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
261#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
262#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
263 EXT_CSD_CARD_TYPE_HS400_1_2V)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200264
Andy Fleming272cc702008-10-30 16:41:01 -0500265#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
266#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
267#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900268#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
269#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200270#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
Peng Fan44acd492019-07-10 14:43:07 +0800271#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200272
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200273#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
274#define EXT_CSD_TIMING_HS 1 /* HS */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200275#define EXT_CSD_TIMING_HS200 2 /* HS200 */
Peng Fan3dd26262018-08-10 14:07:54 +0800276#define EXT_CSD_TIMING_HS400 3 /* HS400 */
Peng Fan44acd492019-07-10 14:43:07 +0800277#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200278
Amar3690d6d2013-04-27 11:42:58 +0530279#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
280#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
281#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
282#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
283
284#define EXT_CSD_BOOT_ACK(x) (x << 6)
285#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
286#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
287
Angelo Dureghellobdb60992017-08-01 14:27:10 +0200288#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
289#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
290#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
291
Tom Rini5a99b9d2014-02-05 10:24:22 -0500292#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
293#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
294#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
Amar3690d6d2013-04-27 11:42:58 +0530295
Markus Niebeld7b29122014-11-18 15:11:42 +0100296#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
297
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100298#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
299#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
300
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100301#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
302
303#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
304#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
305
Andy Fleming1de97f92008-10-30 16:31:39 -0500306#define R1_ILLEGAL_COMMAND (1 << 22)
307#define R1_APP_CMD (1 << 5)
308
Andy Fleming272cc702008-10-30 16:41:01 -0500309#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000310#define MMC_RSP_136 (1 << 1) /* 136 bit response */
311#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
312#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
313#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500314
Thomas Chouabe2c932011-04-19 03:48:31 +0000315#define MMC_RSP_NONE (0)
316#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500317#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
318 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000319#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
320#define MMC_RSP_R3 (MMC_RSP_PRESENT)
321#define MMC_RSP_R4 (MMC_RSP_PRESENT)
322#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
323#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
324#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500325
Lei Wenbc897b12011-05-02 16:26:26 +0000326#define MMCPART_NOAVAILABLE (0xff)
327#define PART_ACCESS_MASK (0x7)
328#define PART_SUPPORT (0x1)
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100329#define ENHNCD_SUPPORT (0x2)
Oliver Metz1937e5a2013-10-01 20:32:07 +0200330#define PART_ENH_ATTRIB (0x1f)
wdenk71f95112003-06-15 22:40:42 +0000331
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200332#define MMC_QUIRK_RETRY_SEND_CID BIT(0)
333#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
334
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200335enum mmc_voltage {
336 MMC_SIGNAL_VOLTAGE_000 = 0,
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200337 MMC_SIGNAL_VOLTAGE_120 = 1,
338 MMC_SIGNAL_VOLTAGE_180 = 2,
339 MMC_SIGNAL_VOLTAGE_330 = 4,
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200340};
341
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200342#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
343 MMC_SIGNAL_VOLTAGE_180 |\
344 MMC_SIGNAL_VOLTAGE_330)
345
Simon Glass8bfa1952013-04-03 08:54:30 +0000346/* Maximum block size for MMC */
347#define MMC_MAX_BLOCK_LEN 512
348
Amar3690d6d2013-04-27 11:42:58 +0530349/* The number of MMC physical partitions. These consist of:
350 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
351 */
352#define MMC_NUM_BOOT_PARTITION 2
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200353#define MMC_PART_RPMB 3 /* RPMB partition number */
Amar3690d6d2013-04-27 11:42:58 +0530354
Simon Glasse7ecf7c2015-06-23 15:38:48 -0600355/* Driver model support */
356
357/**
358 * struct mmc_uclass_priv - Holds information about a device used by the uclass
359 */
360struct mmc_uclass_priv {
361 struct mmc *mmc;
362};
363
364/**
365 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
366 *
367 * Provided that the device is already probed and ready for use, this value
368 * will be available.
369 *
370 * @dev: Device
371 * @return associated mmc struct pointer if available, else NULL
372 */
373struct mmc *mmc_get_mmc_dev(struct udevice *dev);
374
375/* End of driver model support */
376
Andy Fleming1de97f92008-10-30 16:31:39 -0500377struct mmc_cid {
378 unsigned long psn;
379 unsigned short oid;
380 unsigned char mid;
381 unsigned char prv;
382 unsigned char mdt;
383 char pnm[7];
384};
385
Andy Fleming272cc702008-10-30 16:41:01 -0500386struct mmc_cmd {
387 ushort cmdidx;
388 uint resp_type;
389 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530390 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500391};
392
393struct mmc_data {
394 union {
395 char *dest;
396 const char *src; /* src buffers don't get written to */
397 };
398 uint flags;
399 uint blocks;
400 uint blocksize;
401};
402
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200403/* forward decl. */
404struct mmc;
405
Simon Glasse7881d82017-07-29 11:35:31 -0600406#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass8ca51e52016-06-12 23:30:22 -0600407struct dm_mmc_ops {
408 /**
409 * send_cmd() - Send a command to the MMC device
410 *
411 * @dev: Device to receive the command
412 * @cmd: Command to send
413 * @data: Additional data to send/receive
414 * @return 0 if OK, -ve on error
415 */
416 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
417 struct mmc_data *data);
418
419 /**
420 * set_ios() - Set the I/O speed/width for an MMC device
421 *
422 * @dev: Device to update
423 * @return 0 if OK, -ve on error
424 */
425 int (*set_ios)(struct udevice *dev);
426
427 /**
428 * get_cd() - See whether a card is present
429 *
430 * @dev: Device to check
431 * @return 0 if not present, 1 if present, -ve on error
432 */
433 int (*get_cd)(struct udevice *dev);
434
435 /**
436 * get_wp() - See whether a card has write-protect enabled
437 *
438 * @dev: Device to check
439 * @return 0 if write-enabled, 1 if write-protected, -ve on error
440 */
441 int (*get_wp)(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200442
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100443#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200444 /**
445 * execute_tuning() - Start the tuning process
446 *
447 * @dev: Device to start the tuning
448 * @opcode: Command opcode to send
449 * @return 0 if OK, -ve on error
450 */
451 int (*execute_tuning)(struct udevice *dev, uint opcode);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100452#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200453
454 /**
455 * wait_dat0() - wait until dat0 is in the target state
456 * (CLK must be running during the wait)
457 *
458 * @dev: Device to check
459 * @state: target state
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300460 * @timeout_us: timeout in us
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200461 * @return 0 if dat0 is in the target state, -ve on error
462 */
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300463 int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
Peng Fan44acd492019-07-10 14:43:07 +0800464
465#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
466 /* set_enhanced_strobe() - set HS400 enhanced strobe */
467 int (*set_enhanced_strobe)(struct udevice *dev);
468#endif
Yann Gautier3602a562019-09-19 17:56:12 +0200469
470 /**
471 * host_power_cycle - host specific tasks in power cycle sequence
472 * Called between mmc_power_off() and
473 * mmc_power_on()
474 *
475 * @dev: Device to check
476 * @return 0 if not present, 1 if present, -ve on error
477 */
478 int (*host_power_cycle)(struct udevice *dev);
Simon Glass8ca51e52016-06-12 23:30:22 -0600479};
480
481#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
482
483int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
484 struct mmc_data *data);
485int dm_mmc_set_ios(struct udevice *dev);
486int dm_mmc_get_cd(struct udevice *dev);
487int dm_mmc_get_wp(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200488int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300489int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
Yann Gautier3602a562019-09-19 17:56:12 +0200490int dm_mmc_host_power_cycle(struct udevice *dev);
Simon Glass8ca51e52016-06-12 23:30:22 -0600491
492/* Transition functions for compatibility */
493int mmc_set_ios(struct mmc *mmc);
494int mmc_getcd(struct mmc *mmc);
495int mmc_getwp(struct mmc *mmc);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200496int mmc_execute_tuning(struct mmc *mmc, uint opcode);
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300497int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
Peng Fan44acd492019-07-10 14:43:07 +0800498int mmc_set_enhanced_strobe(struct mmc *mmc);
Yann Gautier3602a562019-09-19 17:56:12 +0200499int mmc_host_power_cycle(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600500
501#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200502struct mmc_ops {
503 int (*send_cmd)(struct mmc *mmc,
504 struct mmc_cmd *cmd, struct mmc_data *data);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900505 int (*set_ios)(struct mmc *mmc);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200506 int (*init)(struct mmc *mmc);
507 int (*getcd)(struct mmc *mmc);
508 int (*getwp)(struct mmc *mmc);
Yann Gautier3602a562019-09-19 17:56:12 +0200509 int (*host_power_cycle)(struct mmc *mmc);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200510};
Simon Glass8ca51e52016-06-12 23:30:22 -0600511#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200512
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200513struct mmc_config {
514 const char *name;
Simon Glasse7881d82017-07-29 11:35:31 -0600515#if !CONFIG_IS_ENABLED(DM_MMC)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200516 const struct mmc_ops *ops;
Simon Glass8ca51e52016-06-12 23:30:22 -0600517#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200518 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500519 uint voltages;
Andy Fleming272cc702008-10-30 16:41:01 -0500520 uint f_min;
521 uint f_max;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200522 uint b_max;
523 unsigned char part_type;
524};
525
Peng Fan3697e592016-09-01 11:13:38 +0800526struct sd_ssr {
527 unsigned int au; /* In sectors */
528 unsigned int erase_timeout; /* In milliseconds */
529 unsigned int erase_offset; /* In milliseconds */
530};
531
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200532enum bus_mode {
533 MMC_LEGACY,
534 SD_LEGACY,
535 MMC_HS,
536 SD_HS,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100537 MMC_HS_52,
538 MMC_DDR_52,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200539 UHS_SDR12,
540 UHS_SDR25,
541 UHS_SDR50,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200542 UHS_DDR50,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100543 UHS_SDR104,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200544 MMC_HS_200,
Peng Fan3dd26262018-08-10 14:07:54 +0800545 MMC_HS_400,
Peng Fan44acd492019-07-10 14:43:07 +0800546 MMC_HS_400_ES,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200547 MMC_MODES_END
548};
549
550const char *mmc_mode_name(enum bus_mode mode);
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +0200551void mmc_dump_capabilities(const char *text, uint caps);
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200552
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200553static inline bool mmc_is_mode_ddr(enum bus_mode mode)
554{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100555 if (mode == MMC_DDR_52)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200556 return true;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100557#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
558 else if (mode == UHS_DDR50)
559 return true;
560#endif
Peng Fan3dd26262018-08-10 14:07:54 +0800561#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
562 else if (mode == MMC_HS_400)
563 return true;
564#endif
Peng Fan44acd492019-07-10 14:43:07 +0800565#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
566 else if (mode == MMC_HS_400_ES)
567 return true;
568#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200569 else
570 return false;
571}
572
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200573#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
574 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
575 MMC_CAP(UHS_DDR50))
576
577static inline bool supports_uhs(uint caps)
578{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100579#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200580 return (caps & UHS_CAPS) ? true : false;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100581#else
582 return false;
583#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200584}
585
Simon Glass8ca51e52016-06-12 23:30:22 -0600586/*
587 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
588 * with mmc_get_mmc_dev().
589 *
590 * TODO struct mmc should be in mmc_private but it's hard to fix right now
591 */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200592struct mmc {
Simon Glassc4d660d2017-07-04 13:31:19 -0600593#if !CONFIG_IS_ENABLED(BLK)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200594 struct list_head link;
Simon Glass33fb2112016-05-01 13:52:41 -0600595#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200596 const struct mmc_config *cfg; /* provided configuration */
597 uint version;
598 void *priv;
599 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500600 int high_capacity;
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200601 bool clk_disable; /* true if the clock can be turned off */
Andy Fleming272cc702008-10-30 16:41:01 -0500602 uint bus_width;
603 uint clock;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200604 enum mmc_voltage signal_voltage;
Andy Fleming272cc702008-10-30 16:41:01 -0500605 uint card_caps;
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +0200606 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500607 uint ocr;
Markus Niebelab711882013-12-16 13:40:46 +0100608 uint dsr;
609 uint dsr_imp;
Andy Fleming272cc702008-10-30 16:41:01 -0500610 uint scr[2];
611 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530612 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500613 ushort rca;
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100614 u8 part_support;
615 u8 part_attr;
Diego Santa Cruz9e41a002014-12-23 10:50:33 +0100616 u8 wr_rel_set;
Tom Rini7ca0d3d2017-05-10 15:20:16 -0400617 u8 part_config;
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300618 u8 gen_cmd6_time; /* units: 10 ms */
619 u8 part_switch_time; /* units: 10 ms */
Andy Fleming272cc702008-10-30 16:41:01 -0500620 uint tran_speed;
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200621 uint legacy_speed; /* speed for the legacy mode provided by the card */
Andy Fleming272cc702008-10-30 16:41:01 -0500622 uint read_bl_len;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100623#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Fleming272cc702008-10-30 16:41:01 -0500624 uint write_bl_len;
Diego Santa Cruza4ff9f82014-12-23 10:50:24 +0100625 uint erase_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100626#endif
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100627#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruz037dc0a2014-12-23 10:50:25 +0100628 uint hc_wp_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100629#endif
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100630#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fan3697e592016-09-01 11:13:38 +0800631 struct sd_ssr ssr; /* SD status register */
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100632#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500633 u64 capacity;
Stephen Warrenf866a462013-06-11 15:14:01 -0600634 u64 capacity_user;
635 u64 capacity_boot;
636 u64 capacity_rpmb;
637 u64 capacity_gp[4];
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100638#ifndef CONFIG_SPL_BUILD
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100639 u64 enh_user_start;
640 u64 enh_user_size;
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100641#endif
Simon Glassc4d660d2017-07-04 13:31:19 -0600642#if !CONFIG_IS_ENABLED(BLK)
Simon Glass4101f682016-02-29 15:25:34 -0700643 struct blk_desc block_dev;
Simon Glass33fb2112016-05-01 13:52:41 -0600644#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +0000645 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
646 char init_in_progress; /* 1 if we have done mmc_start_init() */
647 char preinit; /* start init as early as possible */
Andrew Gabbasov786e8f82014-12-01 06:59:09 -0600648 int ddr_mode;
Simon Glassc4d660d2017-07-04 13:31:19 -0600649#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glasscffe5d82016-05-01 13:52:34 -0600650 struct udevice *dev; /* Device for this MMC controller */
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +0200651#if CONFIG_IS_ENABLED(DM_REGULATOR)
652 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
653 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
654#endif
Simon Glasscffe5d82016-05-01 13:52:34 -0600655#endif
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +0200656 u8 *ext_csd;
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200657 u32 cardtype; /* cardtype read from the MMC */
658 enum mmc_voltage current_voltage;
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200659 enum bus_mode selected_mode; /* mode currently used */
660 enum bus_mode best_mode; /* best mode is the supported mode with the
661 * highest bandwidth. It may not always be the
662 * operating mode due to limitations when
663 * accessing the boot partitions
664 */
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200665 u32 quirks;
Andy Fleming272cc702008-10-30 16:41:01 -0500666};
667
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100668struct mmc_hwpart_conf {
669 struct {
670 uint enh_start; /* in 512-byte sectors */
671 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100672 unsigned wr_rel_change : 1;
673 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100674 } user;
675 struct {
676 uint size; /* in 512-byte sectors */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100677 unsigned enhanced : 1;
678 unsigned wr_rel_change : 1;
679 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100680 } gp_part[4];
681};
682
683enum mmc_hwpart_conf_mode {
684 MMC_HWPART_CONF_CHECK,
685 MMC_HWPART_CONF_SET,
686 MMC_HWPART_CONF_COMPLETE,
687};
688
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200689struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
Simon Glassad27dd52016-05-01 13:52:40 -0600690
691/**
692 * mmc_bind() - Set up a new MMC device ready for probing
693 *
694 * A child block device is bound with the IF_TYPE_MMC interface type. This
695 * allows the device to be used with CONFIG_BLK
696 *
697 * @dev: MMC device to set up
698 * @mmc: MMC struct
699 * @cfg: MMC configuration
700 * @return 0 if OK, -ve on error
701 */
702int mmc_bind(struct udevice *dev, struct mmc *mmc,
703 const struct mmc_config *cfg);
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200704void mmc_destroy(struct mmc *mmc);
Simon Glassad27dd52016-05-01 13:52:40 -0600705
706/**
707 * mmc_unbind() - Unbind a MMC device's child block device
708 *
709 * @dev: MMC device
710 * @return 0 if OK, -ve on error
711 */
712int mmc_unbind(struct udevice *dev);
Andy Fleming272cc702008-10-30 16:41:01 -0500713int mmc_initialize(bd_t *bis);
Lokesh Vutla80f02012019-09-09 14:40:36 +0530714int mmc_init_device(int num);
Andy Fleming272cc702008-10-30 16:41:01 -0500715int mmc_init(struct mmc *mmc);
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200716int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100717
Marek Vasutfceea992019-01-29 04:45:51 +0100718#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
719 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
720 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
721int mmc_deinit(struct mmc *mmc);
722#endif
723
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100724/**
725 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
726 *
727 * @dev: MMC device
728 * @cfg: MMC configuration
729 * @return 0 if OK, -ve on error
730 */
731int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
732
Andy Fleming272cc702008-10-30 16:41:01 -0500733int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200734
735/**
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200736 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
737 *
738 * @voltage: The mmc_voltage to convert
739 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
740 */
741int mmc_voltage_to_mv(enum mmc_voltage voltage);
742
743/**
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200744 * mmc_set_clock() - change the bus clock
745 * @mmc: MMC struct
746 * @clock: bus frequency in Hz
747 * @disable: flag indicating if the clock must on or off
748 * @return 0 if OK, -ve on error
749 */
750int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
751
Jaehoon Chung65117182018-01-26 19:25:29 +0900752#define MMC_CLK_ENABLE false
753#define MMC_CLK_DISABLE true
754
Andy Fleming272cc702008-10-30 16:41:01 -0500755struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700756int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500757void print_mmc_devices(char separator);
Kever Yang46683f32016-07-22 17:22:50 +0800758
759/**
760 * get_mmc_num() - get the total MMC device number
761 *
762 * @return 0 if there is no MMC device, else the number of devices
763 */
Lei Wenea6ebe22011-05-02 16:26:25 +0000764int get_mmc_num(void);
Marek Vasutb5b838f2016-12-01 02:06:33 +0100765int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100766int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
767 enum mmc_hwpart_conf_mode mode);
Simon Glass8ca51e52016-06-12 23:30:22 -0600768
Simon Glasse7881d82017-07-29 11:35:31 -0600769#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Reding48972d92012-01-02 01:15:37 +0000770int mmc_getcd(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200771int board_mmc_getcd(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000772int mmc_getwp(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200773int board_mmc_getwp(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600774#endif
775
Markus Niebelab711882013-12-16 13:40:46 +0100776int mmc_set_dsr(struct mmc *mmc, u16 val);
Amar3690d6d2013-04-27 11:42:58 +0530777/* Function to change the size of boot partition and rpmb partitions */
778int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
779 unsigned long rpmbsize);
Tom Rini792970b2014-02-05 10:24:21 -0500780/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
781int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
Tom Rini5a99b9d2014-02-05 10:24:22 -0500782/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
783int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
Tom Rini33ace362014-02-07 14:15:20 -0500784/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
785int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200786/* Functions to read / write the RPMB partition */
787int mmc_rpmb_set_key(struct mmc *mmc, void *key);
788int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
789int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
790 unsigned short cnt, unsigned char *key);
791int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
792 unsigned short cnt, unsigned char *key);
Jens Wiklander4853ad32018-09-25 16:40:08 +0200793
794/**
795 * mmc_rpmb_route_frames() - route RPMB data frames
796 * @mmc Pointer to a MMC device struct
797 * @req Request data frames
798 * @reqlen Length of data frames in bytes
799 * @rsp Supplied buffer for response data frames
800 * @rsplen Length of supplied buffer for response data frames
801 *
802 * The RPMB data frames are routed to/from some external entity, for
803 * example a Trusted Exectuion Environment in an arm TrustZone protected
804 * secure world. It's expected that it's the external entity who is in
805 * control of the RPMB key.
806 *
807 * Returns 0 on success, < 0 on error.
808 */
809int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
810 void *rsp, unsigned long rsplen);
811
Tomas Melincd3d4882016-11-25 11:01:03 +0200812#ifdef CONFIG_CMD_BKOPS_ENABLE
813int mmc_set_bkops_enable(struct mmc *mmc);
814#endif
815
Che-Liang Chioue9550442012-11-28 15:21:13 +0000816/**
817 * Start device initialization and return immediately; it does not block on
Jon Nettleton6c09eba2018-06-11 15:26:19 +0300818 * polling OCR (operation condition register) status. Useful for checking
819 * the presence of SD/eMMC when no card detect logic is available.
820 *
821 * @param mmc Pointer to a MMC device struct
822 * @return 0 on success, <0 on error.
823 */
824int mmc_get_op_cond(struct mmc *mmc);
825
826/**
827 * Start device initialization and return immediately; it does not block on
Che-Liang Chioue9550442012-11-28 15:21:13 +0000828 * polling OCR (operation condition register) status. Then you should call
829 * mmc_init, which would block on polling OCR status and complete the device
830 * initializatin.
831 *
832 * @param mmc Pointer to a MMC device struct
Baruch Siach31d95002018-06-11 15:26:18 +0300833 * @return 0 on success, <0 on error.
Che-Liang Chioue9550442012-11-28 15:21:13 +0000834 */
835int mmc_start_init(struct mmc *mmc);
836
837/**
838 * Set preinit flag of mmc device.
839 *
840 * This will cause the device to be pre-inited during mmc_initialize(),
841 * which may save boot time if the device is not accessed until later.
842 * Some eMMC devices take 200-300ms to init, but unfortunately they
843 * must be sent a series of commands to even get them to start preparing
844 * for operation.
845 *
846 * @param mmc Pointer to a MMC device struct
847 * @param preinit preinit flag value
848 */
849void mmc_set_preinit(struct mmc *mmc, int preinit);
850
Paul Burton8687d5c2013-09-04 16:12:26 +0100851#ifdef CONFIG_MMC_SPI
Tom Rini0b2da7e2014-03-28 16:55:29 -0400852#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
Paul Burton8687d5c2013-09-04 16:12:26 +0100853#else
854#define mmc_host_is_spi(mmc) 0
855#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200856
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +0100857void board_mmc_power_init(void);
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200858int board_mmc_init(bd_t *bis);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200859int cpu_mmc_init(bd_t *bis);
Jeroen Hofsteeaeb80552014-10-08 22:58:05 +0200860int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
Rajesh Bhagat43d17c42019-01-12 07:30:51 +0000861# ifdef CONFIG_SYS_MMC_ENV_PART
862extern uint mmc_get_env_part(struct mmc *mmc);
863# endif
Clemens Gruberaa844fe2016-01-26 16:20:38 +0100864int mmc_get_env_dev(void);
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200865
Jean-Jacques Hiblot513e00b2019-07-02 10:53:55 +0200866/* Minimum partition switch timeout in units of 10-milliseconds */
867#define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
868
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200869/* Set block count limit because of 16 bit register limit on some hardware*/
870#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
871#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
872#endif
873
Simon Glasscb5ec332016-05-01 13:52:27 -0600874/**
875 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
876 *
877 * @mmc: MMC device
878 * @return block device if found, else NULL
879 */
880struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
881
wdenk71f95112003-06-15 22:40:42 +0000882#endif /* _MMC_H_ */