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wdenkc6097192002-11-03 00:24:07 +00001/*
Marek Vasut20f7b1b2011-10-31 14:12:39 +01002 * armboot - Startup Code for XScale CPU-core
wdenkc6097192002-11-03 00:24:07 +00003 *
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
wdenka8c7c702003-12-06 19:49:23 +00007 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
Marek Vasut20f7b1b2011-10-31 14:12:39 +01008 * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
wdenk1cb8e982003-03-06 21:55:29 +000011 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
Wolfgang Denk951a9542006-03-06 23:18:48 +010012 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
Marek Vasut20f7b1b2011-10-31 14:12:39 +010013 * Copyright (C) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
wdenkc6097192002-11-03 00:24:07 +000018 *
19 * See file CREDITS for list of people who contributed to this
20 * project.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk384ae022002-11-05 00:17:55 +000029 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkc6097192002-11-03 00:24:07 +000030 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 * MA 02111-1307 USA
36 */
37
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020038#include <asm-offsets.h>
wdenkc6097192002-11-03 00:24:07 +000039#include <config.h>
40#include <version.h>
Marek Vasut7f4cfcf2011-11-05 19:26:47 +010041
Marek Vasutabc20ab2011-11-26 07:20:07 +010042#ifdef CONFIG_CPU_PXA25X
Marek Vasut7f4cfcf2011-11-05 19:26:47 +010043#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
44#error "Init SP address must be set to 0xfffff800 for PXA250"
45#endif
46#endif
47
wdenkc6097192002-11-03 00:24:07 +000048.globl _start
wdenk384ae022002-11-05 00:17:55 +000049_start: b reset
Aneesh V401bb302011-07-13 05:11:07 +000050#ifdef CONFIG_SPL_BUILD
Marek Vasut5ab877b2010-07-06 02:48:35 +020051 ldr pc, _hang
52 ldr pc, _hang
53 ldr pc, _hang
54 ldr pc, _hang
55 ldr pc, _hang
56 ldr pc, _hang
57 ldr pc, _hang
58
59_hang:
60 .word do_hang
61 .word 0x12345678
62 .word 0x12345678
63 .word 0x12345678
64 .word 0x12345678
65 .word 0x12345678
66 .word 0x12345678
67 .word 0x12345678 /* now 16*4=64 */
68#else
wdenkc6097192002-11-03 00:24:07 +000069 ldr pc, _undefined_instruction
70 ldr pc, _software_interrupt
71 ldr pc, _prefetch_abort
72 ldr pc, _data_abort
73 ldr pc, _not_used
74 ldr pc, _irq
75 ldr pc, _fiq
76
wdenk384ae022002-11-05 00:17:55 +000077_undefined_instruction: .word undefined_instruction
wdenkc6097192002-11-03 00:24:07 +000078_software_interrupt: .word software_interrupt
79_prefetch_abort: .word prefetch_abort
80_data_abort: .word data_abort
81_not_used: .word not_used
82_irq: .word irq
83_fiq: .word fiq
Marek Vasut20f7b1b2011-10-31 14:12:39 +010084_pad: .word 0x12345678 /* now 16*4=64 */
Aneesh V401bb302011-07-13 05:11:07 +000085#endif /* CONFIG_SPL_BUILD */
Marek Vasut20f7b1b2011-10-31 14:12:39 +010086.global _end_vect
87_end_vect:
wdenkc6097192002-11-03 00:24:07 +000088
89 .balignl 16,0xdeadbeef
wdenkc6097192002-11-03 00:24:07 +000090/*
Marek Vasut20f7b1b2011-10-31 14:12:39 +010091 *************************************************************************
92 *
wdenkc6097192002-11-03 00:24:07 +000093 * Startup Code (reset vector)
94 *
Marek Vasut20f7b1b2011-10-31 14:12:39 +010095 * do important init only if we don't start from memory!
96 * setup Memory and board specific bits prior to relocation.
97 * relocate armboot to ram
98 * setup stack
99 *
100 *************************************************************************
wdenkc6097192002-11-03 00:24:07 +0000101 */
102
Heiko Schocher5347f682010-09-17 13:10:46 +0200103.globl _TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000104_TEXT_BASE:
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100105#ifdef CONFIG_SPL_BUILD
106 .word CONFIG_SPL_TEXT_BASE
107#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200108 .word CONFIG_SYS_TEXT_BASE
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100109#endif
wdenkc6097192002-11-03 00:24:07 +0000110
wdenkc6097192002-11-03 00:24:07 +0000111/*
wdenkf6e20fc2004-02-08 19:38:38 +0000112 * These are defined in the board-specific linker script.
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100113 * Subtracting _start from them lets the linker put their
114 * relative position in the executable instead of leaving
115 * them null.
wdenk47cd00f2003-03-06 13:39:27 +0000116 */
Marek Vasut6e96cf92010-10-20 19:36:39 +0200117.globl _bss_start_ofs
118_bss_start_ofs:
119 .word __bss_start - _start
wdenk47cd00f2003-03-06 13:39:27 +0000120
Marek Vasut6e96cf92010-10-20 19:36:39 +0200121.globl _bss_end_ofs
122_bss_end_ofs:
Simon Glass3929fb02013-03-14 06:54:53 +0000123 .word __bss_end - _start
wdenk47cd00f2003-03-06 13:39:27 +0000124
Po-Yu Chuangf326cbb2011-03-01 23:02:04 +0000125.globl _end_ofs
126_end_ofs:
127 .word _end - _start
128
wdenkc6097192002-11-03 00:24:07 +0000129#ifdef CONFIG_USE_IRQ
130/* IRQ stack memory (calculated at run-time) */
131.globl IRQ_STACK_START
132IRQ_STACK_START:
133 .word 0x0badc0de
134
135/* IRQ stack memory (calculated at run-time) */
136.globl FIQ_STACK_START
137FIQ_STACK_START:
138 .word 0x0badc0de
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100139#endif
wdenkc6097192002-11-03 00:24:07 +0000140
Heiko Schocher5347f682010-09-17 13:10:46 +0200141/* IRQ stack memory (calculated at run-time) + 8 bytes */
142.globl IRQ_STACK_START_IN
143IRQ_STACK_START_IN:
144 .word 0x0badc0de
145
Heiko Schocher5347f682010-09-17 13:10:46 +0200146/*
147 * the actual reset code
148 */
149
150reset:
151 /*
152 * set the cpu to SVC32 mode
153 */
154 mrs r0,cpsr
155 bic r0,r0,#0x1f
156 orr r0,r0,#0xd3
157 msr cpsr,r0
158
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100159#ifndef CONFIG_SKIP_LOWLEVEL_INIT
160 bl cpu_init_crit
161#endif
Heiko Schocher5347f682010-09-17 13:10:46 +0200162
Marek Vasutabc20ab2011-11-26 07:20:07 +0100163#ifdef CONFIG_CPU_PXA25X
Marek Vasut7f4cfcf2011-11-05 19:26:47 +0100164 bl lock_cache_for_stack
165#endif
166
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +0000167 bl _main
Heiko Schocher5347f682010-09-17 13:10:46 +0200168
169/*------------------------------------------------------------------------------*/
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100170#ifndef CONFIG_SPL_BUILD
Heiko Schocher5347f682010-09-17 13:10:46 +0200171/*
172 * void relocate_code (addr_sp, gd, addr_moni)
173 *
174 * This "function" does not return, instead it continues in RAM
175 * after relocating the monitor code.
176 *
177 */
178 .globl relocate_code
179relocate_code:
180 mov r4, r0 /* save addr_sp */
181 mov r5, r1 /* save addr of gd */
182 mov r6, r2 /* save addr of destination */
Heiko Schocher5347f682010-09-17 13:10:46 +0200183
Marek Vasut7f4cfcf2011-11-05 19:26:47 +0100184/* Disable the Dcache RAM lock for stack now */
Marek Vasutabc20ab2011-11-26 07:20:07 +0100185#ifdef CONFIG_CPU_PXA25X
Łukasz Dałekdf3ad6c2013-01-12 11:39:27 +0000186 mov r12, lr
Marek Vasut7f4cfcf2011-11-05 19:26:47 +0100187 bl cpu_init_crit
Łukasz Dałekdf3ad6c2013-01-12 11:39:27 +0000188 mov lr, r12
Marek Vasut7f4cfcf2011-11-05 19:26:47 +0100189#endif
190
Heiko Schocher5347f682010-09-17 13:10:46 +0200191 adr r0, _start
Andreas Bießmanna1a47d32010-12-01 00:58:34 +0100192 cmp r0, r6
Zhong Hongbo76abfa52012-09-01 20:49:52 +0000193 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +0000194 beq relocate_done /* skip relocation */
Andreas Bießmanna78fb682010-12-01 00:58:33 +0100195 mov r1, r6 /* r1 <- scratch for copy_loop */
Marek Vasut6e96cf92010-10-20 19:36:39 +0200196 ldr r3, _bss_start_ofs
197 add r2, r0, r3 /* r2 <- source end address */
Heiko Schocher5347f682010-09-17 13:10:46 +0200198
Heiko Schocher5347f682010-09-17 13:10:46 +0200199copy_loop:
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100200 ldmia r0!, {r9-r10} /* copy from source address [r0] */
201 stmia r1!, {r9-r10} /* copy to target address [r1] */
Albert Aribaudda90d4c2010-10-05 16:06:39 +0200202 cmp r0, r2 /* until source end address [r2] */
203 blo copy_loop
Heiko Schocher5347f682010-09-17 13:10:46 +0200204
Aneesh V401bb302011-07-13 05:11:07 +0000205#ifndef CONFIG_SPL_BUILD
Marek Vasut6e96cf92010-10-20 19:36:39 +0200206 /*
207 * fix .rel.dyn relocations
208 */
209 ldr r0, _TEXT_BASE /* r0 <- Text base */
Andreas Bießmanna78fb682010-12-01 00:58:33 +0100210 sub r9, r6, r0 /* r9 <- relocation offset */
Marek Vasut6e96cf92010-10-20 19:36:39 +0200211 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
212 add r10, r10, r0 /* r10 <- sym table in FLASH */
213 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
214 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
215 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
216 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
Heiko Schocher5347f682010-09-17 13:10:46 +0200217fixloop:
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100218 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
219 add r0, r0, r9 /* r0 <- location to fix up in RAM */
Marek Vasut6e96cf92010-10-20 19:36:39 +0200220 ldr r1, [r2, #4]
Andreas Bießmann1f52d892010-12-01 00:58:35 +0100221 and r7, r1, #0xff
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100222 cmp r7, #23 /* relative fixup? */
Marek Vasut6e96cf92010-10-20 19:36:39 +0200223 beq fixrel
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100224 cmp r7, #2 /* absolute fixup? */
Marek Vasut6e96cf92010-10-20 19:36:39 +0200225 beq fixabs
226 /* ignore unknown type of fixup */
227 b fixnext
228fixabs:
229 /* absolute fix: set location to (offset) symbol value */
230 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
231 add r1, r10, r1 /* r1 <- address of symbol in table */
232 ldr r1, [r1, #4] /* r1 <- symbol value */
Wolfgang Denk36009452010-12-09 11:26:24 +0100233 add r1, r1, r9 /* r1 <- relocated sym addr */
Marek Vasut6e96cf92010-10-20 19:36:39 +0200234 b fixnext
235fixrel:
236 /* relative fix: increase location by offset */
237 ldr r1, [r0]
238 add r1, r1, r9
239fixnext:
240 str r1, [r0]
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100241 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
Heiko Schocher5347f682010-09-17 13:10:46 +0200242 cmp r2, r3
Marek Vasut6e96cf92010-10-20 19:36:39 +0200243 blo fixloop
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100244#endif
Heiko Schocher5347f682010-09-17 13:10:46 +0200245
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +0000246relocate_done:
Heiko Schocher5347f682010-09-17 13:10:46 +0200247
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +0000248 bx lr
Heiko Schocher5347f682010-09-17 13:10:46 +0200249
Marek Vasut6e96cf92010-10-20 19:36:39 +0200250_rel_dyn_start_ofs:
251 .word __rel_dyn_start - _start
252_rel_dyn_end_ofs:
253 .word __rel_dyn_end - _start
254_dynsym_start_ofs:
255 .word __dynsym_start - _start
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +0000256
Marek Vasut2cad92f2010-09-28 15:44:10 +0200257#endif
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +0000258
259 .globl c_runtime_cpu_setup
260c_runtime_cpu_setup:
261
262 bx lr
263
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100264/*
265 *************************************************************************
266 *
267 * CPU_init_critical registers
268 *
269 * setup important registers
270 * setup memory timing
271 *
272 *************************************************************************
273 */
Marek Vasutabc20ab2011-11-26 07:20:07 +0100274#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100275cpu_init_crit:
276 /*
277 * flush v4 I/D caches
278 */
279 mov r0, #0
280 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
281 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
Marek Vasut2cad92f2010-09-28 15:44:10 +0200282
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100283 /*
284 * disable MMU stuff and caches
285 */
286 mrc p15, 0, r0, c1, c0, 0
287 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
288 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
289 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
290 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
291 mcr p15, 0, r0, c1, c0, 0
wdenkc6097192002-11-03 00:24:07 +0000292
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100293 mov pc, lr /* back to my caller */
Marek Vasutabc20ab2011-11-26 07:20:07 +0100294#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
wdenkc6097192002-11-03 00:24:07 +0000295
Aneesh V401bb302011-07-13 05:11:07 +0000296#ifndef CONFIG_SPL_BUILD
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100297/*
298 *************************************************************************
299 *
300 * Interrupt handling
301 *
302 *************************************************************************
303 */
304@
305@ IRQ stack frame.
306@
wdenkc6097192002-11-03 00:24:07 +0000307#define S_FRAME_SIZE 72
308
309#define S_OLD_R0 68
310#define S_PSR 64
311#define S_PC 60
312#define S_LR 56
313#define S_SP 52
314
315#define S_IP 48
316#define S_FP 44
317#define S_R10 40
318#define S_R9 36
319#define S_R8 32
320#define S_R7 28
321#define S_R6 24
322#define S_R5 20
323#define S_R4 16
324#define S_R3 12
325#define S_R2 8
326#define S_R1 4
327#define S_R0 0
328
329#define MODE_SVC 0x13
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100330#define I_BIT 0x80
wdenkc6097192002-11-03 00:24:07 +0000331
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100332/*
333 * use bad_save_user_regs for abort/prefetch/undef/swi ...
334 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
335 */
wdenkc6097192002-11-03 00:24:07 +0000336
337 .macro bad_save_user_regs
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100338 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
339 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
wdenkc6097192002-11-03 00:24:07 +0000340
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100341 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
342 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
343 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
wdenkc6097192002-11-03 00:24:07 +0000344
345 add r5, sp, #S_SP
346 mov r1, lr
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100347 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
348 mov r0, sp @ save current stack into r0 (param register)
wdenkc6097192002-11-03 00:24:07 +0000349 .endm
350
wdenkc6097192002-11-03 00:24:07 +0000351 .macro irq_save_user_regs
352 sub sp, sp, #S_FRAME_SIZE
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100353 stmia sp, {r0 - r12} @ Calling r0-r12
354 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
355 stmdb r8, {sp, lr}^ @ Calling SP, LR
356 str lr, [r8, #0] @ Save calling PC
wdenk384ae022002-11-05 00:17:55 +0000357 mrs r6, spsr
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100358 str r6, [r8, #4] @ Save CPSR
359 str r0, [r8, #8] @ Save OLD_R0
wdenkc6097192002-11-03 00:24:07 +0000360 mov r0, sp
361 .endm
362
363 .macro irq_restore_user_regs
364 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
365 mov r0, r0
366 ldr lr, [sp, #S_PC] @ Get PC
367 add sp, sp, #S_FRAME_SIZE
368 subs pc, lr, #4 @ return & move spsr_svc into cpsr
369 .endm
370
371 .macro get_bad_stack
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100372 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
wdenkc6097192002-11-03 00:24:07 +0000373
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100374 str lr, [r13] @ save caller lr in position 0 of saved stack
375 mrs lr, spsr @ get the spsr
376 str lr, [r13, #4] @ save spsr in position 1 of saved stack
wdenkc6097192002-11-03 00:24:07 +0000377
378 mov r13, #MODE_SVC @ prepare SVC-Mode
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100379 @ msr spsr_c, r13
380 msr spsr, r13 @ switch modes, make sure moves will execute
381 mov lr, pc @ capture return pc
382 movs pc, lr @ jump to next instruction & switch modes.
383 .endm
384
385 .macro get_bad_stack_swi
386 sub r13, r13, #4 @ space on current stack for scratch reg.
387 str r0, [r13] @ save R0's value.
388 ldr r0, IRQ_STACK_START_IN @ get data regions start
389 str lr, [r0] @ save caller lr in position 0 of saved stack
390 mrs r0, spsr @ get the spsr
391 str lr, [r0, #4] @ save spsr in position 1 of saved stack
392 ldr r0, [r13] @ restore r0
393 add r13, r13, #4 @ pop stack entry
wdenkc6097192002-11-03 00:24:07 +0000394 .endm
395
396 .macro get_irq_stack @ setup IRQ stack
397 ldr sp, IRQ_STACK_START
398 .endm
399
400 .macro get_fiq_stack @ setup FIQ stack
401 ldr sp, FIQ_STACK_START
402 .endm
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100403#endif /* CONFIG_SPL_BUILD */
wdenkc6097192002-11-03 00:24:07 +0000404
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100405/*
406 * exception handlers
407 */
Aneesh V401bb302011-07-13 05:11:07 +0000408#ifdef CONFIG_SPL_BUILD
Marek Vasut5ab877b2010-07-06 02:48:35 +0200409 .align 5
410do_hang:
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100411 ldr sp, _TEXT_BASE /* use 32 words about stack */
Marek Vasut5ab877b2010-07-06 02:48:35 +0200412 bl hang /* hang and never return */
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100413#else /* !CONFIG_SPL_BUILD */
wdenk384ae022002-11-05 00:17:55 +0000414 .align 5
wdenkc6097192002-11-03 00:24:07 +0000415undefined_instruction:
416 get_bad_stack
417 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000418 bl do_undefined_instruction
wdenkc6097192002-11-03 00:24:07 +0000419
420 .align 5
421software_interrupt:
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100422 get_bad_stack_swi
wdenkc6097192002-11-03 00:24:07 +0000423 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000424 bl do_software_interrupt
wdenkc6097192002-11-03 00:24:07 +0000425
426 .align 5
427prefetch_abort:
428 get_bad_stack
429 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000430 bl do_prefetch_abort
wdenkc6097192002-11-03 00:24:07 +0000431
432 .align 5
433data_abort:
434 get_bad_stack
435 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000436 bl do_data_abort
wdenkc6097192002-11-03 00:24:07 +0000437
438 .align 5
439not_used:
440 get_bad_stack
441 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000442 bl do_not_used
wdenkc6097192002-11-03 00:24:07 +0000443
444#ifdef CONFIG_USE_IRQ
445
446 .align 5
447irq:
448 get_irq_stack
449 irq_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000450 bl do_irq
wdenkc6097192002-11-03 00:24:07 +0000451 irq_restore_user_regs
452
453 .align 5
454fiq:
455 get_fiq_stack
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100456 /* someone ought to write a more effiction fiq_save_user_regs */
457 irq_save_user_regs
458 bl do_fiq
wdenkc6097192002-11-03 00:24:07 +0000459 irq_restore_user_regs
460
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100461#else
wdenkc6097192002-11-03 00:24:07 +0000462
463 .align 5
464irq:
465 get_bad_stack
466 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000467 bl do_irq
wdenkc6097192002-11-03 00:24:07 +0000468
469 .align 5
470fiq:
471 get_bad_stack
472 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000473 bl do_fiq
wdenkc6097192002-11-03 00:24:07 +0000474
Marek Vasut20f7b1b2011-10-31 14:12:39 +0100475#endif
476 .align 5
Aneesh V401bb302011-07-13 05:11:07 +0000477#endif /* CONFIG_SPL_BUILD */
Marek Vasut7f4cfcf2011-11-05 19:26:47 +0100478
479
480/*
481 * Enable MMU to use DCache as DRAM.
482 *
483 * This is useful on PXA25x and PXA26x in early bootstages, where there is no
484 * other possible memory available to hold stack.
485 */
Marek Vasutabc20ab2011-11-26 07:20:07 +0100486#ifdef CONFIG_CPU_PXA25X
Marek Vasut7f4cfcf2011-11-05 19:26:47 +0100487.macro CPWAIT reg
488 mrc p15, 0, \reg, c2, c0, 0
489 mov \reg, \reg
490 sub pc, pc, #4
491.endm
492lock_cache_for_stack:
493 /* Domain access -- enable for all CPs */
494 ldr r0, =0x0000ffff
495 mcr p15, 0, r0, c3, c0, 0
496
497 /* Point TTBR to MMU table */
498 ldr r0, =mmutable
499 mcr p15, 0, r0, c2, c0, 0
500
501 /* Kick in MMU, ICache, DCache, BTB */
502 mrc p15, 0, r0, c1, c0, 0
503 bic r0, #0x1b00
504 bic r0, #0x0087
505 orr r0, #0x1800
506 orr r0, #0x0005
507 mcr p15, 0, r0, c1, c0, 0
508 CPWAIT r0
509
510 /* Unlock Icache, Dcache */
511 mcr p15, 0, r0, c9, c1, 1
512 mcr p15, 0, r0, c9, c2, 1
513
514 /* Flush Icache, Dcache, BTB */
515 mcr p15, 0, r0, c7, c7, 0
516
517 /* Unlock I-TLB, D-TLB */
518 mcr p15, 0, r0, c10, c4, 1
519 mcr p15, 0, r0, c10, c8, 1
520
521 /* Flush TLB */
522 mcr p15, 0, r0, c8, c7, 0
523
524 /* Allocate 4096 bytes of Dcache as RAM */
525
526 /* Drain pending loads and stores */
527 mcr p15, 0, r0, c7, c10, 4
528
529 mov r4, #0x00
530 mov r5, #0x00
531 mov r2, #0x01
532 mcr p15, 0, r0, c9, c2, 0
533 CPWAIT r0
534
535 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
536 mov r0, #128
537 ldr r1, =0xfffff000
538
539alloc:
540 mcr p15, 0, r1, c7, c2, 5
541 /* Drain pending loads and stores */
542 mcr p15, 0, r0, c7, c10, 4
543 strd r4, [r1], #8
544 strd r4, [r1], #8
545 strd r4, [r1], #8
546 strd r4, [r1], #8
547 subs r0, #0x01
548 bne alloc
549 /* Drain pending loads and stores */
550 mcr p15, 0, r0, c7, c10, 4
551 mov r2, #0x00
552 mcr p15, 0, r2, c9, c2, 0
553 CPWAIT r0
554
555 mov pc, lr
556
557.section .mmutable, "a"
558mmutable:
559 .align 14
560 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
561 .set __base, 0
562 .rept 0xfff
563 .word (__base << 20) | 0xc12
564 .set __base, __base + 1
565 .endr
566
567 /* 0xfff00000 : 1:1, cached mapping */
568 .word (0xfff << 20) | 0x1c1e
Marek Vasutabc20ab2011-11-26 07:20:07 +0100569#endif /* CONFIG_CPU_PXA25X */