wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * armboot - Startup Code for XScale |
| 3 | * |
| 4 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> |
| 5 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> |
| 6 | * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 7 | * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 8 | * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 9 | * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> |
| 10 | * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 28 | * MA 02111-1307 USA |
| 29 | */ |
| 30 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 31 | #include <config.h> |
| 32 | #include <version.h> |
Markus Klotzbücher | e8cd008 | 2006-02-28 23:11:07 +0100 | [diff] [blame] | 33 | #include <asm/arch/pxa-regs.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 34 | |
| 35 | .globl _start |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 36 | _start: b reset |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 37 | #ifdef CONFIG_PRELOADER |
| 38 | ldr pc, _hang |
| 39 | ldr pc, _hang |
| 40 | ldr pc, _hang |
| 41 | ldr pc, _hang |
| 42 | ldr pc, _hang |
| 43 | ldr pc, _hang |
| 44 | ldr pc, _hang |
| 45 | |
| 46 | _hang: |
| 47 | .word do_hang |
| 48 | .word 0x12345678 |
| 49 | .word 0x12345678 |
| 50 | .word 0x12345678 |
| 51 | .word 0x12345678 |
| 52 | .word 0x12345678 |
| 53 | .word 0x12345678 |
| 54 | .word 0x12345678 /* now 16*4=64 */ |
| 55 | #else |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 56 | ldr pc, _undefined_instruction |
| 57 | ldr pc, _software_interrupt |
| 58 | ldr pc, _prefetch_abort |
| 59 | ldr pc, _data_abort |
| 60 | ldr pc, _not_used |
| 61 | ldr pc, _irq |
| 62 | ldr pc, _fiq |
| 63 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 64 | _undefined_instruction: .word undefined_instruction |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 65 | _software_interrupt: .word software_interrupt |
| 66 | _prefetch_abort: .word prefetch_abort |
| 67 | _data_abort: .word data_abort |
| 68 | _not_used: .word not_used |
| 69 | _irq: .word irq |
| 70 | _fiq: .word fiq |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 71 | #endif /* CONFIG_PRELOADER */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 72 | |
| 73 | .balignl 16,0xdeadbeef |
| 74 | |
| 75 | |
| 76 | /* |
| 77 | * Startup Code (reset vector) |
| 78 | * |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 79 | * do important init only if we don't start from RAM! |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 80 | * - relocate armboot to RAM |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 81 | * - setup stack |
| 82 | * - jump to second stage |
| 83 | */ |
| 84 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 85 | _TEXT_BASE: |
| 86 | .word TEXT_BASE |
| 87 | |
| 88 | .globl _armboot_start |
| 89 | _armboot_start: |
| 90 | .word _start |
| 91 | |
| 92 | /* |
wdenk | f6e20fc | 2004-02-08 19:38:38 +0000 | [diff] [blame] | 93 | * These are defined in the board-specific linker script. |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 94 | */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 95 | .globl _bss_start |
| 96 | _bss_start: |
wdenk | f6e20fc | 2004-02-08 19:38:38 +0000 | [diff] [blame] | 97 | .word __bss_start |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 98 | |
| 99 | .globl _bss_end |
| 100 | _bss_end: |
wdenk | f6e20fc | 2004-02-08 19:38:38 +0000 | [diff] [blame] | 101 | .word _end |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 102 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 103 | #ifdef CONFIG_USE_IRQ |
| 104 | /* IRQ stack memory (calculated at run-time) */ |
| 105 | .globl IRQ_STACK_START |
| 106 | IRQ_STACK_START: |
| 107 | .word 0x0badc0de |
| 108 | |
| 109 | /* IRQ stack memory (calculated at run-time) */ |
| 110 | .globl FIQ_STACK_START |
| 111 | FIQ_STACK_START: |
| 112 | .word 0x0badc0de |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 113 | #endif /* CONFIG_USE_IRQ */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 114 | |
| 115 | |
| 116 | /****************************************************************************/ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 117 | /* */ |
| 118 | /* the actual reset code */ |
| 119 | /* */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 120 | /****************************************************************************/ |
| 121 | |
| 122 | reset: |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 123 | mrs r0,cpsr /* set the CPU to SVC32 mode */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 124 | bic r0,r0,#0x1f /* (superviser mode, M=10011) */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 125 | orr r0,r0,#0x13 |
| 126 | msr cpsr,r0 |
| 127 | |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 128 | /* |
| 129 | * we do sys-critical inits only at reboot, |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 130 | * not when booting from RAM! |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 131 | */ |
wdenk | 8aa1a2d | 2005-04-04 12:44:11 +0000 | [diff] [blame] | 132 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 133 | bl cpu_init_crit /* we do sys-critical inits */ |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 134 | #endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 135 | |
wdenk | 8aa1a2d | 2005-04-04 12:44:11 +0000 | [diff] [blame] | 136 | #ifndef CONFIG_SKIP_RELOCATE_UBOOT |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 137 | relocate: /* relocate U-Boot to RAM */ |
| 138 | adr r0, _start /* r0 <- current position of code */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 139 | ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 140 | #ifndef CONFIG_PRELOADER |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 141 | cmp r0, r1 /* don't reloc during debug */ |
| 142 | beq stack_setup |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 143 | #endif |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 144 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 145 | ldr r2, _armboot_start |
wdenk | f6e20fc | 2004-02-08 19:38:38 +0000 | [diff] [blame] | 146 | ldr r3, _bss_start |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 147 | sub r2, r3, r2 /* r2 <- size of armboot */ |
| 148 | add r2, r0, r2 /* r2 <- source end address */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 149 | |
| 150 | copy_loop: |
| 151 | ldmia r0!, {r3-r10} /* copy from source address [r0] */ |
| 152 | stmia r1!, {r3-r10} /* copy to target address [r1] */ |
Marcel Ziswiler | dbab069 | 2008-07-09 08:17:06 +0200 | [diff] [blame] | 153 | cmp r0, r2 /* until source end address [r2] */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 154 | ble copy_loop |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 155 | #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 156 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 157 | /* Set up the stack */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 158 | stack_setup: |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 159 | ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 160 | #ifdef CONFIG_PRELOADER |
| 161 | sub sp, r0, #128 /* leave 32 words for abort-stack */ |
| 162 | #else |
| 163 | sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ |
| 164 | sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 165 | #ifdef CONFIG_USE_IRQ |
| 166 | sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 167 | #endif /* CONFIG_USE_IRQ */ |
Vitaly Kuzmichev | 1a27f7d | 2010-06-15 22:18:11 +0400 | [diff] [blame] | 168 | sub sp, r0, #12 /* leave 3 words for abort-stack */ |
| 169 | bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 170 | #endif |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 171 | |
| 172 | clear_bss: |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 173 | ldr r0, _bss_start /* find start of bss segment */ |
| 174 | ldr r1, _bss_end /* stop here */ |
| 175 | mov r2, #0x00000000 /* clear */ |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 176 | |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 177 | #ifndef CONFIG_PRELOADER |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 178 | clbss_l:str r2, [r0] /* clear loop... */ |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 179 | add r0, r0, #4 |
| 180 | cmp r0, r1 |
wdenk | a119190 | 2005-01-09 17:12:27 +0000 | [diff] [blame] | 181 | ble clbss_l |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 182 | #endif |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 183 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 184 | ldr pc, _start_armboot |
| 185 | |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 186 | #ifdef CONFIG_ONENAND_IPL |
| 187 | _start_armboot: .word start_oneboot |
| 188 | #else |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 189 | _start_armboot: .word start_armboot |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 190 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 191 | |
| 192 | /****************************************************************************/ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 193 | /* */ |
| 194 | /* CPU_init_critical registers */ |
| 195 | /* */ |
| 196 | /* - setup important registers */ |
| 197 | /* - setup memory timing */ |
| 198 | /* */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 199 | /****************************************************************************/ |
Markus Klotzbücher | 43638c6 | 2006-03-06 15:04:25 +0100 | [diff] [blame] | 200 | /* mk@tbd: Fix this! */ |
Jean-Christophe PLAGNIOL-VILLARD | 27c3868 | 2008-05-01 02:13:44 +0200 | [diff] [blame] | 201 | #undef RCSR |
Markus Klotzbücher | 43638c6 | 2006-03-06 15:04:25 +0100 | [diff] [blame] | 202 | #undef ICMR |
| 203 | #undef OSMR3 |
| 204 | #undef OSCR |
| 205 | #undef OWER |
| 206 | #undef OIER |
Marcel Ziswiler | 2a4741d | 2007-10-19 00:25:33 +0200 | [diff] [blame] | 207 | #undef CCCR |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 208 | |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 209 | /* Interrupt-Controller base address */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 210 | IC_BASE: .word 0x40d00000 |
| 211 | #define ICMR 0x04 |
| 212 | |
| 213 | /* Reset-Controller */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 214 | RST_BASE: .word 0x40f00030 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 215 | #define RCSR 0x00 |
| 216 | |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 217 | /* Operating System Timer */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 218 | OSTIMER_BASE: .word 0x40a00000 |
| 219 | #define OSMR3 0x0C |
| 220 | #define OSCR 0x10 |
| 221 | #define OWER 0x18 |
| 222 | #define OIER 0x1C |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 223 | |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 224 | /* Clock Manager Registers */ |
Markus Klotzbuecher | 40b0baf | 2006-03-24 14:35:25 +0100 | [diff] [blame] | 225 | #ifdef CONFIG_CPU_MONAHANS |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | # ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO |
| 227 | # error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!" |
| 228 | # endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */ |
| 229 | # ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO |
| 230 | # define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 |
| 231 | # endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */ |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 232 | #else /* !CONFIG_CPU_MONAHANS */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 233 | #ifdef CONFIG_SYS_CPUSPEED |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 234 | CC_BASE: .word 0x41300000 |
| 235 | #define CCCR 0x00 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 236 | cpuspeed: .word CONFIG_SYS_CPUSPEED |
| 237 | #else /* !CONFIG_SYS_CPUSPEED */ |
| 238 | #error "You have to define CONFIG_SYS_CPUSPEED!!" |
| 239 | #endif /* CONFIG_SYS_CPUSPEED */ |
Markus Klotzbuecher | 40b0baf | 2006-03-24 14:35:25 +0100 | [diff] [blame] | 240 | #endif /* CONFIG_CPU_MONAHANS */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 241 | |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 242 | /* takes care the CP15 update has taken place */ |
| 243 | .macro CPWAIT reg |
| 244 | mrc p15,0,\reg,c2,c0,0 |
| 245 | mov \reg,\reg |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 246 | sub pc,pc,#4 |
| 247 | .endm |
| 248 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 249 | cpu_init_crit: |
| 250 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 251 | /* mask all IRQs */ |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 252 | #ifndef CONFIG_CPU_MONAHANS |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 253 | ldr r0, IC_BASE |
| 254 | mov r1, #0x00 |
| 255 | str r1, [r0, #ICMR] |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 256 | #else /* CONFIG_CPU_MONAHANS */ |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 257 | /* Step 1 - Enable CP6 permission */ |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 258 | mrc p15, 0, r1, c15, c1, 0 @ read CPAR |
| 259 | orr r1, r1, #0x40 |
| 260 | mcr p15, 0, r1, c15, c1, 0 |
| 261 | CPWAIT r1 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 262 | |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 263 | /* Step 2 - Mask ICMR & ICMR2 */ |
| 264 | mov r1, #0 |
| 265 | mcr p6, 0, r1, c1, c0, 0 @ ICMR |
| 266 | mcr p6, 0, r1, c7, c0, 0 @ ICMR2 |
Markus Klotzbücher | e8cd008 | 2006-02-28 23:11:07 +0100 | [diff] [blame] | 267 | |
| 268 | /* turn off all clocks but the ones we will definitly require */ |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 269 | ldr r1, =CKENA |
| 270 | ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC) |
| 271 | str r2, [r1] |
| 272 | ldr r1, =CKENB |
| 273 | ldr r2, =(CKENB_6_IRQ) |
| 274 | str r2, [r1] |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 275 | #endif /* !CONFIG_CPU_MONAHANS */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 276 | |
Markus Klotzbuecher | 40b0baf | 2006-03-24 14:35:25 +0100 | [diff] [blame] | 277 | /* set clock speed */ |
| 278 | #ifdef CONFIG_CPU_MONAHANS |
| 279 | ldr r0, =ACCR |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 280 | ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) |
Markus Klotzbuecher | 40b0baf | 2006-03-24 14:35:25 +0100 | [diff] [blame] | 281 | str r1, [r0] |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 282 | #else /* !CONFIG_CPU_MONAHANS */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 283 | #ifdef CONFIG_SYS_CPUSPEED |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 284 | ldr r0, CC_BASE |
| 285 | ldr r1, cpuspeed |
| 286 | str r1, [r0, #CCCR] |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 287 | mov r0, #2 |
wdenk | 7f6c2cb | 2002-11-10 22:06:23 +0000 | [diff] [blame] | 288 | mcr p14, 0, r0, c6, c0, 0 |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 289 | |
| 290 | setspeed_done: |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 291 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 292 | #endif /* CONFIG_SYS_CPUSPEED */ |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 293 | #endif /* CONFIG_CPU_MONAHANS */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 294 | |
| 295 | /* |
| 296 | * before relocating, we have to setup RAM timing |
| 297 | * because memory timing is board-dependend, you will |
wdenk | 400558b | 2005-04-02 23:52:25 +0000 | [diff] [blame] | 298 | * find a lowlevel_init.S in your board directory. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 299 | */ |
| 300 | mov ip, lr |
wdenk | 400558b | 2005-04-02 23:52:25 +0000 | [diff] [blame] | 301 | bl lowlevel_init |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 302 | mov lr, ip |
| 303 | |
| 304 | /* Memory interfaces are working. Disable MMU and enable I-cache. */ |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 305 | /* mk: hmm, this is not in the monahans docs, leave it now but |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 306 | * check here if it doesn't work :-) */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 307 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 308 | ldr r0, =0x2001 /* enable access to all coproc. */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 309 | mcr p15, 0, r0, c15, c1, 0 |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 310 | CPWAIT r0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 311 | |
| 312 | mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 313 | CPWAIT r0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 314 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 315 | mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 316 | CPWAIT r0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 317 | |
| 318 | mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ |
Markus Klotzbücher | e026957 | 2006-02-07 20:04:48 +0100 | [diff] [blame] | 319 | CPWAIT r0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 320 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 321 | /* Enable the Icache */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 322 | /* |
| 323 | mrc p15, 0, r0, c1, c0, 0 |
| 324 | orr r0, r0, #0x1800 |
| 325 | mcr p15, 0, r0, c1, c0, 0 |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame] | 326 | CPWAIT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 327 | */ |
| 328 | mov pc, lr |
| 329 | |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 330 | #ifndef CONFIG_PRELOADER |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 331 | /****************************************************************************/ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 332 | /* */ |
| 333 | /* Interrupt handling */ |
| 334 | /* */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 335 | /****************************************************************************/ |
| 336 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 337 | /* IRQ stack frame */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 338 | |
| 339 | #define S_FRAME_SIZE 72 |
| 340 | |
| 341 | #define S_OLD_R0 68 |
| 342 | #define S_PSR 64 |
| 343 | #define S_PC 60 |
| 344 | #define S_LR 56 |
| 345 | #define S_SP 52 |
| 346 | |
| 347 | #define S_IP 48 |
| 348 | #define S_FP 44 |
| 349 | #define S_R10 40 |
| 350 | #define S_R9 36 |
| 351 | #define S_R8 32 |
| 352 | #define S_R7 28 |
| 353 | #define S_R6 24 |
| 354 | #define S_R5 20 |
| 355 | #define S_R4 16 |
| 356 | #define S_R3 12 |
| 357 | #define S_R2 8 |
| 358 | #define S_R1 4 |
| 359 | #define S_R0 0 |
| 360 | |
| 361 | #define MODE_SVC 0x13 |
| 362 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 363 | /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 364 | |
| 365 | .macro bad_save_user_regs |
| 366 | sub sp, sp, #S_FRAME_SIZE |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 367 | stmia sp, {r0 - r12} /* Calling r0-r12 */ |
| 368 | add r8, sp, #S_PC |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 369 | |
wdenk | f6e20fc | 2004-02-08 19:38:38 +0000 | [diff] [blame] | 370 | ldr r2, _armboot_start |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 371 | sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) |
| 372 | sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 373 | ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ |
| 374 | add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 375 | |
| 376 | add r5, sp, #S_SP |
| 377 | mov r1, lr |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 378 | stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 379 | mov r0, sp |
| 380 | .endm |
| 381 | |
| 382 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 383 | /* use irq_save_user_regs / irq_restore_user_regs for */ |
| 384 | /* IRQ/FIQ handling */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 385 | |
| 386 | .macro irq_save_user_regs |
| 387 | sub sp, sp, #S_FRAME_SIZE |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 388 | stmia sp, {r0 - r12} /* Calling r0-r12 */ |
| 389 | add r8, sp, #S_PC |
| 390 | stmdb r8, {sp, lr}^ /* Calling SP, LR */ |
| 391 | str lr, [r8, #0] /* Save calling PC */ |
| 392 | mrs r6, spsr |
| 393 | str r6, [r8, #4] /* Save CPSR */ |
| 394 | str r0, [r8, #8] /* Save OLD_R0 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 395 | mov r0, sp |
| 396 | .endm |
| 397 | |
| 398 | .macro irq_restore_user_regs |
| 399 | ldmia sp, {r0 - lr}^ @ Calling r0 - lr |
| 400 | mov r0, r0 |
| 401 | ldr lr, [sp, #S_PC] @ Get PC |
| 402 | add sp, sp, #S_FRAME_SIZE |
| 403 | subs pc, lr, #4 @ return & move spsr_svc into cpsr |
| 404 | .endm |
| 405 | |
| 406 | .macro get_bad_stack |
wdenk | f6e20fc | 2004-02-08 19:38:38 +0000 | [diff] [blame] | 407 | ldr r13, _armboot_start @ setup our mode stack |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 408 | sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) |
| 409 | sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 410 | |
| 411 | str lr, [r13] @ save caller lr / spsr |
| 412 | mrs lr, spsr |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 413 | str lr, [r13, #4] |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 414 | |
| 415 | mov r13, #MODE_SVC @ prepare SVC-Mode |
| 416 | msr spsr_c, r13 |
| 417 | mov lr, pc |
| 418 | movs pc, lr |
| 419 | .endm |
| 420 | |
| 421 | .macro get_irq_stack @ setup IRQ stack |
| 422 | ldr sp, IRQ_STACK_START |
| 423 | .endm |
| 424 | |
| 425 | .macro get_fiq_stack @ setup FIQ stack |
| 426 | ldr sp, FIQ_STACK_START |
| 427 | .endm |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 428 | #endif /* CONFIG_PRELOADER */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 429 | |
| 430 | |
| 431 | /****************************************************************************/ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 432 | /* */ |
| 433 | /* exception handlers */ |
| 434 | /* */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 435 | /****************************************************************************/ |
| 436 | |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 437 | #ifdef CONFIG_PRELOADER |
| 438 | .align 5 |
| 439 | do_hang: |
| 440 | ldr sp, _TEXT_BASE /* use 32 words abort stack */ |
| 441 | bl hang /* hang and never return */ |
| 442 | #else /* !CONFIG_PRELOADER */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 443 | .align 5 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 444 | undefined_instruction: |
| 445 | get_bad_stack |
| 446 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 447 | bl do_undefined_instruction |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 448 | |
| 449 | .align 5 |
| 450 | software_interrupt: |
| 451 | get_bad_stack |
| 452 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 453 | bl do_software_interrupt |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 454 | |
| 455 | .align 5 |
| 456 | prefetch_abort: |
| 457 | get_bad_stack |
| 458 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 459 | bl do_prefetch_abort |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 460 | |
| 461 | .align 5 |
| 462 | data_abort: |
| 463 | get_bad_stack |
| 464 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 465 | bl do_data_abort |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 466 | |
| 467 | .align 5 |
| 468 | not_used: |
| 469 | get_bad_stack |
| 470 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 471 | bl do_not_used |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 472 | |
| 473 | #ifdef CONFIG_USE_IRQ |
| 474 | |
| 475 | .align 5 |
| 476 | irq: |
| 477 | get_irq_stack |
| 478 | irq_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 479 | bl do_irq |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 480 | irq_restore_user_regs |
| 481 | |
| 482 | .align 5 |
| 483 | fiq: |
| 484 | get_fiq_stack |
| 485 | irq_save_user_regs /* someone ought to write a more */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 486 | bl do_fiq /* effiction fiq_save_user_regs */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 487 | irq_restore_user_regs |
| 488 | |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 489 | #else /* !CONFIG_USE_IRQ */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 490 | |
| 491 | .align 5 |
| 492 | irq: |
| 493 | get_bad_stack |
| 494 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 495 | bl do_irq |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 496 | |
| 497 | .align 5 |
| 498 | fiq: |
| 499 | get_bad_stack |
| 500 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 501 | bl do_fiq |
Marek Vasut | 5ab877b | 2010-07-06 02:48:35 +0200 | [diff] [blame^] | 502 | #endif /* CONFIG_PRELOADER */ |
Marcel Ziswiler | 10c7382 | 2007-12-30 03:30:56 +0100 | [diff] [blame] | 503 | #endif /* CONFIG_USE_IRQ */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 504 | |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 505 | /****************************************************************************/ |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 506 | /* */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 507 | /* Reset function: the PXA250 doesn't have a reset function, so we have to */ |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 508 | /* perform a watchdog timeout for a soft reset. */ |
| 509 | /* */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 510 | /****************************************************************************/ |
| 511 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 512 | .align 5 |
| 513 | .globl reset_cpu |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 514 | |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 515 | /* FIXME: this code is PXA250 specific. How is this handled on */ |
| 516 | /* other XScale processors? */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 517 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 518 | reset_cpu: |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 519 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 520 | /* We set OWE:WME (watchdog enable) and wait until timeout happens */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 521 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 522 | ldr r0, OSTIMER_BASE |
| 523 | ldr r1, [r0, #OWER] |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 524 | orr r1, r1, #0x0001 /* bit0: WME */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 525 | str r1, [r0, #OWER] |
| 526 | |
| 527 | /* OS timer does only wrap every 1165 seconds, so we have to set */ |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 528 | /* the match register as well. */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 529 | |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 530 | ldr r1, [r0, #OSCR] /* read OS timer */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 531 | add r1, r1, #0x800 /* let OSMR3 match after */ |
| 532 | add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ |
| 533 | str r1, [r0, #OSMR3] |
| 534 | |
| 535 | reset_endless: |
| 536 | |
| 537 | b reset_endless |