blob: 563528ca5e6362c5b2b78dcaa197712e69370a52 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
Simon Glass7b51b572019-08-01 09:46:52 -060012#include <env.h>
wdenk8bde7f72003-06-27 21:31:46 +000013#include <fpga.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053014#include <fs.h>
Simon Glass0c670fc2019-08-01 09:46:36 -060015#include <gzip.h>
Simon Glass4d72caa2020-05-10 11:40:01 -060016#include <image.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000017#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000018
Michal Simekf4c7a4a2018-06-04 14:57:34 +020019static long do_fpga_get_device(char *arg)
20{
21 long dev = FPGA_INVALID_DEVICE;
22 char *devstr = env_get("fpga");
23
24 if (devstr)
25 /* Should be strtol to handle -1 cases */
26 dev = simple_strtol(devstr, NULL, 16);
27
Michal Simek8c75f792018-07-26 15:33:51 +020028 if (dev == FPGA_INVALID_DEVICE && arg)
Michal Simekf4c7a4a2018-06-04 14:57:34 +020029 dev = simple_strtol(arg, NULL, 16);
30
31 debug("%s: device = %ld\n", __func__, dev);
32
33 return dev;
34}
35
Michal Simek85754792018-06-04 15:51:23 +020036static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
37 cmd_tbl_t *cmdtp, int argc, char *const argv[])
38{
39 size_t local_data_size;
40 long local_fpga_data;
41
42 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
43
44 if (argc != cmdtp->maxargs) {
45 debug("fpga: incorrect parameters passed\n");
46 return CMD_RET_USAGE;
47 }
48
49 *dev = do_fpga_get_device(argv[0]);
50
51 local_fpga_data = simple_strtol(argv[1], NULL, 16);
52 if (!local_fpga_data) {
53 debug("fpga: zero fpga_data address\n");
54 return CMD_RET_USAGE;
55 }
56 *fpga_data = local_fpga_data;
57
58 local_data_size = simple_strtoul(argv[2], NULL, 16);
59 if (!local_data_size) {
60 debug("fpga: zero size\n");
61 return CMD_RET_USAGE;
62 }
63 *data_size = local_data_size;
64
65 return 0;
66}
67
Michal Simek323fe382018-05-30 10:00:40 +020068#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simekb5d19a92018-06-05 15:14:39 +020069int do_fpga_loads(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000070{
wdenkd4ca31c2004-01-02 14:00:00 +000071 size_t data_size = 0;
Michal Simekb5d19a92018-06-05 15:14:39 +020072 long fpga_data, dev;
73 int ret;
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053074 struct fpga_secure_info fpga_sec_info;
75
76 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
wdenk4a9cbbe2002-08-27 09:48:53 +000077
Michal Simekb5d19a92018-06-05 15:14:39 +020078 if (argc < 5) {
79 debug("fpga: incorrect parameters passed\n");
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +053080 return CMD_RET_USAGE;
81 }
82
Michal Simekb5d19a92018-06-05 15:14:39 +020083 if (argc == 6)
84 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
85 simple_strtoull(argv[5],
86 NULL, 16);
87 else
88 /*
89 * If 6th parameter is not passed then do_fpga_check_params
90 * will get 5 instead of expected 6 which means that function
91 * return CMD_RET_USAGE. Increase number of params +1 to pass
92 * this.
93 */
94 argc++;
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +053095
Michal Simekb5d19a92018-06-05 15:14:39 +020096 fpga_sec_info.encflag = (u8)simple_strtoul(argv[4], NULL, 16);
97 fpga_sec_info.authflag = (u8)simple_strtoul(argv[3], NULL, 16);
Michal Simek44d839b2018-05-30 11:18:38 +020098
Michal Simekb5d19a92018-06-05 15:14:39 +020099 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
100 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
101 debug("fpga: Use <fpga load> for NonSecure bitstream\n");
Michal Simekccd65202018-05-30 10:04:34 +0200102 return CMD_RET_USAGE;
Stefano Babica790b5b2010-10-19 09:22:52 +0200103 }
104
Michal Simekb5d19a92018-06-05 15:14:39 +0200105 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
106 !fpga_sec_info.userkey_addr) {
107 debug("fpga: User key not provided\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000108 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000109 }
Michal Simekb5d19a92018-06-05 15:14:39 +0200110
111 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
112 cmdtp, argc, argv);
113 if (ret)
114 return ret;
115
116 return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info);
wdenk4a9cbbe2002-08-27 09:48:53 +0000117}
Michal Simekb5d19a92018-06-05 15:14:39 +0200118#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000119
Michal Simek49503f92018-06-04 15:51:16 +0200120#if defined(CONFIG_CMD_FPGA_LOADFS)
121static int do_fpga_loadfs(cmd_tbl_t *cmdtp, int flag, int argc,
122 char *const argv[])
123{
124 size_t data_size = 0;
125 long fpga_data, dev;
126 int ret;
127 fpga_fs_info fpga_fsinfo;
128
129 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
130 cmdtp, argc, argv);
131 if (ret)
132 return ret;
133
134 fpga_fsinfo.fstype = FS_TYPE_ANY;
135 fpga_fsinfo.blocksize = (unsigned int)simple_strtoul(argv[3], NULL, 16);
136 fpga_fsinfo.interface = argv[4];
137 fpga_fsinfo.dev_part = argv[5];
138 fpga_fsinfo.filename = argv[6];
139
140 return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo);
141}
142#endif
143
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200144static int do_fpga_info(cmd_tbl_t *cmdtp, int flag, int argc,
145 char * const argv[])
146{
147 long dev = do_fpga_get_device(argv[0]);
148
149 return fpga_info(dev);
150}
151
Michal Simek85754792018-06-04 15:51:23 +0200152static int do_fpga_dump(cmd_tbl_t *cmdtp, int flag, int argc,
153 char * const argv[])
154{
155 size_t data_size = 0;
156 long fpga_data, dev;
157 int ret;
158
159 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
160 cmdtp, argc, argv);
161 if (ret)
162 return ret;
163
164 return fpga_dump(dev, (void *)fpga_data, data_size);
165}
166
167static int do_fpga_load(cmd_tbl_t *cmdtp, int flag, int argc,
168 char * const argv[])
169{
170 size_t data_size = 0;
171 long fpga_data, dev;
172 int ret;
173
174 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
175 cmdtp, argc, argv);
176 if (ret)
177 return ret;
178
179 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL);
180}
181
182static int do_fpga_loadb(cmd_tbl_t *cmdtp, int flag, int argc,
183 char * const argv[])
184{
185 size_t data_size = 0;
186 long fpga_data, dev;
187 int ret;
188
189 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
190 cmdtp, argc, argv);
191 if (ret)
192 return ret;
193
194 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
195}
196
197#if defined(CONFIG_CMD_FPGA_LOADP)
198static int do_fpga_loadp(cmd_tbl_t *cmdtp, int flag, int argc,
199 char * const argv[])
200{
201 size_t data_size = 0;
202 long fpga_data, dev;
203 int ret;
204
205 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
206 cmdtp, argc, argv);
207 if (ret)
208 return ret;
209
210 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL);
211}
212#endif
213
214#if defined(CONFIG_CMD_FPGA_LOADBP)
215static int do_fpga_loadbp(cmd_tbl_t *cmdtp, int flag, int argc,
216 char * const argv[])
217{
218 size_t data_size = 0;
219 long fpga_data, dev;
220 int ret;
221
222 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
223 cmdtp, argc, argv);
224 if (ret)
225 return ret;
226
227 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
228 BIT_PARTIAL);
229}
230#endif
231
Michal Simek2892fe82018-06-04 16:15:58 +0200232#if defined(CONFIG_CMD_FPGA_LOADMK)
233static int do_fpga_loadmk(cmd_tbl_t *cmdtp, int flag, int argc,
234 char * const argv[])
235{
236 size_t data_size = 0;
237 void *fpga_data = NULL;
238#if defined(CONFIG_FIT)
239 const char *fit_uname = NULL;
240 ulong fit_addr;
241#endif
242 ulong dev = do_fpga_get_device(argv[0]);
243 char *datastr = env_get("fpgadata");
244
Michal Simek8c75f792018-07-26 15:33:51 +0200245 debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
246
247 if (dev == FPGA_INVALID_DEVICE) {
248 debug("fpga: Invalid fpga device\n");
249 return CMD_RET_USAGE;
250 }
251
252 if (argc == 0 && !datastr) {
253 debug("fpga: No datastr passed\n");
254 return CMD_RET_USAGE;
255 }
Michal Simek2892fe82018-06-04 16:15:58 +0200256
257 if (argc == 2) {
Michal Simek8c75f792018-07-26 15:33:51 +0200258 datastr = argv[1];
259 debug("fpga: Full command with two args\n");
260 } else if (argc == 1 && !datastr) {
261 debug("fpga: Dev is setup - fpgadata passed\n");
262 datastr = argv[0];
263 }
264
Michal Simek2892fe82018-06-04 16:15:58 +0200265#if defined(CONFIG_FIT)
Michal Simek8c75f792018-07-26 15:33:51 +0200266 if (fit_parse_subimage(datastr, (ulong)fpga_data,
267 &fit_addr, &fit_uname)) {
268 fpga_data = (void *)fit_addr;
269 debug("* fpga: subimage '%s' from FIT image ",
270 fit_uname);
271 debug("at 0x%08lx\n", fit_addr);
272 } else
Michal Simek2892fe82018-06-04 16:15:58 +0200273#endif
Michal Simek8c75f792018-07-26 15:33:51 +0200274 {
275 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
276 debug("* fpga: cmdline image address = 0x%08lx\n",
277 (ulong)fpga_data);
278 }
279 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
280 if (!fpga_data) {
281 puts("Zero fpga_data address\n");
282 return CMD_RET_USAGE;
Michal Simek2892fe82018-06-04 16:15:58 +0200283 }
284
285 switch (genimg_get_format(fpga_data)) {
Tom Rinic76c93a2019-05-23 07:14:07 -0400286#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
Michal Simek2892fe82018-06-04 16:15:58 +0200287 case IMAGE_FORMAT_LEGACY:
288 {
289 image_header_t *hdr = (image_header_t *)fpga_data;
290 ulong data;
291 u8 comp;
292
293 comp = image_get_comp(hdr);
294 if (comp == IH_COMP_GZIP) {
295#if defined(CONFIG_GZIP)
296 ulong image_buf = image_get_data(hdr);
297 ulong image_size = ~0UL;
298
299 data = image_get_load(hdr);
300
301 if (gunzip((void *)data, ~0UL, (void *)image_buf,
302 &image_size) != 0) {
303 puts("GUNZIP: error\n");
Michal Simeka2d10332018-06-05 16:43:38 +0200304 return CMD_RET_FAILURE;
Michal Simek2892fe82018-06-04 16:15:58 +0200305 }
306 data_size = image_size;
307#else
308 puts("Gunzip image is not supported\n");
309 return 1;
310#endif
311 } else {
312 data = (ulong)image_get_data(hdr);
313 data_size = image_get_data_size(hdr);
314 }
315 return fpga_load(dev, (void *)data, data_size,
316 BIT_FULL);
317 }
318#endif
319#if defined(CONFIG_FIT)
320 case IMAGE_FORMAT_FIT:
321 {
322 const void *fit_hdr = (const void *)fpga_data;
323 int noffset;
324 const void *fit_data;
325
326 if (!fit_uname) {
327 puts("No FIT subimage unit name\n");
Michal Simeka2d10332018-06-05 16:43:38 +0200328 return CMD_RET_FAILURE;
Michal Simek2892fe82018-06-04 16:15:58 +0200329 }
330
331 if (!fit_check_format(fit_hdr)) {
332 puts("Bad FIT image format\n");
Michal Simeka2d10332018-06-05 16:43:38 +0200333 return CMD_RET_FAILURE;
Michal Simek2892fe82018-06-04 16:15:58 +0200334 }
335
336 /* get fpga component image node offset */
337 noffset = fit_image_get_node(fit_hdr, fit_uname);
338 if (noffset < 0) {
339 printf("Can't find '%s' FIT subimage\n", fit_uname);
Michal Simeka2d10332018-06-05 16:43:38 +0200340 return CMD_RET_FAILURE;
Michal Simek2892fe82018-06-04 16:15:58 +0200341 }
342
343 /* verify integrity */
344 if (!fit_image_verify(fit_hdr, noffset)) {
345 puts("Bad Data Hash\n");
Michal Simeka2d10332018-06-05 16:43:38 +0200346 return CMD_RET_FAILURE;
Michal Simek2892fe82018-06-04 16:15:58 +0200347 }
348
Tien Fong Chee9184c922019-02-12 20:41:34 +0800349 /* get fpga subimage/external data address and length */
350 if (fit_image_get_data_and_size(fit_hdr, noffset,
351 &fit_data, &data_size)) {
Michal Simek2892fe82018-06-04 16:15:58 +0200352 puts("Fpga subimage data not found\n");
Michal Simeka2d10332018-06-05 16:43:38 +0200353 return CMD_RET_FAILURE;
Michal Simek2892fe82018-06-04 16:15:58 +0200354 }
355
356 return fpga_load(dev, fit_data, data_size, BIT_FULL);
357 }
358#endif
359 default:
360 puts("** Unknown image type\n");
Michal Simeka2d10332018-06-05 16:43:38 +0200361 return CMD_RET_FAILURE;
Michal Simek2892fe82018-06-04 16:15:58 +0200362 }
363}
364#endif
365
Michal Simek9657d972018-06-04 14:55:20 +0200366static cmd_tbl_t fpga_commands[] = {
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200367 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek85754792018-06-04 15:51:23 +0200368 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
369 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
370 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
371#if defined(CONFIG_CMD_FPGA_LOADP)
372 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
373#endif
374#if defined(CONFIG_CMD_FPGA_LOADBP)
375 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
376#endif
Michal Simek49503f92018-06-04 15:51:16 +0200377#if defined(CONFIG_CMD_FPGA_LOADFS)
378 U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""),
379#endif
Michal Simek2892fe82018-06-04 16:15:58 +0200380#if defined(CONFIG_CMD_FPGA_LOADMK)
381 U_BOOT_CMD_MKENT(loadmk, 2, 1, do_fpga_loadmk, "", ""),
382#endif
Michal Simekb5d19a92018-06-05 15:14:39 +0200383#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
384 U_BOOT_CMD_MKENT(loads, 6, 1, do_fpga_loads, "", ""),
385#endif
Michal Simek9657d972018-06-04 14:55:20 +0200386};
387
388static int do_fpga_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
389 char *const argv[])
390{
391 cmd_tbl_t *fpga_cmd;
392 int ret;
393
394 if (argc < 2)
395 return CMD_RET_USAGE;
396
397 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
398 ARRAY_SIZE(fpga_commands));
Michal Simek9657d972018-06-04 14:55:20 +0200399 if (!fpga_cmd) {
400 debug("fpga: non existing command\n");
401 return CMD_RET_USAGE;
402 }
403
404 argc -= 2;
405 argv += 2;
406
407 if (argc > fpga_cmd->maxargs) {
408 debug("fpga: more parameters passed\n");
409 return CMD_RET_USAGE;
410 }
411
412 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
413
414 return cmd_process_error(fpga_cmd, ret);
415}
416
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530417#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9657d972018-06-04 14:55:20 +0200418U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530419#else
Michal Simek9657d972018-06-04 14:55:20 +0200420U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530421#endif
Michal Simekfc598412013-04-26 13:10:07 +0200422 "loadable FPGA image support",
423 "[operation type] [device number] [image address] [image size]\n"
424 "fpga operations:\n"
Michal Simek2d73f0d2015-01-26 08:52:27 +0100425 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simekfc598412013-04-26 13:10:07 +0200426 " info\t[dev]\t\t\tlist known device information\n"
427 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200428#if defined(CONFIG_CMD_FPGA_LOADP)
429 " loadp\t[dev] [address] [size]\t"
430 "Load device from memory buffer with partial bitstream\n"
431#endif
Michal Simekfc598412013-04-26 13:10:07 +0200432 " loadb\t[dev] [address] [size]\t"
433 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200434#if defined(CONFIG_CMD_FPGA_LOADBP)
435 " loadbp\t[dev] [address] [size]\t"
436 "Load device from bitstream buffer with partial bitstream"
437 "(Xilinx only)\n"
438#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530439#if defined(CONFIG_CMD_FPGA_LOADFS)
440 "Load device from filesystem (FAT by default) (Xilinx only)\n"
441 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
442 " [<dev[:part]>] <filename>\n"
443#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530444#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200445 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100446#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200447 "\n"
448 "\tFor loadmk operating on FIT format uImage address must include\n"
449 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100450#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530451#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530452#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
453 "Load encrypted bitstream (Xilinx only)\n"
454 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
455 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
456 "Loads the secure bistreams(authenticated/encrypted/both\n"
457 "authenticated and encrypted) of [size] from [address].\n"
458 "The auth-OCM/DDR flag specifies to perform authentication\n"
459 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
460 "The enc flag specifies which key to be used for decryption\n"
461 "0-device key, 1-user key, 2-no encryption.\n"
462 "The optional Userkey address specifies from which address key\n"
463 "has to be used for decryption if user key is selected.\n"
Robert P. J. Dayce9e4e02019-05-28 11:33:27 -0400464 "NOTE: the secure bitstream has to be created using Xilinx\n"
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530465 "bootgen tool only.\n"
466#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100467);