Blame - arch/riscv/Kconfig - platform/external/u-boot

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Bin Meng	117a433	2018-09-26 06:55:06 -0700	[diff] [blame]	1	menu "RISC-V architecture"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	2	depends on RISCV
				3
				4	config SYS_ARCH
				5	default "riscv"
				6
				7	choice
				8	prompt "Target select"
				9	optional
				10
Rick Chen	6f4dd62	2018-05-29 09:54:40 +0800	[diff] [blame]	11	config TARGET_AX25_AE350
				12	bool "Support ax25-ae350"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	13
Bin Meng	510e379	2018-09-26 06:55:21 -0700	[diff] [blame]	14	config TARGET_QEMU_VIRT
				15	bool "Support QEMU Virt Board"
				16
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	17	endchoice
				18
Rick Chen	52923c6	2018-11-07 09:34:06 +0800	[diff] [blame]	19	# board-specific options below
Rick Chen	6f4dd62	2018-05-29 09:54:40 +0800	[diff] [blame]	20	source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng	510e379	2018-09-26 06:55:21 -0700	[diff] [blame]	21	source "board/emulation/qemu-riscv/Kconfig"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	22
Rick Chen	52923c6	2018-11-07 09:34:06 +0800	[diff] [blame]	23	# platform-specific options below
				24	source "arch/riscv/cpu/ax25/Kconfig"
				25
				26	# architecture-specific options below
				27
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	28	choice
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	29	prompt "Base ISA"
				30	default ARCH_RV32I
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	31
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	32	config ARCH_RV32I
				33	bool "RV32I"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	34	select 32BIT
				35	help
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	36	Choose this option to target the RV32I base integer instruction set.
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	37
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	38	config ARCH_RV64I
				39	bool "RV64I"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	40	select 64BIT
Lukas Auer	7115856	2018-11-22 11:26:13 +0100	[diff] [blame]	41	select PHYS_64BIT
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	42	help
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	43	Choose this option to target the RV64I base integer instruction set.
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	44
				45	endchoice
				46
Lukas Auer	8176ea4	2018-12-12 06:12:23 -0800	[diff] [blame]	47	choice
				48	prompt "Code Model"
				49	default CMODEL_MEDLOW
				50
				51	config CMODEL_MEDLOW
				52	bool "medium low code model"
				53	help
				54	U-Boot and its statically defined symbols must lie within a single 2 GiB
				55	address range and must lie between absolute addresses -2 GiB and +2 GiB.
				56
				57	config CMODEL_MEDANY
				58	bool "medium any code model"
				59	help
				60	U-Boot and its statically defined symbols must be within any single 2 GiB
				61	address range.
				62
				63	endchoice
				64
Anup Patel	3cfc825	2018-12-12 06:12:29 -0800	[diff] [blame]	65	choice
				66	prompt "Run Mode"
				67	default RISCV_MMODE
				68
				69	config RISCV_MMODE
				70	bool "Machine"
				71	help
				72	Choose this option to build U-Boot for RISC-V M-Mode.
				73
				74	config RISCV_SMODE
				75	bool "Supervisor"
				76	help
				77	Choose this option to build U-Boot for RISC-V S-Mode.
				78
				79	endchoice
				80
Lukas Auer	d57ffa6	2018-11-22 11:26:14 +0100	[diff] [blame]	81	config RISCV_ISA_C
				82	bool "Emit compressed instructions"
				83	default y
				84	help
				85	Adds "C" to the ISA subsets that the toolchain is allowed to emit
				86	when building U-Boot, which results in compressed instructions in the
				87	U-Boot binary.
				88
				89	config RISCV_ISA_A
				90	def_bool y
				91
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	92	config 32BIT
				93	bool
				94
				95	config 64BIT
				96	bool
				97
Bin Meng	644a3cd	2018-12-12 06:12:30 -0800	[diff] [blame]	98	config SIFIVE_CLINT
				99	bool
				100	depends on RISCV_MMODE
				101	select REGMAP
				102	select SYSCON
				103	help
				104	The SiFive CLINT block holds memory-mapped control and status registers
				105	associated with software and timer interrupts.
				106
Anup Patel	511107d	2018-12-12 06:12:31 -0800	[diff] [blame^]	107	config RISCV_RDTIME
				108	bool
				109	default y if RISCV_SMODE
				110	help
				111	The provides the riscv_get_time() API that is implemented using the
				112	standard rdtime instruction. This is the case for S-mode U-Boot, and
				113	is useful for processors that support rdtime in M-mode too.
				114
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	115	endmenu