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Stefan Roese566806c2007-10-05 17:11:30 +02001/*
Grant Erickson8a24c072008-05-22 14:44:24 -07002 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
4 *
Stefan Roese566806c2007-10-05 17:11:30 +02005 * (C) Copyright 2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/************************************************************************
28 * kilauea.h - configuration for AMCC Kilauea (405EX)
29 ***********************************************************************/
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*-----------------------------------------------------------------------
35 * High Level Configuration Options
36 *----------------------------------------------------------------------*/
37#define CONFIG_KILAUEA 1 /* Board is Kilauea */
38#define CONFIG_4xx 1 /* ... PPC4xx family */
39#define CONFIG_405EX 1 /* Specifc 405EX support*/
40#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
41
Stefan Roese490f2042008-06-06 15:55:03 +020042/*
43 * Include common defines/options for all AMCC eval boards
44 */
45#define CONFIG_HOSTNAME kilauea
46#include "amcc-common.h"
47
Stefan Roese566806c2007-10-05 17:11:30 +020048#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
49#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Stefan Roese353f2682007-10-23 10:10:08 +020050#define CONFIG_BOARD_EMAC_COUNT
Stefan Roese566806c2007-10-05 17:11:30 +020051
52/*-----------------------------------------------------------------------
53 * Base addresses -- Note these are effective addresses where the
54 * actual resources get mapped (not physical addresses)
55 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_FLASH_BASE 0xFC000000
57#define CONFIG_SYS_NAND_ADDR 0xF8000000
58#define CONFIG_SYS_FPGA_BASE 0xF0000000
59#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
Stefan Roese566806c2007-10-05 17:11:30 +020060
61/*-----------------------------------------------------------------------
Grant Erickson8a24c072008-05-22 14:44:24 -070062 * Initial RAM & Stack Pointer Configuration Options
63 *
64 * There are traditionally three options for the primordial
65 * (i.e. initial) stack usage on the 405-series:
66 *
67 * 1) On-chip Memory (OCM) (i.e. SRAM)
68 * 2) Data cache
69 * 3) SDRAM
70 *
71 * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
72 * the latter of which is less than desireable since it requires
73 * setting up the SDRAM and ECC in assembly code.
74 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075 * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
Grant Erickson8a24c072008-05-22 14:44:24 -070076 * select on the External Bus Controller (EBC) and then select a
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
78 * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
79 * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
Grant Erickson8a24c072008-05-22 14:44:24 -070080 * physical SDRAM to use (3).
81 *-----------------------------------------------------------------------*/
82
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_INIT_DCACHE_CS 4
Grant Erickson8a24c072008-05-22 14:44:24 -070084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#if defined(CONFIG_SYS_INIT_DCACHE_CS)
86#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
Grant Erickson8a24c072008-05-22 14:44:24 -070087#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
89#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
Grant Erickson8a24c072008-05-22 14:44:24 -070090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_INIT_RAM_END (4 << 10) /* 4 KiB */
92#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
93#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Stefan Roese566806c2007-10-05 17:11:30 +020094
Grant Erickson8a24c072008-05-22 14:44:24 -070095/*
96 * If the data cache is being used for the primordial stack and global
97 * data area, the POST word must be placed somewhere else. The General
98 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
99 * its compare and mask register contents across reset, so it is used
100 * for the POST word.
101 */
102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#if defined(CONFIG_SYS_INIT_DCACHE_CS)
104# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
105# define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
Grant Erickson8a24c072008-05-22 14:44:24 -0700106#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107# define CONFIG_SYS_INIT_EXTRA_SIZE 16
108# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
109# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
110# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
111#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
Stefan Roese566806c2007-10-05 17:11:30 +0200112
113/*-----------------------------------------------------------------------
114 * Serial Port
115 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Stefan Roese566806c2007-10-05 17:11:30 +0200117/* define this if you want console on UART1 */
118#undef CONFIG_UART1_CONSOLE
119
Stefan Roese566806c2007-10-05 17:11:30 +0200120/*-----------------------------------------------------------------------
121 * Environment
122 *----------------------------------------------------------------------*/
123#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200124#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese566806c2007-10-05 17:11:30 +0200125#else
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200126#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200127#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Stefan Roese566806c2007-10-05 17:11:30 +0200128#endif
129
130/*-----------------------------------------------------------------------
131 * FLASH related
132 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200134#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese566806c2007-10-05 17:11:30 +0200135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
137#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
138#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese566806c2007-10-05 17:11:30 +0200139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
141#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese566806c2007-10-05 17:11:30 +0200142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
144#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese566806c2007-10-05 17:11:30 +0200145
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200146#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200147#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200149#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese566806c2007-10-05 17:11:30 +0200150
151/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200152#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
153#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200154#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese566806c2007-10-05 17:11:30 +0200155
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100156/*
157 * IPL (Initial Program Loader, integrated inside CPU)
158 * Will load first 4k from NAND (SPL) into cache and execute it from there.
159 *
160 * SPL (Secondary Program Loader)
161 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
162 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
163 * controller and the NAND controller so that the special U-Boot image can be
164 * loaded from NAND to SDRAM.
165 *
166 * NUB (NAND U-Boot)
167 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
168 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
169 *
Stefan Roeseec724f82008-06-02 17:13:55 +0200170 * On 405EX the SPL is copied to SDRAM before the NAND controller is
171 * set up. While still running from location 0xfffff000...0xffffffff the
172 * NAND controller cannot be accessed since it is attached to CS0 too.
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
175#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
176#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
177#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
178#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
179#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100180
181/*
182 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
185#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100186
187/*
188 * Now the NAND chip has to be defined (no autodetection used!)
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
191#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
192#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
193#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
194#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_NAND_ECCSIZE 256
197#define CONFIG_SYS_NAND_ECCBYTES 3
198#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
199#define CONFIG_SYS_NAND_OOBSIZE 16
200#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
201#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100202
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200203#ifdef CONFIG_ENV_IS_IN_NAND
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100204/*
205 * For NAND booting the environment is embedded in the U-Boot image. Please take
206 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
209#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200210#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100211#endif
212
213/*-----------------------------------------------------------------------
214 * NAND FLASH
215 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
218#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100219
Stefan Roese566806c2007-10-05 17:11:30 +0200220/*-----------------------------------------------------------------------
221 * DDR SDRAM
222 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
Stefan Roese566806c2007-10-05 17:11:30 +0200224
Adam Grahamf6b6c452008-09-03 12:26:59 -0700225/*
226 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
227 *
228 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
229 * SDRAM Controller DDR autocalibration values and takes a lot longer
230 * to run than Method_B.
231 * (See the Method_A and Method_B algorithm discription in the file:
232 * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
233 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
234 *
235 * DDR Autocalibration Method_B is the default.
236 */
237#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
238#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
239#undef CONFIG_PPC4xx_DDR_METHOD_A
240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
Grant Erickson8a24c072008-05-22 14:44:24 -0700242
243/* DDR1/2 SDRAM Device Control Register Data Values */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
Grant Erickson8a24c072008-05-22 14:44:24 -0700245 SDRAM_RXBAS_SDSZ_256MB | \
246 SDRAM_RXBAS_SDAM_MODE7 | \
247 SDRAM_RXBAS_SDBE_ENABLE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
249#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
250#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
251#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
Grant Erickson2e205082008-07-09 16:46:35 -0700252 SDRAM_MCOPT1_8_BANKS | \
253 SDRAM_MCOPT1_DDR2_TYPE | \
254 SDRAM_MCOPT1_QDEP | \
255 SDRAM_MCOPT1_DCOO_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
257#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700258 SDRAM_MODT_EB0R_ENABLE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
260#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
Grant Erickson2e205082008-07-09 16:46:35 -0700261 SDRAM_CODT_CKLZ_36OHM | \
262 SDRAM_CODT_DQS_1_8_V_DDR2 | \
263 SDRAM_CODT_IO_NMODE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
265#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700266 SDRAM_INITPLR_IMWT_ENCODE(80) | \
267 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700269 SDRAM_INITPLR_IMWT_ENCODE(3) | \
270 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
271 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
272 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700274 SDRAM_INITPLR_IMWT_ENCODE(2) | \
275 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
276 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
277 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700279 SDRAM_INITPLR_IMWT_ENCODE(2) | \
280 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
281 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
282 SDRAM_INITPLR_IMA_ENCODE(0))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700284 SDRAM_INITPLR_IMWT_ENCODE(2) | \
285 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
286 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
287 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
288 JEDEC_MA_EMR_RTT_75OHM))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700290 SDRAM_INITPLR_IMWT_ENCODE(2) | \
291 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
292 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
293 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
294 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
295 JEDEC_MA_MR_BLEN_4 | \
296 JEDEC_MA_MR_DLL_RESET))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700298 SDRAM_INITPLR_IMWT_ENCODE(3) | \
299 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
300 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
301 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700303 SDRAM_INITPLR_IMWT_ENCODE(26) | \
304 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700306 SDRAM_INITPLR_IMWT_ENCODE(26) | \
307 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700309 SDRAM_INITPLR_IMWT_ENCODE(26) | \
310 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700312 SDRAM_INITPLR_IMWT_ENCODE(26) | \
313 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700315 SDRAM_INITPLR_IMWT_ENCODE(2) | \
316 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
317 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
318 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
319 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
320 JEDEC_MA_MR_BLEN_4))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700322 SDRAM_INITPLR_IMWT_ENCODE(2) | \
323 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
324 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
325 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
326 JEDEC_MA_EMR_RDQS_DISABLE | \
327 JEDEC_MA_EMR_DQS_DISABLE | \
328 JEDEC_MA_EMR_RTT_DISABLED | \
329 JEDEC_MA_EMR_ODS_NORMAL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700331 SDRAM_INITPLR_IMWT_ENCODE(2) | \
332 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
333 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
334 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
335 JEDEC_MA_EMR_RDQS_DISABLE | \
336 JEDEC_MA_EMR_DQS_DISABLE | \
337 JEDEC_MA_EMR_RTT_DISABLED | \
338 JEDEC_MA_EMR_ODS_NORMAL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
340#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
341#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700342 SDRAM_RQDC_RQFD_ENCODE(56))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
344#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
345#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
Grant Erickson2e205082008-07-09 16:46:35 -0700346 SDRAM_DLCR_DLCS_CONT_DONE | \
347 SDRAM_DLCR_DLCV_ENCODE(165))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
349#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
350#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
Grant Erickson2e205082008-07-09 16:46:35 -0700351 SDRAM_SDTR1_RTW_2_CLK | \
352 SDRAM_SDTR1_RTRO_1_CLK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
Grant Erickson2e205082008-07-09 16:46:35 -0700354 SDRAM_SDTR2_WTR_2_CLK | \
355 SDRAM_SDTR2_XSNR_32_CLK | \
356 SDRAM_SDTR2_WPC_4_CLK | \
357 SDRAM_SDTR2_RPC_2_CLK | \
358 SDRAM_SDTR2_RP_3_CLK | \
359 SDRAM_SDTR2_RRD_2_CLK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
Grant Erickson2e205082008-07-09 16:46:35 -0700361 SDRAM_SDTR3_RC_ENCODE(11) | \
362 SDRAM_SDTR3_XCS | \
363 SDRAM_SDTR3_RFC_ENCODE(26))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
Grant Erickson2e205082008-07-09 16:46:35 -0700365 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
366 SDRAM_MMODE_BLEN_4)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700368 SDRAM_MEMODE_RTT_75OHM)
Grant Erickson8a24c072008-05-22 14:44:24 -0700369
Stefan Roese566806c2007-10-05 17:11:30 +0200370/*-----------------------------------------------------------------------
371 * I2C
372 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
Stefan Roese566806c2007-10-05 17:11:30 +0200374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
376#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
377#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roese566806c2007-10-05 17:11:30 +0200378
379/* Standard DTT sensor configuration */
380#define CONFIG_DTT_DS1775 1
381#define CONFIG_DTT_SENSORS { 0 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_I2C_DTT_ADDR 0x48
Stefan Roese566806c2007-10-05 17:11:30 +0200383
384/* RTC configuration */
385#define CONFIG_RTC_DS1338 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Stefan Roese566806c2007-10-05 17:11:30 +0200387
388/*-----------------------------------------------------------------------
389 * Ethernet
390 *----------------------------------------------------------------------*/
391#define CONFIG_M88E1111_PHY 1
392#define CONFIG_IBM_EMAC4_V4 1
Grant Erickson1740c1b2008-07-08 08:35:00 -0700393#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
Stefan Roese566806c2007-10-05 17:11:30 +0200394#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
395
396#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
397#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
398
399#define CONFIG_HAS_ETH0 1
400
Stefan Roese566806c2007-10-05 17:11:30 +0200401#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
402#define CONFIG_PHY1_ADDR 2
403
Adam Grahamf6b6c452008-09-03 12:26:59 -0700404/* Debug messages for the DDR autocalibration */
405#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
406
Stefan Roese490f2042008-06-06 15:55:03 +0200407/*
408 * Default environment variables
409 */
Stefan Roese566806c2007-10-05 17:11:30 +0200410#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200411 CONFIG_AMCC_DEF_ENV \
412 CONFIG_AMCC_DEF_ENV_POWERPC \
413 CONFIG_AMCC_DEF_ENV_PPC_OLD \
414 CONFIG_AMCC_DEF_ENV_NOR_UPD \
415 CONFIG_AMCC_DEF_ENV_NAND_UPD \
Stefan Roese566806c2007-10-05 17:11:30 +0200416 "logversion=2\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200417 "kernel_addr=fc000000\0" \
Stefan Roese64e541f2008-04-11 07:02:29 +0200418 "fdt_addr=fc1e0000\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200419 "ramdisk_addr=fc200000\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200420 "pciconfighost=1\0" \
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200421 "pcie_mode=RP:RP\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200422 ""
Stefan Roese566806c2007-10-05 17:11:30 +0200423
424/*
Stefan Roese490f2042008-06-06 15:55:03 +0200425 * Commands additional to the ones defined in amcc-common.h
Stefan Roese566806c2007-10-05 17:11:30 +0200426 */
Stefan Roese566806c2007-10-05 17:11:30 +0200427#define CONFIG_CMD_DATE
Stefan Roese566806c2007-10-05 17:11:30 +0200428#define CONFIG_CMD_LOG
Stefan Roese566806c2007-10-05 17:11:30 +0200429#define CONFIG_CMD_NAND
Stefan Roese566806c2007-10-05 17:11:30 +0200430#define CONFIG_CMD_PCI
Stefan Roeseafe9fa52007-10-22 16:24:44 +0200431#define CONFIG_CMD_SNTP
Stefan Roese566806c2007-10-05 17:11:30 +0200432
Stefan Roesedd7c3022009-04-15 14:08:48 +0200433/*
434 * Don't run the memory POST on the NAND-booting version. It will
435 * overwrite part of the U-Boot image which is already loaded from NAND
436 * to SDRAM.
437 */
438#if defined(CONFIG_NAND_U_BOOT)
439#define CONFIG_SYS_POST_MEMORY_ON 0
440#else
441#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
442#endif
443
Stefan Roese566806c2007-10-05 17:11:30 +0200444/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
446 CONFIG_SYS_POST_CPU | \
447 CONFIG_SYS_POST_ETHER | \
448 CONFIG_SYS_POST_I2C | \
Stefan Roesedd7c3022009-04-15 14:08:48 +0200449 CONFIG_SYS_POST_MEMORY_ON | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450 CONFIG_SYS_POST_UART)
Stefan Roese566806c2007-10-05 17:11:30 +0200451
452/* Define here the base-addresses of the UARTs to test in POST */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE}
Stefan Roese566806c2007-10-05 17:11:30 +0200454
455#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
Stefan Roese566806c2007-10-05 17:11:30 +0200457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Stefan Roese566806c2007-10-05 17:11:30 +0200459
Stefan Roese566806c2007-10-05 17:11:30 +0200460/*-----------------------------------------------------------------------
461 * PCI stuff
462 *----------------------------------------------------------------------*/
463#define CONFIG_PCI /* include pci support */
464#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
465#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
466#define CONFIG_PCI_CONFIG_HOST_BRIDGE
467
468/*-----------------------------------------------------------------------
469 * PCIe stuff
470 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
472#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
Stefan Roese566806c2007-10-05 17:11:30 +0200473
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */
475#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */
476#define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
Stefan Roese566806c2007-10-05 17:11:30 +0200477
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */
479#define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */
480#define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
Stefan Roese566806c2007-10-05 17:11:30 +0200481
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
483#define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
Stefan Roese566806c2007-10-05 17:11:30 +0200484
485/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
Stefan Roese566806c2007-10-05 17:11:30 +0200487
Stefan Roese566806c2007-10-05 17:11:30 +0200488/*-----------------------------------------------------------------------
Stefan Roese566806c2007-10-05 17:11:30 +0200489 * External Bus Controller (EBC) Setup
490 *----------------------------------------------------------------------*/
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100491#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
492/* booting from NAND, so NAND chips select has to be on CS 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100494
495/* Memory Bank 1 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_EBC_PB1AP 0x05806500
497#define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100498
499/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_EBC_PB0AP 0x018003c0
501#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100502#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */
Stefan Roese566806c2007-10-05 17:11:30 +0200504
505/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_EBC_PB0AP 0x05806500
507#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
Stefan Roese566806c2007-10-05 17:11:30 +0200508
509/* Memory Bank 1 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_EBC_PB1AP 0x018003c0
511#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100512#endif
Stefan Roese566806c2007-10-05 17:11:30 +0200513
514/* Memory Bank 2 (FPGA) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_EBC_PB2AP 0x9400C800
516#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000)
Stefan Roese566806c2007-10-05 17:11:30 +0200517
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */
Stefan Roese566806c2007-10-05 17:11:30 +0200519
520/*-----------------------------------------------------------------------
Stefan Roese566806c2007-10-05 17:11:30 +0200521 * GPIO Setup
522 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100524{ \
525/* GPIO Core 0 */ \
526{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
527{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
528{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
529{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
530{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
531{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
532{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
533{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
Stefan Roese8be76092007-11-27 11:57:35 +0100534{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
535{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
536{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100537{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
538{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
539{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100540{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
541{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100542{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
Stefan Roese8be76092007-11-27 11:57:35 +0100543{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100544{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
545{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
546{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
547{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
548{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
549{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
550{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
551{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
552{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
553{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
554{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \
Stefan Roese8be76092007-11-27 11:57:35 +0100555{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
556{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
557{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100558} \
559}
Stefan Roese566806c2007-10-05 17:11:30 +0200560
Stefan Roese566806c2007-10-05 17:11:30 +0200561/*-----------------------------------------------------------------------
562 * Some Kilauea stuff..., mainly fpga registers
563 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE
565#define CONFIG_SYS_FPGA_FIFO_BASE (in32(CONFIG_SYS_FPGA_BASE) | (1 << 10))
Stefan Roese566806c2007-10-05 17:11:30 +0200566
567/* interrupt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000
569#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT 0x40000000
570#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT 0x20000000
571#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT 0x10000000
572#define CONFIG_SYS_FPGA_PHY0_INT 0x08000000
573#define CONFIG_SYS_FPGA_PHY1_INT 0x04000000
574#define CONFIG_SYS_FPGA_SLIC0_INT 0x02000000
575#define CONFIG_SYS_FPGA_SLIC1_INT 0x01000000
Stefan Roese566806c2007-10-05 17:11:30 +0200576
577/* DPRAM setting */
578/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */
580#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */
581#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE 0x00080000
582#define CONFIG_SYS_FPGA_DPRAM_RST 0x00040000
583#define CONFIG_SYS_FPGA_UART0_FO 0x00020000
584#define CONFIG_SYS_FPGA_UART1_FO 0x00010000
Stefan Roese566806c2007-10-05 17:11:30 +0200585
586/* loopback */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200587#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK 0x00004000
588#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK 0x00008000
589#define CONFIG_SYS_FPGA_SLIC0_ENABLE 0x00002000
590#define CONFIG_SYS_FPGA_SLIC1_ENABLE 0x00001000
591#define CONFIG_SYS_FPGA_SLIC0_CS 0x00000800
592#define CONFIG_SYS_FPGA_SLIC1_CS 0x00000400
593#define CONFIG_SYS_FPGA_USER_LED0 0x00000200
594#define CONFIG_SYS_FPGA_USER_LED1 0x00000100
Stefan Roese566806c2007-10-05 17:11:30 +0200595
Stefan Roese837c7302007-10-21 14:26:29 +0200596#endif /* __CONFIG_H */