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wdenk138ff602004-12-16 15:52:40 +00001/*
Detlev Zundele979e852009-03-30 00:31:35 +02002 * (C) Copyright 2009
3 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
4 *
wdenk414eec32005-04-02 22:37:54 +00005 * (C) Copyright 2003-2005
wdenk138ff602004-12-16 15:52:40 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk138ff602004-12-16 15:52:40 +00009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090019#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
20#define CONFIG_INKA4X0 1 /* INKA4x0 board */
wdenk138ff602004-12-16 15:52:40 +000021
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022/*
23 * Valid values for CONFIG_SYS_TEXT_BASE are:
24 * 0xFFE00000 boot low
25 * 0x00100000 boot from RAM (for testing only)
26 */
27#ifndef CONFIG_SYS_TEXT_BASE
28#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
29#endif
Wolfgang Denk2ced53e2010-11-28 21:18:58 +010030#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenk138ff602004-12-16 15:52:40 +000033
wdenk151ab832005-02-24 22:44:16 +000034#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
35
Becky Bruce31d82672008-05-08 19:02:12 -050036#define CONFIG_HIGH_BATS 1 /* High BATs supported */
37
wdenk138ff602004-12-16 15:52:40 +000038/*
39 * Serial console configuration
40 */
wdenk151ab832005-02-24 22:44:16 +000041#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
42#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk138ff602004-12-16 15:52:40 +000044
45/*
wdenk436be292005-01-31 22:09:11 +000046 * PCI Mapping:
47 * 0x40000000 - 0x4fffffff - PCI Memory
48 * 0x50000000 - 0x50ffffff - PCI IO Space
49 */
50#define CONFIG_PCI 1
51#define CONFIG_PCI_PNP 1
52#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050053#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenk436be292005-01-31 22:09:11 +000054
55#define CONFIG_PCI_MEM_BUS 0x40000000
56#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57#define CONFIG_PCI_MEM_SIZE 0x10000000
58
59#define CONFIG_PCI_IO_BUS 0x50000000
60#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61#define CONFIG_PCI_IO_SIZE 0x01000000
62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_XLB_PIPELINING 1
wdenk436be292005-01-31 22:09:11 +000064
65/* Partitions */
66#define CONFIG_MAC_PARTITION
67#define CONFIG_DOS_PARTITION
68#define CONFIG_ISO_PARTITION
69
wdenk138ff602004-12-16 15:52:40 +000070
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050071/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050072 * BOOTP options
73 */
74#define CONFIG_BOOTP_BOOTFILESIZE
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_GATEWAY
77#define CONFIG_BOOTP_HOSTNAME
78
79
80/*
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050081 * Command line configuration.
82 */
83#include <config_cmd_default.h>
84
Detlev Zundele979e852009-03-30 00:31:35 +020085#define CONFIG_CMD_DATE
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050086#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_EXT2
88#define CONFIG_CMD_FAT
89#define CONFIG_CMD_IDE
90#define CONFIG_CMD_NFS
91#define CONFIG_CMD_PCI
Detlev Zundele979e852009-03-30 00:31:35 +020092#define CONFIG_CMD_PING
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050093#define CONFIG_CMD_SNTP
94#define CONFIG_CMD_USB
95
wdenkb05dcb52005-03-04 11:27:31 +000096#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
97
Wolfgang Denk14d0a022010-10-07 21:51:12 +020098#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099# define CONFIG_SYS_LOWBOOT 1
wdenk138ff602004-12-16 15:52:40 +0000100#endif
101
102/*
103 * Autobooting
104 */
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100105#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
wdenk138ff602004-12-16 15:52:40 +0000106
107#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100108 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk138ff602004-12-16 15:52:40 +0000109 "echo"
110
111#undef CONFIG_BOOTARGS
112
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100113#define CONFIG_ETHADDR 00:a0:a4:03:00:00
114#define CONFIG_OVERWRITE_ETHADDR_ONCE
115
116#define CONFIG_IPADDR 192.168.100.2
117#define CONFIG_SERVERIP 192.168.100.1
118#define CONFIG_NETMASK 255.255.255.0
119#define HOSTNAME inka4x0
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000120#define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000121#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100122
wdenk138ff602004-12-16 15:52:40 +0000123#define CONFIG_EXTRA_ENV_SETTINGS \
124 "netdev=eth0\0" \
125 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100126 "nfsroot=${serverip}:${rootpath}\0" \
wdenk138ff602004-12-16 15:52:40 +0000127 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100128 "addip=setenv bootargs ${bootargs} " \
129 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
130 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100131 "addcons=setenv bootargs ${bootargs} " \
132 "console=ttyS0,${baudrate}\0" \
133 "flash_nfs=run nfsargs addip addcons;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100134 "bootm ${kernel_addr}\0" \
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100135 "net_nfs=tftp 200000 ${bootfile};" \
136 "run nfsargs addip addcons;bootm\0" \
137 "enable_disp=mw.l 100000 04000000 1;" \
138 "cp.l 100000 f0000b20 1;" \
139 "cp.l 100000 f0000b28 1\0" \
140 "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
141 "ide_boot=ext2load ide 0:1 200000 uImage;" \
Marian Balakowiczf23cb342007-11-15 13:24:43 +0100142 "run ideargs addip addcons enable_disp;bootm\0" \
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100143 "brightness=255\0" \
wdenk138ff602004-12-16 15:52:40 +0000144 ""
145
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100146#define CONFIG_BOOTCOMMAND "run ide_boot"
wdenk138ff602004-12-16 15:52:40 +0000147
148/*
149 * IPB Bus clocking configuration.
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenk138ff602004-12-16 15:52:40 +0000152
153/*
154 * Flash configuration
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200157#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_BASE 0xffe00000
159#define CONFIG_SYS_FLASH_SIZE 0x00200000
160#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
161#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
162#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
163#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
wdenk138ff602004-12-16 15:52:40 +0000164
165/*
166 * Environment settings
167 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200168#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200170#define CONFIG_ENV_SIZE 0x2000
171#define CONFIG_ENV_SECT_SIZE 0x2000
wdenk138ff602004-12-16 15:52:40 +0000172#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk138ff602004-12-16 15:52:40 +0000174
175/*
176 * Memory map
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MBAR 0xF0000000
179#define CONFIG_SYS_SDRAM_BASE 0x00000000
180#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenk138ff602004-12-16 15:52:40 +0000181
Marian Balakowicz5fb6d712007-11-15 13:29:55 +0100182/*
183 * SDRAM controller configuration
184 */
185#undef CONFIG_SDR_MT48LC16M16A2
186#undef CONFIG_DDR_MT46V16M16
187#undef CONFIG_DDR_MT46V32M16
188#undef CONFIG_DDR_HYB25D512160BF
189#define CONFIG_DDR_K4H511638C
wdenk138ff602004-12-16 15:52:40 +0000190
191/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Michael Zaidman800eb092010-09-20 08:51:53 +0200193
wdenk138ff602004-12-16 15:52:40 +0000194/* preserve space for the post_word at end of on-chip SRAM */
Michael Zaidman800eb092010-09-20 08:51:53 +0200195#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
196
197#ifdef CONFIG_POST
Wolfgang Denk553f0982010-10-26 13:32:32 +0200198#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
wdenk138ff602004-12-16 15:52:40 +0000199#else
Wolfgang Denk553f0982010-10-26 13:32:32 +0200200#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
wdenk138ff602004-12-16 15:52:40 +0000201#endif
202
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200203#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk138ff602004-12-16 15:52:40 +0000205
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200206#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
208# define CONFIG_SYS_RAMBOOT 1
wdenk138ff602004-12-16 15:52:40 +0000209#endif
210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
212#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
213#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk138ff602004-12-16 15:52:40 +0000214
215/*
216 * Ethernet configuration
217 */
218#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800219#define CONFIG_MPC5xxx_FEC_MII100
wdenk138ff602004-12-16 15:52:40 +0000220/*
Ben Warren86321fc2009-02-05 23:58:25 -0800221 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
wdenk138ff602004-12-16 15:52:40 +0000222 */
Ben Warren86321fc2009-02-05 23:58:25 -0800223/* #define CONFIG_MPC5xxx_FEC_MII10 */
wdenk138ff602004-12-16 15:52:40 +0000224#define CONFIG_PHY_ADDR 0x00
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100225#define CONFIG_MII
wdenk138ff602004-12-16 15:52:40 +0000226
227/*
228 * GPIO configuration
229 *
wdenk9f709b62005-04-22 15:09:09 +0000230 * use CS1 as gpio_wkup_6 output
231 * Bit 0 (mask: 0x80000000): 0
wdenk138ff602004-12-16 15:52:40 +0000232 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
233 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
234 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
235 * EEPROM
236 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
Detlev Zundele979e852009-03-30 00:31:35 +0200237 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
238 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
239 * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101
wdenk138ff602004-12-16 15:52:40 +0000240 */
Detlev Zundele979e852009-03-30 00:31:35 +0200241#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
wdenk138ff602004-12-16 15:52:40 +0000242
243/*
244 * RTC configuration
245 */
Detlev Zundele979e852009-03-30 00:31:35 +0200246#define CONFIG_RTC_RTC4543 1 /* use external RTC */
247
248/*
249 * Software (bit-bang) three wire serial configuration
250 *
251 * Note that we need the ifdefs because otherwise compilation of
252 * mkimage.c fails.
253 */
254#define CONFIG_SOFT_TWS 1
255
256#ifdef TWS_IMPLEMENTATION
257#include <mpc5xxx.h>
258#include <asm/io.h>
259
260#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
261#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
262#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
263#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
264
265static inline void tws_ce(unsigned bit)
266{
267 struct mpc5xxx_wu_gpio *wu_gpio =
268 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
269 if (bit)
270 setbits_8(&wu_gpio->dvo, TWS_CE);
271 else
272 clrbits_8(&wu_gpio->dvo, TWS_CE);
273}
274
275static inline void tws_wr(unsigned bit)
276{
277 struct mpc5xxx_wu_gpio *wu_gpio =
278 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
279 if (bit)
280 setbits_8(&wu_gpio->dvo, TWS_WR);
281 else
282 clrbits_8(&wu_gpio->dvo, TWS_WR);
283}
284
285static inline void tws_clk(unsigned bit)
286{
287 struct mpc5xxx_gpio *gpio =
288 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
289 if (bit)
290 setbits_8(&gpio->sint_dvo, TWS_CLK);
291 else
292 clrbits_8(&gpio->sint_dvo, TWS_CLK);
293}
294
295static inline void tws_data(unsigned bit)
296{
297 struct mpc5xxx_gpio *gpio =
298 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
299 if (bit)
300 setbits_8(&gpio->sint_dvo, TWS_DATA);
301 else
302 clrbits_8(&gpio->sint_dvo, TWS_DATA);
303}
304
305static inline unsigned tws_data_read(void)
306{
307 struct mpc5xxx_gpio *gpio =
308 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
309 return !!(in_8(&gpio->sint_ival) & TWS_DATA);
310}
311
312static inline void tws_data_config_output(unsigned output)
313{
314 struct mpc5xxx_gpio *gpio =
315 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
316 if (output)
317 setbits_8(&gpio->sint_ddr, TWS_DATA);
318 else
319 clrbits_8(&gpio->sint_ddr, TWS_DATA);
320}
321#endif /* TWS_IMPLEMENTATION */
wdenk138ff602004-12-16 15:52:40 +0000322
323/*
324 * Miscellaneous configurable options
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -0500327#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk138ff602004-12-16 15:52:40 +0000329#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk138ff602004-12-16 15:52:40 +0000331#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
333#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
334#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk138ff602004-12-16 15:52:40 +0000335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -0500337#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -0500339#endif
340
wdenk138ff602004-12-16 15:52:40 +0000341/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_ALT_MEMTEST
wdenk138ff602004-12-16 15:52:40 +0000343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
345#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk138ff602004-12-16 15:52:40 +0000346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk138ff602004-12-16 15:52:40 +0000348
wdenk138ff602004-12-16 15:52:40 +0000349/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500350 * Enable loopw command.
wdenk138ff602004-12-16 15:52:40 +0000351 */
352#define CONFIG_LOOPW
353
354/*
355 * Various low-level settings
356 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
358#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenk138ff602004-12-16 15:52:40 +0000359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
361#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
362#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
363#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
364#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenk138ff602004-12-16 15:52:40 +0000365
wdenke58cf2a2005-02-27 23:46:58 +0000366/* 32Mbit SRAM @0x30000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_CS1_START 0x30000000
368#define CONFIG_SYS_CS1_SIZE 0x00400000
369#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
wdenke58cf2a2005-02-27 23:46:58 +0000370
371/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_CS2_START 0x80000000
373#define CONFIG_SYS_CS2_SIZE 0x0001000
374#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
wdenke58cf2a2005-02-27 23:46:58 +0000375
wdenkf4733a02005-03-06 01:21:30 +0000376/* GPIO in @0x30400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_CS3_START 0x30400000
378#define CONFIG_SYS_CS3_SIZE 0x00100000
379#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
wdenkf4733a02005-03-06 01:21:30 +0000380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_CS_BURST 0x00000000
382#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenk138ff602004-12-16 15:52:40 +0000383
wdenk436be292005-01-31 22:09:11 +0000384/*-----------------------------------------------------------------------
385 * USB stuff
386 *-----------------------------------------------------------------------
387 */
388#define CONFIG_USB_OHCI
wdenk151ab832005-02-24 22:44:16 +0000389#define CONFIG_USB_CLOCK 0x00015555
390#define CONFIG_USB_CONFIG 0x00001000
wdenk1968e612005-02-24 23:23:29 +0000391#define CONFIG_USB_STORAGE
wdenk436be292005-01-31 22:09:11 +0000392
wdenkb05dcb52005-03-04 11:27:31 +0000393/*-----------------------------------------------------------------------
394 * IDE/ATA stuff Supports IDE harddisk
395 *-----------------------------------------------------------------------
396 */
397
398#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
399
400#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
401#undef CONFIG_IDE_LED /* LED for ide not supported */
402
wdenkb05dcb52005-03-04 11:27:31 +0000403#define CONFIG_IDE_PREINIT
404
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
406#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
wdenkb05dcb52005-03-04 11:27:31 +0000407
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
409#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
410#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
411#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
412#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
413#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
wdenkb05dcb52005-03-04 11:27:31 +0000414
415#define CONFIG_ATAPI 1
Wolfgang Denk1806c752005-09-21 10:07:56 +0200416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
wdenkb05dcb52005-03-04 11:27:31 +0000418
wdenk138ff602004-12-16 15:52:40 +0000419#endif /* __CONFIG_H */