blob: 7efe46432a3c77547006aab3357a26edfb75c67b [file] [log] [blame]
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
4 select SPL_BOARD_INIT
5 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Patrick Delaunaybc061342018-07-09 15:17:21 +02008 select SPL_DRIVERS_MISC_SUPPORT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
10 select SPL_GPIO_SUPPORT
11 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tanbfc6bae2018-06-14 18:45:19 +080017 select SPL_DM_RESET
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010018 select SPL_SERIAL_SUPPORT
19 select SPL_SYSCON
Patrice Chotard8c1007a2019-04-30 17:26:22 +020020 select SPL_WATCHDOG_SUPPORT
Patrick Delaunay27a986d2019-04-18 17:32:47 +020021 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
22 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay006ea182019-02-27 17:01:14 +010023 imply SPL_DISPLAY_PRINT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010024 imply SPL_LIBDISK_SUPPORT
25
26config SYS_SOC
27 default "stm32mp"
28
Patrick Delaunayef84ddd2019-04-18 17:32:36 +020029config SYS_MALLOC_LEN
30 default 0x2000000
31
Patrick Delaunay579a3e72019-04-18 17:32:37 +020032config ENV_SIZE
Patrice Chotard1538e1a2019-05-07 18:40:47 +020033 default 0x2000
Patrick Delaunay579a3e72019-04-18 17:32:37 +020034
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010035config TARGET_STM32MP1
36 bool "Support stm32mp1xx"
Patrick Delaunayabf26782019-02-12 11:44:39 +010037 select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
Lokesh Vutlaacf15002018-04-26 18:21:26 +053038 select CPU_V7A
Patrick Delaunayabf26782019-02-12 11:44:39 +010039 select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED
Patrick Delaunay41c79772018-04-16 10:13:24 +020040 select CPU_V7_HAS_VIRT
Patrick Delaunaye81f8d12019-07-02 13:26:07 +020041 select OF_BOARD_SETUP
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010042 select PINCTRL_STM32
Patrick Delaunayd090cba2018-07-09 15:17:20 +020043 select STM32_RCC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010044 select STM32_RESET
Andre Przywara7842b6a2018-04-12 04:24:46 +030045 select SYS_ARCH_TIMER
Patrick Delaunay34199822019-04-18 17:32:45 +020046 imply BOOTCOUNT_LIMIT
Patrick Delaunay27a986d2019-04-18 17:32:47 +020047 imply BOOTSTAGE
Patrick Delaunay34199822019-04-18 17:32:45 +020048 imply CMD_BOOTCOUNT
Patrick Delaunay27a986d2019-04-18 17:32:47 +020049 imply CMD_BOOTSTAGE
Patrick Delaunay67551982019-07-30 19:16:23 +020050 imply PRE_CONSOLE_BUFFER
Patrick Delaunayc50c9282019-07-30 19:16:22 +020051 imply SILENT_CONSOLE
Patrick Delaunayabf26782019-02-12 11:44:39 +010052 imply SYSRESET_PSCI if STM32MP1_TRUSTED
53 imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010054 help
55 target STMicroelectronics SOC STM32MP1 family
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010056 STM32MP157, STM32MP153 or STM32MP151
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010057 STMicroelectronics MPU with core ARMv7
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010058 dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010059
Patrick Delaunayabf26782019-02-12 11:44:39 +010060config STM32MP1_TRUSTED
61 bool "Support trusted boot with TF-A"
62 default y if !SPL
63 select ARM_SMCCC
64 help
65 Say Y here to enable boot with TF-A
66 Trusted boot chain is :
67 BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32
Patrick Delaunay152c84b2019-07-02 13:26:06 +020068 TF-A monitor provides proprietary SMC to manage secure devices
69
70config STM32MP1_OPTEE
71 bool "Support trusted boot with TF-A and OP-TEE"
72 depends on STM32MP1_TRUSTED
73 default n
74 help
75 Say Y here to enable boot with TF-A and OP-TEE
76 Trusted boot chain is :
77 BootRom => TF-A.stm32 (clock & DDR) => OP-TEE => U-Boot.stm32
78 OP-TEE monitor provides ST SMC to access to secure resources
Patrick Delaunayabf26782019-02-12 11:44:39 +010079
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010080config SYS_TEXT_BASE
81 prompt "U-Boot base address"
82 default 0xC0100000
83 help
84 configure the U-Boot base address
85 when DDR driver is used:
86 DDR + 1MB (0xC0100000)
87
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010088config NR_DRAM_BANKS
89 default 1
90
Patrick Delaunay11dfd1a2018-03-20 10:54:54 +010091config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
92 hex "Partition on MMC2 to use to load U-Boot from"
93 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
94 default 1
95 help
96 Partition on the second MMC to load U-Boot from when the MMC is being
97 used in raw mode
98
Patrick Delaunayc60f3b32019-07-05 17:20:15 +020099config STM32_ETZPC
100 bool "STM32 Extended TrustZone Protection"
101 depends on TARGET_STM32MP1
102 default y
103 help
104 Say y to enable STM32 Extended TrustZone Protection
105
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200106config CMD_STM32KEY
107 bool "command stm32key to fuse public key hash"
108 default y
109 depends on CMD_FUSE
110 help
111 fuse public key hash in corresponding fuse used to authenticate
112 binary.
113
Patrick Delaunay67551982019-07-30 19:16:23 +0200114
115config PRE_CON_BUF_ADDR
116 default 0xC02FF000
117
118config PRE_CON_BUF_SZ
119 default 4096
120
Patrick Delaunay27a986d2019-04-18 17:32:47 +0200121config BOOTSTAGE_STASH_ADDR
122 default 0xC3000000
123
Patrick Delaunay34199822019-04-18 17:32:45 +0200124if BOOTCOUNT_LIMIT
125config SYS_BOOTCOUNT_SINGLEWORD
126 default y
127
128# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
129config SYS_BOOTCOUNT_ADDR
130 default 0x5C00A154
131endif
132
Patrick Delaunay320d2662018-05-17 14:50:46 +0200133if DEBUG_UART
134
135config DEBUG_UART_BOARD_INIT
136 default y
137
138# debug on UART4 by default
139config DEBUG_UART_BASE
140 default 0x40010000
141
142# clock source is HSI on reset
143config DEBUG_UART_CLOCK
144 default 64000000
145endif
146
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100147source "board/st/stm32mp1/Kconfig"
148
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100149endif