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Stefan Roese8a316c92005-08-01 16:49:12 +02001/*
Stefan Roese8b395012007-04-29 14:13:01 +02002 * (C) Copyright 2005-2007
Stefan Roese8a316c92005-08-01 16:49:12 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese8a316c92005-08-01 16:49:12 +02006 */
7
8/************************************************************************
9 * bamboo.h - configuration for BAMBOO board
10 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
Stefan Roese17f50f222005-08-04 17:09:16 +020017#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
Stefan Roese846b0dd2005-08-08 12:42:22 +020018#define CONFIG_440EP 1 /* Specific PPC440EP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020019#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese8a316c92005-08-01 16:49:12 +020020#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
21
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#ifndef CONFIG_SYS_TEXT_BASE
23#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
24#endif
25
Stefan Roese490f2042008-06-06 15:55:03 +020026/*
27 * Include common defines/options for all AMCC eval boards
28 */
29#define CONFIG_HOSTNAME bamboo
30#include "amcc-common.h"
31
Stefan Roesec57c7982005-08-11 17:56:56 +020032#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
33
34/*
35 * Please note that, if NAND support is enabled, the 2nd ethernet port
36 * can't be used because of pin multiplexing. So, if you want to use the
37 * 2nd ethernet port you have to "undef" the following define.
38 */
39#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
40
Stefan Roese8a316c92005-08-01 16:49:12 +020041/*-----------------------------------------------------------------------
42 * Base addresses -- Note these are effective addresses where the
43 * actual resources get mapped (not physical addresses)
44 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
46#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
47#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
48#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
49#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese8a316c92005-08-01 16:49:12 +020050
51/*Don't change either of these*/
Stefan Roese550650d2010-09-20 16:05:31 +020052#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
Stefan Roese8a316c92005-08-01 16:49:12 +020053/*Don't change either of these*/
54
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_USB_DEVICE 0x50000000
56#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
57#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
58#define CONFIG_SYS_NAND_ADDR 0x90000000
59#define CONFIG_SYS_NAND2_ADDR 0x94000000
Stefan Roese8a316c92005-08-01 16:49:12 +020060
61/*-----------------------------------------------------------------------
62 * Initial RAM & stack pointer (placed in SDRAM)
63 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
65#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
Wolfgang Denk553f0982010-10-26 13:32:32 +020066#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020067#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese8a316c92005-08-01 16:49:12 +020069
Stefan Roese8a316c92005-08-01 16:49:12 +020070/*-----------------------------------------------------------------------
71 * Serial Port
72 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020073#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
Stefan Roese8a316c92005-08-01 16:49:12 +020075
Stefan Roese8a316c92005-08-01 16:49:12 +020076/*-----------------------------------------------------------------------
77 * NVRAM/RTC
78 *
79 * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
80 * The DS1558 code assumes this condition
81 *
82 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
Stefan Roese17f50f222005-08-04 17:09:16 +020084#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
85
86/*-----------------------------------------------------------------------
87 * Environment
88 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020089#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +020090
91/*-----------------------------------------------------------------------
92 * FLASH related
93 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
95#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Stefan Roese8a316c92005-08-01 16:49:12 +020096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#undef CONFIG_SYS_FLASH_CHECKSUM
98#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
99#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese8a316c92005-08-01 16:49:12 +0200100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_ADDR0 0x555
102#define CONFIG_SYS_FLASH_ADDR1 0x2aa
103#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese17f50f222005-08-04 17:09:16 +0200104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
106#define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
Stefan Roese17f50f222005-08-04 17:09:16 +0200107
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200108#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200109#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200111#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese17f50f222005-08-04 17:09:16 +0200112
Stefan Roese17f50f222005-08-04 17:09:16 +0200113/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200114#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
115#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200116#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese8a316c92005-08-01 16:49:12 +0200117
118/*-----------------------------------------------------------------------
Stefan Roese8b395012007-04-29 14:13:01 +0200119 * NAND FLASH
Stefan Roesec57c7982005-08-11 17:56:56 +0200120 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_MAX_NAND_DEVICE 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
123#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
124#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_NAND_CS 1
Stefan Roesecf959c72007-06-01 15:27:11 +0200126
Stefan Roesec57c7982005-08-11 17:56:56 +0200127/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +0200128 * DDR SDRAM
Stefan Roese17f50f222005-08-04 17:09:16 +0200129 *----------------------------------------------------------------------------- */
130#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
Stefan Roesefd49bf02005-11-15 16:04:58 +0100131#undef CONFIG_DDR_ECC /* don't use ECC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
133#define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
134#define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
Eugene OBriend2f68002007-07-31 10:24:56 +0200135#define CONFIG_PROG_SDRAM_TLB
Stefan Roese8a316c92005-08-01 16:49:12 +0200136
137/*-----------------------------------------------------------------------
138 * I2C
139 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000140#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese8a316c92005-08-01 16:49:12 +0200141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
143#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
144#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
145#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese8a316c92005-08-01 16:49:12 +0200146
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200147#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200148#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
149#define CONFIG_ENV_OFFSET 0x0
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200150#endif /* CONFIG_ENV_IS_IN_EEPROM */
Stefan Roese17f50f222005-08-04 17:09:16 +0200151
Stefan Roese490f2042008-06-06 15:55:03 +0200152/*
153 * Default environment variables
154 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200155#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200156 CONFIG_AMCC_DEF_ENV \
157 CONFIG_AMCC_DEF_ENV_POWERPC \
158 CONFIG_AMCC_DEF_ENV_PPC_OLD \
159 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese17f50f222005-08-04 17:09:16 +0200160 "kernel_addr=fff00000\0" \
161 "ramdisk_addr=fff10000\0" \
Stefan Roese17f50f222005-08-04 17:09:16 +0200162 ""
Stefan Roese8a316c92005-08-01 16:49:12 +0200163
Stefan Roesea00eccf2008-05-08 11:05:15 +0200164#define CONFIG_HAS_ETH0
Stefan Roese17f50f222005-08-04 17:09:16 +0200165#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200166#define CONFIG_PHY1_ADDR 1
Stefan Roesec57c7982005-08-11 17:56:56 +0200167
168#ifndef CONFIG_BAMBOO_NAND
Stefan Roese8a316c92005-08-01 16:49:12 +0200169#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
Stefan Roesec57c7982005-08-11 17:56:56 +0200170#endif /* CONFIG_BAMBOO_NAND */
171
Stefan Roese846b0dd2005-08-08 12:42:22 +0200172#ifdef CONFIG_440EP
Stefan Roese8a316c92005-08-01 16:49:12 +0200173/* USB */
174#define CONFIG_USB_OHCI
175#define CONFIG_USB_STORAGE
176
177/*Comment this out to enable USB 1.1 device*/
178#define USB_2_0_DEVICE
Stefan Roese846b0dd2005-08-08 12:42:22 +0200179#endif /*CONFIG_440EP*/
Stefan Roese8a316c92005-08-01 16:49:12 +0200180
Jon Loeligerba2351f2007-07-04 22:31:49 -0500181/*
Stefan Roese490f2042008-06-06 15:55:03 +0200182 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500183 */
Jon Loeligerba2351f2007-07-04 22:31:49 -0500184#define CONFIG_CMD_DATE
Jon Loeligerba2351f2007-07-04 22:31:49 -0500185#define CONFIG_CMD_EXT2
Stefan Roese490f2042008-06-06 15:55:03 +0200186#define CONFIG_CMD_FAT
187#define CONFIG_CMD_PCI
188#define CONFIG_CMD_SDRAM
Jon Loeligerba2351f2007-07-04 22:31:49 -0500189#define CONFIG_CMD_SNTP
Stefan Roese490f2042008-06-06 15:55:03 +0200190#define CONFIG_CMD_USB
Jon Loeligerba2351f2007-07-04 22:31:49 -0500191
192#ifdef CONFIG_BAMBOO_NAND
193#define CONFIG_CMD_NAND
194#endif
195
Stefan Roese3b6748e2005-10-14 15:37:34 +0200196#define CONFIG_SUPPORT_VFAT
197
Stefan Roese490f2042008-06-06 15:55:03 +0200198/* Partitions */
199#define CONFIG_MAC_PARTITION
200#define CONFIG_DOS_PARTITION
201#define CONFIG_ISO_PARTITION
Stefan Roese193dd952006-07-27 16:14:05 +0200202
Stefan Roese8a316c92005-08-01 16:49:12 +0200203/*-----------------------------------------------------------------------
204 * PCI stuff
205 *-----------------------------------------------------------------------
206 */
207/* General PCI */
Stefan Roesec57c7982005-08-11 17:56:56 +0200208#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000209#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roesec57c7982005-08-11 17:56:56 +0200210#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
Stefan Roese17f50f222005-08-04 17:09:16 +0200211#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
Stefan Roese8a316c92005-08-01 16:49:12 +0200213
214/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_PCI_TARGET_INIT
216#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese8a316c92005-08-01 16:49:12 +0200217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
219#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roese8a316c92005-08-01 16:49:12 +0200220
Stefan Roese8a316c92005-08-01 16:49:12 +0200221#endif /* __CONFIG_H */