blob: 53dd780a6ca2273702ba97c6f856fc7243582e2a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simekd5dae852013-04-22 15:43:02 +02002/*
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
4 *
5 * (C) Copyright 2012
6 * Joe Hershberger <joe.hershberger@ni.com>
Michal Simekd5dae852013-04-22 15:43:02 +02007 */
8
9#include <common.h>
Simon Glass24b852a2015-11-08 23:47:45 -070010#include <console.h>
Simon Glass9edefc22019-11-14 12:57:37 -070011#include <cpu_func.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Simon Glass90526e92020-05-10 11:39:56 -060013#include <asm/cache.h>
Michal Simekd5dae852013-04-22 15:43:02 +020014#include <asm/io.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053015#include <fs.h>
Michal Simekd5dae852013-04-22 15:43:02 +020016#include <zynqpl.h>
Simon Glassc05ed002020-05-10 11:40:11 -060017#include <linux/delay.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040018#include <linux/sizes.h>
Michal Simekd5dae852013-04-22 15:43:02 +020019#include <asm/arch/hardware.h>
20#include <asm/arch/sys_proto.h>
21
22#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
Siva Durga Prasad Paladugu71723aa2018-03-06 17:37:09 +053023#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
Siva Durga Prasad Paladugu37e3a362018-06-26 15:02:19 +053024#define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
Ibai Erkiagac64afba2018-04-05 05:19:27 -070025#define DEVCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00
Michal Simekd5dae852013-04-22 15:43:02 +020026#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
27#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
28#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
29#define DEVCFG_ISR_DMA_DONE 0x00002000
30#define DEVCFG_ISR_PCFG_DONE 0x00000004
31#define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
32#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
33#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
34#define DEVCFG_STATUS_PCFG_INIT 0x00000010
Soren Brinkmann5f932272013-06-14 17:43:24 -070035#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
Michal Simekd5dae852013-04-22 15:43:02 +020036#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
37#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
38
Tom Rini65cc0e22022-11-16 13:10:41 -050039#ifndef CFG_SYS_FPGA_WAIT
40#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
Michal Simekd5dae852013-04-22 15:43:02 +020041#endif
42
43#ifndef CONFIG_SYS_FPGA_PROG_TIME
Michal Simekfd2b10b2013-06-17 13:54:07 +020044#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
Michal Simekd5dae852013-04-22 15:43:02 +020045#endif
46
Michal Simekd5dae852013-04-22 15:43:02 +020047#define DUMMY_WORD 0xffffffff
48
49/* Xilinx binary format header */
50static const u32 bin_format[] = {
51 DUMMY_WORD, /* Dummy words */
52 DUMMY_WORD,
53 DUMMY_WORD,
54 DUMMY_WORD,
55 DUMMY_WORD,
56 DUMMY_WORD,
57 DUMMY_WORD,
58 DUMMY_WORD,
59 0x000000bb, /* Sync word */
60 0x11220044, /* Sync word */
61 DUMMY_WORD,
62 DUMMY_WORD,
63 0xaa995566, /* Sync word */
64};
65
66#define SWAP_NO 1
67#define SWAP_DONE 2
68
69/*
70 * Load the whole word from unaligned buffer
71 * Keep in your mind that it is byte loading on little-endian system
72 */
73static u32 load_word(const void *buf, u32 swap)
74{
75 u32 word = 0;
76 u8 *bitc = (u8 *)buf;
77 int p;
78
79 if (swap == SWAP_NO) {
80 for (p = 0; p < 4; p++) {
81 word <<= 8;
82 word |= bitc[p];
83 }
84 } else {
85 for (p = 3; p >= 0; p--) {
86 word <<= 8;
87 word |= bitc[p];
88 }
89 }
90
91 return word;
92}
93
94static u32 check_header(const void *buf)
95{
96 u32 i, pattern;
97 int swap = SWAP_NO;
98 u32 *test = (u32 *)buf;
99
100 debug("%s: Let's check bitstream header\n", __func__);
101
102 /* Checking that passing bin is not a bitstream */
103 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
104 pattern = load_word(&test[i], swap);
105
106 /*
107 * Bitstreams in binary format are swapped
108 * compare to regular bistream.
109 * Do not swap dummy word but if swap is done assume
110 * that parsing buffer is binary format
111 */
112 if ((__swab32(pattern) != DUMMY_WORD) &&
113 (__swab32(pattern) == bin_format[i])) {
114 pattern = __swab32(pattern);
115 swap = SWAP_DONE;
116 debug("%s: data swapped - let's swap\n", __func__);
117 }
118
119 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
120 (u32)&test[i], pattern, bin_format[i]);
121 if (pattern != bin_format[i]) {
122 debug("%s: Bitstream is not recognized\n", __func__);
123 return 0;
124 }
125 }
126 debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
127 (u32)buf, swap == SWAP_NO ? "without" : "with");
128
129 return swap;
130}
131
132static void *check_data(u8 *buf, size_t bsize, u32 *swap)
133{
134 u32 word, p = 0; /* possition */
135
136 /* Because buf doesn't need to be aligned let's read it by chars */
137 for (p = 0; p < bsize; p++) {
138 word = load_word(&buf[p], SWAP_NO);
139 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
140
141 /* Find the first bitstream dummy word */
142 if (word == DUMMY_WORD) {
143 debug("%s: Found dummy word at position %x/%x\n",
144 __func__, p, (u32)&buf[p]);
145 *swap = check_header(&buf[p]);
146 if (*swap) {
147 /* FIXME add full bitstream checking here */
148 return &buf[p];
149 }
150 }
151 /* Loop can be huge - support CTRL + C */
152 if (ctrlc())
Michal Simek42a74a02014-04-25 13:51:58 +0200153 return NULL;
Michal Simekd5dae852013-04-22 15:43:02 +0200154 }
Michal Simek42a74a02014-04-25 13:51:58 +0200155 return NULL;
Michal Simekd5dae852013-04-22 15:43:02 +0200156}
157
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530158static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
Michal Simekd5dae852013-04-22 15:43:02 +0200159{
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530160 unsigned long ts;
161 u32 isr_status;
Michal Simekd5dae852013-04-22 15:43:02 +0200162
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530163 /* Set up the transfer */
164 writel((u32)srcbuf, &devcfg_base->dma_src_addr);
165 writel(dstbuf, &devcfg_base->dma_dst_addr);
166 writel(srclen, &devcfg_base->dma_src_len);
167 writel(dstlen, &devcfg_base->dma_dst_len);
Michal Simekd5dae852013-04-22 15:43:02 +0200168
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530169 isr_status = readl(&devcfg_base->int_sts);
Michal Simekd5dae852013-04-22 15:43:02 +0200170
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530171 /* Polling the PCAP_INIT status for Set */
172 ts = get_timer(0);
173 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
174 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
175 debug("%s: Error: isr = 0x%08X\n", __func__,
176 isr_status);
177 debug("%s: Write count = 0x%08X\n", __func__,
178 readl(&devcfg_base->write_count));
179 debug("%s: Read count = 0x%08X\n", __func__,
180 readl(&devcfg_base->read_count));
Michal Simekd5dae852013-04-22 15:43:02 +0200181
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530182 return FPGA_FAIL;
Novasys Ingenieriec83a35f2013-11-27 09:03:01 +0100183 }
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530184 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
185 printf("%s: Timeout wait for DMA to complete\n",
186 __func__);
187 return FPGA_FAIL;
188 }
189 isr_status = readl(&devcfg_base->int_sts);
Michal Simekd5dae852013-04-22 15:43:02 +0200190 }
191
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530192 debug("%s: DMA transfer is done\n", __func__);
193
194 /* Clear out the DMA status */
195 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
196
197 return FPGA_SUCCESS;
198}
199
Michal Simek5b815c92014-05-02 14:15:27 +0200200static int zynq_dma_xfer_init(bitstream_type bstype)
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530201{
202 u32 status, control, isr_status;
203 unsigned long ts;
204
Soren Brinkmann5f932272013-06-14 17:43:24 -0700205 /* Clear loopback bit */
206 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
207
Siva Durga Prasad Paladugu3427f4d2015-12-09 18:46:43 +0530208 if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
Michal Simekd5dae852013-04-22 15:43:02 +0200209 zynq_slcr_devcfg_disable();
210
211 /* Setting PCFG_PROG_B signal to high */
212 control = readl(&devcfg_base->ctrl);
213 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
Siva Durga Prasad Paladugu71723aa2018-03-06 17:37:09 +0530214
215 /*
216 * Delay is required if AES efuse is selected as
217 * key source.
218 */
219 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
220 mdelay(5);
221
Michal Simekd5dae852013-04-22 15:43:02 +0200222 /* Setting PCFG_PROG_B signal to low */
223 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
224
Siva Durga Prasad Paladugu71723aa2018-03-06 17:37:09 +0530225 /*
226 * Delay is required if AES efuse is selected as
227 * key source.
228 */
229 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
230 mdelay(5);
231
Michal Simekd5dae852013-04-22 15:43:02 +0200232 /* Polling the PCAP_INIT status for Reset */
233 ts = get_timer(0);
234 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
Tom Rini65cc0e22022-11-16 13:10:41 -0500235 if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
Michal Simekd5dae852013-04-22 15:43:02 +0200236 printf("%s: Timeout wait for INIT to clear\n",
237 __func__);
238 return FPGA_FAIL;
239 }
240 }
241
242 /* Setting PCFG_PROG_B signal to high */
243 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
244
245 /* Polling the PCAP_INIT status for Set */
246 ts = get_timer(0);
247 while (!(readl(&devcfg_base->status) &
248 DEVCFG_STATUS_PCFG_INIT)) {
Tom Rini65cc0e22022-11-16 13:10:41 -0500249 if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
Michal Simekd5dae852013-04-22 15:43:02 +0200250 printf("%s: Timeout wait for INIT to set\n",
251 __func__);
252 return FPGA_FAIL;
253 }
254 }
255 }
256
257 isr_status = readl(&devcfg_base->int_sts);
258
259 /* Clear it all, so if Boot ROM comes back, it can proceed */
260 writel(0xFFFFFFFF, &devcfg_base->int_sts);
261
262 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
263 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
264
265 /* If RX FIFO overflow, need to flush RX FIFO first */
266 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
267 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
268 writel(0xFFFFFFFF, &devcfg_base->int_sts);
269 }
270 return FPGA_FAIL;
271 }
272
273 status = readl(&devcfg_base->status);
274
275 debug("%s: Status = 0x%08X\n", __func__, status);
276
277 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
278 debug("%s: Error: device busy\n", __func__);
279 return FPGA_FAIL;
280 }
281
282 debug("%s: Device ready\n", __func__);
283
284 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
285 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
286 /* Error state, transfer cannot occur */
287 debug("%s: ISR indicates error\n", __func__);
288 return FPGA_FAIL;
289 } else {
290 /* Clear out the status */
291 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
292 }
293 }
294
295 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
296 /* Clear the count of completed DMA transfers */
297 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
298 }
299
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530300 return FPGA_SUCCESS;
301}
302
303static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
304{
305 u32 *new_buf;
306 u32 i;
307
308 if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
309 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
310
311 /*
312 * This might be dangerous but permits to flash if
313 * ARCH_DMA_MINALIGN is greater than header size
314 */
315 if (new_buf > buf) {
316 debug("%s: Aligned buffer is after buffer start\n",
317 __func__);
Michael Walle8c02d842021-02-10 22:42:29 +0100318 new_buf = (u32 *)((u32)new_buf - ARCH_DMA_MINALIGN);
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530319 }
320 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
321 (u32)buf, (u32)new_buf, swap);
322
323 for (i = 0; i < (len/4); i++)
324 new_buf[i] = load_word(&buf[i], swap);
325
326 buf = new_buf;
327 } else if (swap != SWAP_DONE) {
328 /* For bitstream which are aligned */
329 u32 *new_buf = (u32 *)buf;
330
331 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
332 swap);
333
334 for (i = 0; i < (len/4); i++)
335 new_buf[i] = load_word(&buf[i], swap);
336 }
337
338 return buf;
339}
340
Siva Durga Prasad Paladugu31081852014-03-13 11:57:34 +0530341static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
342 size_t bsize, u32 blocksize, u32 *swap,
Michal Simek5b815c92014-05-02 14:15:27 +0200343 bitstream_type *bstype)
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530344{
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530345 u32 *buf_start;
Siva Durga Prasad Paladugu31081852014-03-13 11:57:34 +0530346 u32 diff;
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530347
Siva Durga Prasad Paladugu31081852014-03-13 11:57:34 +0530348 buf_start = check_data((u8 *)buf, blocksize, swap);
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530349
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530350 if (!buf_start)
351 return FPGA_FAIL;
352
353 /* Check if data is postpone from start */
354 diff = (u32)buf_start - (u32)buf;
355 if (diff) {
356 printf("%s: Bitstream is not validated yet (diff %x)\n",
357 __func__, diff);
358 return FPGA_FAIL;
359 }
360
361 if ((u32)buf < SZ_1M) {
362 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
363 __func__, (u32)buf);
364 return FPGA_FAIL;
365 }
366
Michal Simek5b815c92014-05-02 14:15:27 +0200367 if (zynq_dma_xfer_init(*bstype))
Siva Durga Prasad Paladugu31081852014-03-13 11:57:34 +0530368 return FPGA_FAIL;
369
370 return 0;
371}
372
Michal Simek7a78bd22014-05-02 14:09:30 +0200373static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
Oleksandr Suvorov3e784812022-07-22 17:16:10 +0300374 bitstream_type bstype, int flags)
Siva Durga Prasad Paladugu31081852014-03-13 11:57:34 +0530375{
376 unsigned long ts; /* Timestamp */
Siva Durga Prasad Paladugu31081852014-03-13 11:57:34 +0530377 u32 isr_status, swap;
378
379 /*
380 * send bsize inplace of blocksize as it was not a bitstream
381 * in chunks
382 */
383 if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
Michal Simek5b815c92014-05-02 14:15:27 +0200384 &bstype))
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530385 return FPGA_FAIL;
386
387 buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
388
Michal Simekd5dae852013-04-22 15:43:02 +0200389 debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
390 debug("%s: Size = %zu\n", __func__, bsize);
391
Jagannadha Sutradharudu Tekiec4b73f2013-09-20 18:39:47 +0530392 /* flush(clean & invalidate) d-cache range buf */
393 flush_dcache_range((u32)buf, (u32)buf +
394 roundup(bsize, ARCH_DMA_MINALIGN));
395
Siva Durga Prasad Paladugua0735a32014-03-12 17:09:26 +0530396 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
397 return FPGA_FAIL;
Michal Simekd5dae852013-04-22 15:43:02 +0200398
399 isr_status = readl(&devcfg_base->int_sts);
Michal Simekd5dae852013-04-22 15:43:02 +0200400 /* Check FPGA configuration completion */
401 ts = get_timer(0);
402 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
Tom Rini65cc0e22022-11-16 13:10:41 -0500403 if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
Michal Simekd5dae852013-04-22 15:43:02 +0200404 printf("%s: Timeout wait for FPGA to config\n",
405 __func__);
406 return FPGA_FAIL;
407 }
408 isr_status = readl(&devcfg_base->int_sts);
409 }
410
411 debug("%s: FPGA config done\n", __func__);
412
Michal Simek5b815c92014-05-02 14:15:27 +0200413 if (bstype != BIT_PARTIAL)
Michal Simekd5dae852013-04-22 15:43:02 +0200414 zynq_slcr_devcfg_enable();
415
Stefan Herbrechtsmeier7a0bc182022-08-08 16:53:31 +0200416 if (!IS_ENABLED(CONFIG_SPL_BUILD))
417 puts("INFO:post config was not run, please run manually if needed\n");
Siva Durga Prasad Paladugu31f7ce72019-03-23 16:01:36 +0530418
Michal Simekd5dae852013-04-22 15:43:02 +0200419 return FPGA_SUCCESS;
420}
421
Luis Aranedad600c4f2018-07-19 03:10:17 -0400422#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530423static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
424 fpga_fs_info *fsinfo)
425{
426 unsigned long ts; /* Timestamp */
427 u32 isr_status, swap;
428 u32 partialbit = 0;
Suriyan Ramasamid455d872014-11-17 14:39:38 -0800429 loff_t blocksize, actread;
430 loff_t pos = 0;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530431 int fstype;
Tien Fong Chee3003c442019-02-15 15:57:07 +0800432 char *interface, *dev_part;
433 const char *filename;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530434
435 blocksize = fsinfo->blocksize;
436 interface = fsinfo->interface;
437 dev_part = fsinfo->dev_part;
438 filename = fsinfo->filename;
439 fstype = fsinfo->fstype;
440
441 if (fs_set_blk_dev(interface, dev_part, fstype))
442 return FPGA_FAIL;
443
Suriyan Ramasamid455d872014-11-17 14:39:38 -0800444 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530445 return FPGA_FAIL;
446
447 if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
448 &partialbit))
449 return FPGA_FAIL;
450
451 dcache_disable();
452
453 do {
454 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
455
456 if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
457 0xffffffff, 0))
458 return FPGA_FAIL;
459
460 bsize -= blocksize;
461 pos += blocksize;
462
463 if (fs_set_blk_dev(interface, dev_part, fstype))
464 return FPGA_FAIL;
465
466 if (bsize > blocksize) {
Suriyan Ramasamid455d872014-11-17 14:39:38 -0800467 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530468 return FPGA_FAIL;
469 } else {
Suriyan Ramasamid455d872014-11-17 14:39:38 -0800470 if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530471 return FPGA_FAIL;
472 }
473 } while (bsize > blocksize);
474
475 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
476
477 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
478 return FPGA_FAIL;
479
480 dcache_enable();
481
482 isr_status = readl(&devcfg_base->int_sts);
483
484 /* Check FPGA configuration completion */
485 ts = get_timer(0);
486 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
Tom Rini65cc0e22022-11-16 13:10:41 -0500487 if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530488 printf("%s: Timeout wait for FPGA to config\n",
489 __func__);
490 return FPGA_FAIL;
491 }
492 isr_status = readl(&devcfg_base->int_sts);
493 }
494
495 debug("%s: FPGA config done\n", __func__);
496
497 if (!partialbit)
498 zynq_slcr_devcfg_enable();
499
500 return FPGA_SUCCESS;
501}
502#endif
503
Michal Simek14cfc4f2014-03-13 13:07:57 +0100504struct xilinx_fpga_op zynq_op = {
505 .load = zynq_load,
Luis Aranedad600c4f2018-07-19 03:10:17 -0400506#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530507 .loadfs = zynq_loadfs,
508#endif
Michal Simek14cfc4f2014-03-13 13:07:57 +0100509};
Siva Durga Prasad Paladugu37e3a362018-06-26 15:02:19 +0530510
511#ifdef CONFIG_CMD_ZYNQ_AES
512/*
513 * Load the encrypted image from src addr and decrypt the image and
514 * place it back the decrypted image into dstaddr.
515 */
Siva Durga Prasad Paladugu3427f4d2015-12-09 18:46:43 +0530516int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
517 u8 bstype)
Siva Durga Prasad Paladugu37e3a362018-06-26 15:02:19 +0530518{
T Karthik Reddy1d9632a2019-03-12 20:20:20 +0530519 u32 isr_status, ts;
520
Siva Durga Prasad Paladugu37e3a362018-06-26 15:02:19 +0530521 if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
522 printf("%s: src and dst addr should be > 1M\n",
523 __func__);
524 return FPGA_FAIL;
525 }
526
Ibai Erkiagac64afba2018-04-05 05:19:27 -0700527 /* Check AES engine is enabled */
528 if (!(readl(&devcfg_base->ctrl) &
529 DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
530 printf("%s: AES engine is not enabled\n", __func__);
531 return FPGA_FAIL;
532 }
533
Siva Durga Prasad Paladugu3427f4d2015-12-09 18:46:43 +0530534 if (zynq_dma_xfer_init(bstype)) {
Siva Durga Prasad Paladugu37e3a362018-06-26 15:02:19 +0530535 printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
536 return FPGA_FAIL;
537 }
538
539 writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
540 &devcfg_base->ctrl);
541
542 debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
543 debug("%s: Size = %zu\n", __func__, srclen);
544
545 /* flush(clean & invalidate) d-cache range buf */
546 flush_dcache_range((u32)srcaddr, (u32)srcaddr +
547 roundup(srclen << 2, ARCH_DMA_MINALIGN));
548 /*
549 * Flush destination address range only if image is not
550 * bitstream.
551 */
T Karthik Reddyca0c0e02019-03-12 20:20:23 +0530552 if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
553 flush_dcache_range((u32)dstaddr, (u32)dstaddr +
554 roundup(dstlen << 2, ARCH_DMA_MINALIGN));
Siva Durga Prasad Paladugu37e3a362018-06-26 15:02:19 +0530555
556 if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
557 return FPGA_FAIL;
558
T Karthik Reddy1d9632a2019-03-12 20:20:20 +0530559 if (bstype == BIT_FULL) {
560 isr_status = readl(&devcfg_base->int_sts);
561 /* Check FPGA configuration completion */
562 ts = get_timer(0);
563 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
Tom Rini65cc0e22022-11-16 13:10:41 -0500564 if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
T Karthik Reddy1d9632a2019-03-12 20:20:20 +0530565 printf("%s: Timeout wait for FPGA to config\n",
566 __func__);
567 return FPGA_FAIL;
568 }
569 isr_status = readl(&devcfg_base->int_sts);
570 }
571 printf("%s: FPGA config done\n", __func__);
572 zynq_slcr_devcfg_enable();
573 }
Siva Durga Prasad Paladugu37e3a362018-06-26 15:02:19 +0530574
575 return FPGA_SUCCESS;
576}
577#endif