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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * armboot - Startup Code for XScale
3 *
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
wdenka8c7c702003-12-06 19:49:23 +00007 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
wdenk1cb8e982003-03-06 21:55:29 +00008 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
9 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
wdenka8c7c702003-12-06 19:49:23 +000010 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
wdenkc6097192002-11-03 00:24:07 +000011 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk384ae022002-11-05 00:17:55 +000022 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkc6097192002-11-03 00:24:07 +000023 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
wdenkc6097192002-11-03 00:24:07 +000031#include <config.h>
32#include <version.h>
33
34.globl _start
wdenk384ae022002-11-05 00:17:55 +000035_start: b reset
wdenkc6097192002-11-03 00:24:07 +000036 ldr pc, _undefined_instruction
37 ldr pc, _software_interrupt
38 ldr pc, _prefetch_abort
39 ldr pc, _data_abort
40 ldr pc, _not_used
41 ldr pc, _irq
42 ldr pc, _fiq
43
wdenk384ae022002-11-05 00:17:55 +000044_undefined_instruction: .word undefined_instruction
wdenkc6097192002-11-03 00:24:07 +000045_software_interrupt: .word software_interrupt
46_prefetch_abort: .word prefetch_abort
47_data_abort: .word data_abort
48_not_used: .word not_used
49_irq: .word irq
50_fiq: .word fiq
51
52 .balignl 16,0xdeadbeef
53
54
55/*
56 * Startup Code (reset vector)
57 *
wdenka8c7c702003-12-06 19:49:23 +000058 * do important init only if we don't start from RAM!
wdenkc6097192002-11-03 00:24:07 +000059 * - relocate armboot to ram
60 * - setup stack
61 * - jump to second stage
62 */
63
wdenkc6097192002-11-03 00:24:07 +000064_TEXT_BASE:
65 .word TEXT_BASE
66
67.globl _armboot_start
68_armboot_start:
69 .word _start
70
71/*
wdenkf6e20fc2004-02-08 19:38:38 +000072 * These are defined in the board-specific linker script.
wdenk47cd00f2003-03-06 13:39:27 +000073 */
wdenk8bde7f72003-06-27 21:31:46 +000074.globl _bss_start
75_bss_start:
wdenkf6e20fc2004-02-08 19:38:38 +000076 .word __bss_start
wdenk47cd00f2003-03-06 13:39:27 +000077
78.globl _bss_end
79_bss_end:
wdenkf6e20fc2004-02-08 19:38:38 +000080 .word _end
wdenk47cd00f2003-03-06 13:39:27 +000081
wdenkc6097192002-11-03 00:24:07 +000082#ifdef CONFIG_USE_IRQ
83/* IRQ stack memory (calculated at run-time) */
84.globl IRQ_STACK_START
85IRQ_STACK_START:
86 .word 0x0badc0de
87
88/* IRQ stack memory (calculated at run-time) */
89.globl FIQ_STACK_START
90FIQ_STACK_START:
91 .word 0x0badc0de
92#endif
93
94
95/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +000096/* */
97/* the actual reset code */
98/* */
wdenkc6097192002-11-03 00:24:07 +000099/****************************************************************************/
100
101reset:
wdenk384ae022002-11-05 00:17:55 +0000102 mrs r0,cpsr /* set the cpu to SVC32 mode */
103 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
wdenkc6097192002-11-03 00:24:07 +0000104 orr r0,r0,#0x13
105 msr cpsr,r0
106
wdenka8c7c702003-12-06 19:49:23 +0000107 /*
108 * we do sys-critical inits only at reboot,
109 * not when booting from ram!
110 */
wdenk8aa1a2d2005-04-04 12:44:11 +0000111#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenk384ae022002-11-05 00:17:55 +0000112 bl cpu_init_crit /* we do sys-critical inits */
wdenka8c7c702003-12-06 19:49:23 +0000113#endif
wdenkc6097192002-11-03 00:24:07 +0000114
wdenk8aa1a2d2005-04-04 12:44:11 +0000115#ifndef CONFIG_SKIP_RELOCATE_UBOOT
wdenk1cb8e982003-03-06 21:55:29 +0000116relocate: /* relocate U-Boot to RAM */
117 adr r0, _start /* r0 <- current position of code */
wdenk8bde7f72003-06-27 21:31:46 +0000118 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
wdenk1cb8e982003-03-06 21:55:29 +0000119 cmp r0, r1 /* don't reloc during debug */
120 beq stack_setup
121
wdenkc6097192002-11-03 00:24:07 +0000122 ldr r2, _armboot_start
wdenkf6e20fc2004-02-08 19:38:38 +0000123 ldr r3, _bss_start
wdenk1cb8e982003-03-06 21:55:29 +0000124 sub r2, r3, r2 /* r2 <- size of armboot */
125 add r2, r0, r2 /* r2 <- source end address */
wdenkc6097192002-11-03 00:24:07 +0000126
127copy_loop:
128 ldmia r0!, {r3-r10} /* copy from source address [r0] */
129 stmia r1!, {r3-r10} /* copy to target address [r1] */
130 cmp r0, r2 /* until source end addreee [r2] */
131 ble copy_loop
wdenk8aa1a2d2005-04-04 12:44:11 +0000132#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
wdenkc6097192002-11-03 00:24:07 +0000133
wdenk384ae022002-11-05 00:17:55 +0000134 /* Set up the stack */
wdenk1cb8e982003-03-06 21:55:29 +0000135stack_setup:
wdenka8c7c702003-12-06 19:49:23 +0000136 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
137 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
138 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
139#ifdef CONFIG_USE_IRQ
140 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
141#endif
wdenk47cd00f2003-03-06 13:39:27 +0000142 sub sp, r0, #12 /* leave 3 words for abort-stack */
143
144clear_bss:
wdenk47cd00f2003-03-06 13:39:27 +0000145 ldr r0, _bss_start /* find start of bss segment */
wdenk47cd00f2003-03-06 13:39:27 +0000146 ldr r1, _bss_end /* stop here */
147 mov r2, #0x00000000 /* clear */
148
149clbss_l:str r2, [r0] /* clear loop... */
150 add r0, r0, #4
151 cmp r0, r1
wdenka1191902005-01-09 17:12:27 +0000152 ble clbss_l
wdenk47cd00f2003-03-06 13:39:27 +0000153
wdenkc6097192002-11-03 00:24:07 +0000154 ldr pc, _start_armboot
155
wdenk384ae022002-11-05 00:17:55 +0000156_start_armboot: .word start_armboot
wdenkc6097192002-11-03 00:24:07 +0000157
158
159/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000160/* */
161/* CPU_init_critical registers */
162/* */
163/* - setup important registers */
164/* - setup memory timing */
165/* */
wdenkc6097192002-11-03 00:24:07 +0000166/****************************************************************************/
167
wdenk1cb8e982003-03-06 21:55:29 +0000168/* Interrupt-Controller base address */
wdenkc6097192002-11-03 00:24:07 +0000169IC_BASE: .word 0x40d00000
170#define ICMR 0x04
171
172/* Reset-Controller */
wdenk384ae022002-11-05 00:17:55 +0000173RST_BASE: .word 0x40f00030
wdenkc6097192002-11-03 00:24:07 +0000174#define RCSR 0x00
175
wdenk1cb8e982003-03-06 21:55:29 +0000176/* Operating System Timer */
wdenk384ae022002-11-05 00:17:55 +0000177OSTIMER_BASE: .word 0x40a00000
178#define OSMR3 0x0C
179#define OSCR 0x10
180#define OWER 0x18
181#define OIER 0x1C
wdenkc6097192002-11-03 00:24:07 +0000182
wdenk1cb8e982003-03-06 21:55:29 +0000183/* Clock Manager Registers */
wdenka8c7c702003-12-06 19:49:23 +0000184#ifdef CFG_CPUSPEED
wdenk384ae022002-11-05 00:17:55 +0000185CC_BASE: .word 0x41300000
186#define CCCR 0x00
187cpuspeed: .word CFG_CPUSPEED
wdenka8c7c702003-12-06 19:49:23 +0000188#else
189#error "You have to define CFG_CPUSPEED!!"
190#endif
wdenk1cb8e982003-03-06 21:55:29 +0000191
192
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100193 /* takes care the CP15 update has taken place */
194 .macro CPWAIT reg
195 mrc p15,0,\reg,c2,c0,0
196 mov \reg,\reg
wdenkc6097192002-11-03 00:24:07 +0000197 sub pc,pc,#4
198 .endm
199
200
201cpu_init_crit:
202
wdenk384ae022002-11-05 00:17:55 +0000203 /* mask all IRQs */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100204#ifndef CONFIG_CPU_MONAHANS
205
wdenkc6097192002-11-03 00:24:07 +0000206 ldr r0, IC_BASE
207 mov r1, #0x00
208 str r1, [r0, #ICMR]
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100209#else
210 /* Step 1 - Enable CP6 permission */
211 mrc p15, 0, r1, c15, c1, 0 @ read CPAR
212 orr r1, r1, #0x40
213 mcr p15, 0, r1, c15, c1, 0
214 CPWAIT r1
wdenkc6097192002-11-03 00:24:07 +0000215
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100216 /* Step 2 - Mask ICMR & ICMR2 */
217 mov r1, #0
218 mcr p6, 0, r1, c1, c0, 0 @ ICMR
219 mcr p6, 0, r1, c7, c0, 0 @ ICMR2
220#endif
wdenk1cb8e982003-03-06 21:55:29 +0000221
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100222#ifndef CONFIG_CPU_MONAHANS
223#ifdef CFG_CPUSPEED
224
225 /* set clock speed tbd@mk: required for monahans? */
wdenkc6097192002-11-03 00:24:07 +0000226 ldr r0, CC_BASE
227 ldr r1, cpuspeed
228 str r1, [r0, #CCCR]
wdenk1cb8e982003-03-06 21:55:29 +0000229 mov r0, #2
wdenk7f6c2cb2002-11-10 22:06:23 +0000230 mcr p14, 0, r0, c6, c0, 0
wdenk1cb8e982003-03-06 21:55:29 +0000231
232setspeed_done:
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100233
234#endif /* CFG_CPUSPEED */
235#endif /* CONFIG_CPU_MONAHANS */
236
wdenkc6097192002-11-03 00:24:07 +0000237
238 /*
239 * before relocating, we have to setup RAM timing
240 * because memory timing is board-dependend, you will
wdenk400558b2005-04-02 23:52:25 +0000241 * find a lowlevel_init.S in your board directory.
wdenkc6097192002-11-03 00:24:07 +0000242 */
243 mov ip, lr
wdenk400558b2005-04-02 23:52:25 +0000244 bl lowlevel_init
wdenkc6097192002-11-03 00:24:07 +0000245 mov lr, ip
246
247 /* Memory interfaces are working. Disable MMU and enable I-cache. */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100248 /* mk: hmm, this is not in the monahans docs, leave it now but
249 * check here if it doesn't work :-) */
wdenkc6097192002-11-03 00:24:07 +0000250
wdenk384ae022002-11-05 00:17:55 +0000251 ldr r0, =0x2001 /* enable access to all coproc. */
wdenkc6097192002-11-03 00:24:07 +0000252 mcr p15, 0, r0, c15, c1, 0
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100253 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000254
255 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100256 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000257
wdenk384ae022002-11-05 00:17:55 +0000258 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100259 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000260
261 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100262 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000263
wdenk384ae022002-11-05 00:17:55 +0000264 /* Enable the Icache */
wdenkc6097192002-11-03 00:24:07 +0000265/*
266 mrc p15, 0, r0, c1, c0, 0
267 orr r0, r0, #0x1800
268 mcr p15, 0, r0, c1, c0, 0
wdenk699b13a2002-11-03 18:03:52 +0000269 CPWAIT
wdenkc6097192002-11-03 00:24:07 +0000270*/
271 mov pc, lr
272
273
274/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000275/* */
276/* Interrupt handling */
277/* */
wdenkc6097192002-11-03 00:24:07 +0000278/****************************************************************************/
279
wdenk384ae022002-11-05 00:17:55 +0000280/* IRQ stack frame */
wdenkc6097192002-11-03 00:24:07 +0000281
282#define S_FRAME_SIZE 72
283
284#define S_OLD_R0 68
285#define S_PSR 64
286#define S_PC 60
287#define S_LR 56
288#define S_SP 52
289
290#define S_IP 48
291#define S_FP 44
292#define S_R10 40
293#define S_R9 36
294#define S_R8 32
295#define S_R7 28
296#define S_R6 24
297#define S_R5 20
298#define S_R4 16
299#define S_R3 12
300#define S_R2 8
301#define S_R1 4
302#define S_R0 0
303
304#define MODE_SVC 0x13
305
wdenk384ae022002-11-05 00:17:55 +0000306 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
wdenkc6097192002-11-03 00:24:07 +0000307
308 .macro bad_save_user_regs
309 sub sp, sp, #S_FRAME_SIZE
wdenk384ae022002-11-05 00:17:55 +0000310 stmia sp, {r0 - r12} /* Calling r0-r12 */
311 add r8, sp, #S_PC
wdenkc6097192002-11-03 00:24:07 +0000312
wdenkf6e20fc2004-02-08 19:38:38 +0000313 ldr r2, _armboot_start
314 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
315 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
wdenk384ae022002-11-05 00:17:55 +0000316 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
317 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
wdenkc6097192002-11-03 00:24:07 +0000318
319 add r5, sp, #S_SP
320 mov r1, lr
wdenk384ae022002-11-05 00:17:55 +0000321 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
wdenkc6097192002-11-03 00:24:07 +0000322 mov r0, sp
323 .endm
324
325
wdenk384ae022002-11-05 00:17:55 +0000326 /* use irq_save_user_regs / irq_restore_user_regs for */
327 /* IRQ/FIQ handling */
wdenkc6097192002-11-03 00:24:07 +0000328
329 .macro irq_save_user_regs
330 sub sp, sp, #S_FRAME_SIZE
wdenk384ae022002-11-05 00:17:55 +0000331 stmia sp, {r0 - r12} /* Calling r0-r12 */
332 add r8, sp, #S_PC
333 stmdb r8, {sp, lr}^ /* Calling SP, LR */
334 str lr, [r8, #0] /* Save calling PC */
335 mrs r6, spsr
336 str r6, [r8, #4] /* Save CPSR */
337 str r0, [r8, #8] /* Save OLD_R0 */
wdenkc6097192002-11-03 00:24:07 +0000338 mov r0, sp
339 .endm
340
341 .macro irq_restore_user_regs
342 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
343 mov r0, r0
344 ldr lr, [sp, #S_PC] @ Get PC
345 add sp, sp, #S_FRAME_SIZE
346 subs pc, lr, #4 @ return & move spsr_svc into cpsr
347 .endm
348
349 .macro get_bad_stack
wdenkf6e20fc2004-02-08 19:38:38 +0000350 ldr r13, _armboot_start @ setup our mode stack
351 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
352 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
wdenkc6097192002-11-03 00:24:07 +0000353
354 str lr, [r13] @ save caller lr / spsr
355 mrs lr, spsr
wdenk384ae022002-11-05 00:17:55 +0000356 str lr, [r13, #4]
wdenkc6097192002-11-03 00:24:07 +0000357
358 mov r13, #MODE_SVC @ prepare SVC-Mode
359 msr spsr_c, r13
360 mov lr, pc
361 movs pc, lr
362 .endm
363
364 .macro get_irq_stack @ setup IRQ stack
365 ldr sp, IRQ_STACK_START
366 .endm
367
368 .macro get_fiq_stack @ setup FIQ stack
369 ldr sp, FIQ_STACK_START
370 .endm
371
372
373/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000374/* */
375/* exception handlers */
376/* */
wdenkc6097192002-11-03 00:24:07 +0000377/****************************************************************************/
378
wdenk384ae022002-11-05 00:17:55 +0000379 .align 5
wdenkc6097192002-11-03 00:24:07 +0000380undefined_instruction:
381 get_bad_stack
382 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000383 bl do_undefined_instruction
wdenkc6097192002-11-03 00:24:07 +0000384
385 .align 5
386software_interrupt:
387 get_bad_stack
388 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000389 bl do_software_interrupt
wdenkc6097192002-11-03 00:24:07 +0000390
391 .align 5
392prefetch_abort:
393 get_bad_stack
394 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000395 bl do_prefetch_abort
wdenkc6097192002-11-03 00:24:07 +0000396
397 .align 5
398data_abort:
399 get_bad_stack
400 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000401 bl do_data_abort
wdenkc6097192002-11-03 00:24:07 +0000402
403 .align 5
404not_used:
405 get_bad_stack
406 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000407 bl do_not_used
wdenkc6097192002-11-03 00:24:07 +0000408
409#ifdef CONFIG_USE_IRQ
410
411 .align 5
412irq:
413 get_irq_stack
414 irq_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000415 bl do_irq
wdenkc6097192002-11-03 00:24:07 +0000416 irq_restore_user_regs
417
418 .align 5
419fiq:
420 get_fiq_stack
421 irq_save_user_regs /* someone ought to write a more */
wdenk384ae022002-11-05 00:17:55 +0000422 bl do_fiq /* effiction fiq_save_user_regs */
wdenkc6097192002-11-03 00:24:07 +0000423 irq_restore_user_regs
424
425#else
426
427 .align 5
428irq:
429 get_bad_stack
430 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000431 bl do_irq
wdenkc6097192002-11-03 00:24:07 +0000432
433 .align 5
434fiq:
435 get_bad_stack
436 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000437 bl do_fiq
wdenkc6097192002-11-03 00:24:07 +0000438
439#endif
440
wdenk1cb8e982003-03-06 21:55:29 +0000441/****************************************************************************/
442/* */
443/* Reset function: the PXA250 doesn't have a reset function, so we have to */
444/* perform a watchdog timeout for a soft reset. */
445/* */
446/****************************************************************************/
447
wdenkc6097192002-11-03 00:24:07 +0000448 .align 5
449.globl reset_cpu
wdenk1cb8e982003-03-06 21:55:29 +0000450
451 /* FIXME: this code is PXA250 specific. How is this handled on */
452 /* other XScale processors? */
453
wdenkc6097192002-11-03 00:24:07 +0000454reset_cpu:
wdenk1cb8e982003-03-06 21:55:29 +0000455
wdenk384ae022002-11-05 00:17:55 +0000456 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
wdenkc6097192002-11-03 00:24:07 +0000457
wdenk384ae022002-11-05 00:17:55 +0000458 ldr r0, OSTIMER_BASE
459 ldr r1, [r0, #OWER]
460 orr r1, r1, #0x0001 /* bit0: WME */
461 str r1, [r0, #OWER]
462
463 /* OS timer does only wrap every 1165 seconds, so we have to set */
464 /* the match register as well. */
465
466 ldr r1, [r0, #OSCR] /* read OS timer */
467 add r1, r1, #0x800 /* let OSMR3 match after */
468 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
469 str r1, [r0, #OSMR3]
470
471reset_endless:
472
473 b reset_endless