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Pragnesh Patel7c45fc92020-05-29 11:33:34 +05301# SPDX-License-Identifier: GPL-2.0+
2#
3# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4
5config SIFIVE_FU540
6 bool
7 select ARCH_EARLY_INIT_R
Bin Mengff8e88a2020-08-02 23:09:04 -07008 select SUPPORT_SPL
9 select RAM
10 select SPL_RAM if SPL
Pragnesh Patel7c45fc92020-05-29 11:33:34 +053011 imply CPU
12 imply CPU_RISCV
Sean Andersonc33efaf2020-09-28 10:52:21 -040013 imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
Bin Menga6d7e8c2021-05-11 20:04:12 +080014 imply SPL_SIFIVE_CLINT
Pragnesh Patel7c45fc92020-05-29 11:33:34 +053015 imply CMD_CPU
Simon Glass529d5f92021-03-15 18:11:18 +130016 imply SPL_CPU
Pragnesh Patel7c45fc92020-05-29 11:33:34 +053017 imply SPL_OPENSBI
18 imply SPL_LOAD_FIT
Bin Mengff8e88a2020-08-02 23:09:04 -070019 imply SMP
20 imply CLK_SIFIVE
Green Wand56d79e2021-05-27 06:52:08 -070021 imply CLK_SIFIVE_PRCI
Zong Li835210a2021-09-01 15:01:42 +080022 imply SIFIVE_CACHE
23 imply SIFIVE_CCACHE
Bin Mengff8e88a2020-08-02 23:09:04 -070024 imply SIFIVE_SERIAL
25 imply MACB
26 imply MII
27 imply SPI
28 imply SPI_SIFIVE
29 imply MMC
30 imply MMC_SPI
31 imply MMC_BROKEN_CD
32 imply CMD_MMC
33 imply DM_GPIO
34 imply SIFIVE_GPIO
35 imply CMD_GPIO
36 imply MISC
37 imply SIFIVE_OTP
38 imply DM_PWM
39 imply PWM_SIFIVE
Pragnesh Patelf517e5f2020-11-14 14:42:35 +053040 imply DM_I2C
41 imply SYS_I2C_OCORES
Jagan Tekiff7d25e2020-07-15 15:39:00 +053042
43if ENV_IS_IN_SPI_FLASH
44
45config ENV_OFFSET
46 default 0x505000
47
48config ENV_SIZE
49 default 0x20000
50
51config ENV_SECT_SIZE
52 default 0x10000
53
54endif # ENV_IS_IN_SPI_FLASH