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Stefan Roese566806c2007-10-05 17:11:30 +02001/*
Grant Erickson8a24c072008-05-22 14:44:24 -07002 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
4 *
Stefan Roese566806c2007-10-05 17:11:30 +02005 * (C) Copyright 2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese566806c2007-10-05 17:11:30 +02009 */
10
11/************************************************************************
12 * kilauea.h - configuration for AMCC Kilauea (405EX)
13 ***********************************************************************/
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*-----------------------------------------------------------------------
19 * High Level Configuration Options
20 *----------------------------------------------------------------------*/
21#define CONFIG_KILAUEA 1 /* Board is Kilauea */
Stefan Roese566806c2007-10-05 17:11:30 +020022#define CONFIG_405EX 1 /* Specifc 405EX support*/
23#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
24
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#ifndef CONFIG_SYS_TEXT_BASE
26#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
27#endif
28
Stefan Roese490f2042008-06-06 15:55:03 +020029/*
Steven A. Falco644362c2011-05-05 10:08:35 -040030 * CHIP_21 errata - you must set this to match your exact CPU, else your
31 * board will not boot. DO NOT enable this unless you have JTAG available
32 * for recovery, in the event you get it wrong.
33 *
34 * Kilauea uses the 405EX, while Haleakala uses the 405EXr. Either board
35 * may be equipped for security or not. You must look at the CPU part
36 * number to be sure what you have.
37 */
38/* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
39/* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
40/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
41/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
42
43/*
Stefan Roese490f2042008-06-06 15:55:03 +020044 * Include common defines/options for all AMCC eval boards
45 */
46#define CONFIG_HOSTNAME kilauea
47#include "amcc-common.h"
48
Stefan Roese566806c2007-10-05 17:11:30 +020049#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
50#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Stefan Roese9998b132010-01-21 11:37:31 +010051#define CONFIG_BOARD_TYPES
Stefan Roese353f2682007-10-23 10:10:08 +020052#define CONFIG_BOARD_EMAC_COUNT
Stefan Roese566806c2007-10-05 17:11:30 +020053
54/*-----------------------------------------------------------------------
55 * Base addresses -- Note these are effective addresses where the
56 * actual resources get mapped (not physical addresses)
57 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_FLASH_BASE 0xFC000000
59#define CONFIG_SYS_NAND_ADDR 0xF8000000
60#define CONFIG_SYS_FPGA_BASE 0xF0000000
Stefan Roese566806c2007-10-05 17:11:30 +020061
62/*-----------------------------------------------------------------------
Grant Erickson8a24c072008-05-22 14:44:24 -070063 * Initial RAM & Stack Pointer Configuration Options
64 *
65 * There are traditionally three options for the primordial
66 * (i.e. initial) stack usage on the 405-series:
67 *
68 * 1) On-chip Memory (OCM) (i.e. SRAM)
69 * 2) Data cache
70 * 3) SDRAM
71 *
72 * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
73 * the latter of which is less than desireable since it requires
74 * setting up the SDRAM and ECC in assembly code.
75 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076 * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
Grant Erickson8a24c072008-05-22 14:44:24 -070077 * select on the External Bus Controller (EBC) and then select a
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
79 * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
80 * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
Grant Erickson8a24c072008-05-22 14:44:24 -070081 * physical SDRAM to use (3).
82 *-----------------------------------------------------------------------*/
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_INIT_DCACHE_CS 4
Grant Erickson8a24c072008-05-22 14:44:24 -070085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#if defined(CONFIG_SYS_INIT_DCACHE_CS)
87#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
Grant Erickson8a24c072008-05-22 14:44:24 -070088#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
90#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
Grant Erickson8a24c072008-05-22 14:44:24 -070091
Wolfgang Denk553f0982010-10-26 13:32:32 +020092#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) /* 4 KiB */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020093#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Stefan Roese566806c2007-10-05 17:11:30 +020094
Grant Erickson8a24c072008-05-22 14:44:24 -070095/*
96 * If the data cache is being used for the primordial stack and global
97 * data area, the POST word must be placed somewhere else. The General
98 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
99 * its compare and mask register contents across reset, so it is used
100 * for the POST word.
101 */
102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#if defined(CONFIG_SYS_INIT_DCACHE_CS)
104# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Michael Zaidman800eb092010-09-20 08:51:53 +0200105# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
Grant Erickson8a24c072008-05-22 14:44:24 -0700106#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107# define CONFIG_SYS_INIT_EXTRA_SIZE 16
108# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
110#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
Stefan Roese566806c2007-10-05 17:11:30 +0200111
112/*-----------------------------------------------------------------------
113 * Serial Port
114 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Stefan Roese550650d2010-09-20 16:05:31 +0200116#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese566806c2007-10-05 17:11:30 +0200117
Stefan Roese566806c2007-10-05 17:11:30 +0200118/*-----------------------------------------------------------------------
119 * Environment
120 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200121#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese566806c2007-10-05 17:11:30 +0200122
123/*-----------------------------------------------------------------------
124 * FLASH related
125 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200127#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese566806c2007-10-05 17:11:30 +0200128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
130#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
131#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese566806c2007-10-05 17:11:30 +0200132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese566806c2007-10-05 17:11:30 +0200135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
137#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese566806c2007-10-05 17:11:30 +0200138
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200139#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200140#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese566806c2007-10-05 17:11:30 +0200143
144/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200145#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
146#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200147#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese566806c2007-10-05 17:11:30 +0200148
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100149/*-----------------------------------------------------------------------
150 * NAND FLASH
151 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
154#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese3d6cb3b2007-11-03 12:08:28 +0100155
Stefan Roese566806c2007-10-05 17:11:30 +0200156/*-----------------------------------------------------------------------
157 * DDR SDRAM
158 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
Stefan Roese566806c2007-10-05 17:11:30 +0200160
Adam Grahamf6b6c452008-09-03 12:26:59 -0700161/*
162 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
163 *
164 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
165 * SDRAM Controller DDR autocalibration values and takes a lot longer
166 * to run than Method_B.
167 * (See the Method_A and Method_B algorithm discription in the file:
Stefan Roesea47a12b2010-04-15 16:07:28 +0200168 * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
Adam Grahamf6b6c452008-09-03 12:26:59 -0700169 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
170 *
171 * DDR Autocalibration Method_B is the default.
172 */
173#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
174#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
175#undef CONFIG_PPC4xx_DDR_METHOD_A
176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
Grant Erickson8a24c072008-05-22 14:44:24 -0700178
179/* DDR1/2 SDRAM Device Control Register Data Values */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
Grant Erickson8a24c072008-05-22 14:44:24 -0700181 SDRAM_RXBAS_SDSZ_256MB | \
182 SDRAM_RXBAS_SDAM_MODE7 | \
183 SDRAM_RXBAS_SDBE_ENABLE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
185#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
186#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
187#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
Grant Erickson2e205082008-07-09 16:46:35 -0700188 SDRAM_MCOPT1_8_BANKS | \
189 SDRAM_MCOPT1_DDR2_TYPE | \
190 SDRAM_MCOPT1_QDEP | \
191 SDRAM_MCOPT1_DCOO_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
193#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700194 SDRAM_MODT_EB0R_ENABLE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
196#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
Grant Erickson2e205082008-07-09 16:46:35 -0700197 SDRAM_CODT_CKLZ_36OHM | \
198 SDRAM_CODT_DQS_1_8_V_DDR2 | \
199 SDRAM_CODT_IO_NMODE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
201#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700202 SDRAM_INITPLR_IMWT_ENCODE(80) | \
203 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700205 SDRAM_INITPLR_IMWT_ENCODE(3) | \
206 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
207 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
208 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700210 SDRAM_INITPLR_IMWT_ENCODE(2) | \
211 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
212 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
213 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700215 SDRAM_INITPLR_IMWT_ENCODE(2) | \
216 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
217 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
218 SDRAM_INITPLR_IMA_ENCODE(0))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700220 SDRAM_INITPLR_IMWT_ENCODE(2) | \
221 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
222 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
223 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
224 JEDEC_MA_EMR_RTT_75OHM))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700226 SDRAM_INITPLR_IMWT_ENCODE(2) | \
227 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
228 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
229 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
230 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
231 JEDEC_MA_MR_BLEN_4 | \
232 JEDEC_MA_MR_DLL_RESET))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700234 SDRAM_INITPLR_IMWT_ENCODE(3) | \
235 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
236 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
237 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700239 SDRAM_INITPLR_IMWT_ENCODE(26) | \
240 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700242 SDRAM_INITPLR_IMWT_ENCODE(26) | \
243 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700245 SDRAM_INITPLR_IMWT_ENCODE(26) | \
246 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700248 SDRAM_INITPLR_IMWT_ENCODE(26) | \
249 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700251 SDRAM_INITPLR_IMWT_ENCODE(2) | \
252 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
253 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
254 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
255 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
256 JEDEC_MA_MR_BLEN_4))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700258 SDRAM_INITPLR_IMWT_ENCODE(2) | \
259 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
260 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
261 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
262 JEDEC_MA_EMR_RDQS_DISABLE | \
263 JEDEC_MA_EMR_DQS_DISABLE | \
264 JEDEC_MA_EMR_RTT_DISABLED | \
265 JEDEC_MA_EMR_ODS_NORMAL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700267 SDRAM_INITPLR_IMWT_ENCODE(2) | \
268 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
269 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
270 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
271 JEDEC_MA_EMR_RDQS_DISABLE | \
272 JEDEC_MA_EMR_DQS_DISABLE | \
273 JEDEC_MA_EMR_RTT_DISABLED | \
274 JEDEC_MA_EMR_ODS_NORMAL))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
276#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
277#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700278 SDRAM_RQDC_RQFD_ENCODE(56))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
280#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
281#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
Grant Erickson2e205082008-07-09 16:46:35 -0700282 SDRAM_DLCR_DLCS_CONT_DONE | \
283 SDRAM_DLCR_DLCV_ENCODE(165))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
285#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
286#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
Grant Erickson2e205082008-07-09 16:46:35 -0700287 SDRAM_SDTR1_RTW_2_CLK | \
288 SDRAM_SDTR1_RTRO_1_CLK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
Grant Erickson2e205082008-07-09 16:46:35 -0700290 SDRAM_SDTR2_WTR_2_CLK | \
291 SDRAM_SDTR2_XSNR_32_CLK | \
292 SDRAM_SDTR2_WPC_4_CLK | \
293 SDRAM_SDTR2_RPC_2_CLK | \
294 SDRAM_SDTR2_RP_3_CLK | \
295 SDRAM_SDTR2_RRD_2_CLK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
Grant Erickson2e205082008-07-09 16:46:35 -0700297 SDRAM_SDTR3_RC_ENCODE(11) | \
298 SDRAM_SDTR3_XCS | \
299 SDRAM_SDTR3_RFC_ENCODE(26))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
Grant Erickson2e205082008-07-09 16:46:35 -0700301 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
302 SDRAM_MMODE_BLEN_4)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
Grant Erickson2e205082008-07-09 16:46:35 -0700304 SDRAM_MEMODE_RTT_75OHM)
Grant Erickson8a24c072008-05-22 14:44:24 -0700305
Stefan Roese566806c2007-10-05 17:11:30 +0200306/*-----------------------------------------------------------------------
307 * I2C
308 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000309#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese566806c2007-10-05 17:11:30 +0200310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
312#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roesef6af8ce2009-07-21 14:33:52 +0200313#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
314#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese566806c2007-10-05 17:11:30 +0200315
Stefan Roese4b1389e2009-07-21 14:06:29 +0200316/* I2C bootstrap EEPROM */
317#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
318#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
319#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
320
Stefan Roese566806c2007-10-05 17:11:30 +0200321/* Standard DTT sensor configuration */
322#define CONFIG_DTT_DS1775 1
323#define CONFIG_DTT_SENSORS { 0 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_I2C_DTT_ADDR 0x48
Stefan Roese566806c2007-10-05 17:11:30 +0200325
326/* RTC configuration */
327#define CONFIG_RTC_DS1338 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Stefan Roese566806c2007-10-05 17:11:30 +0200329
330/*-----------------------------------------------------------------------
331 * Ethernet
332 *----------------------------------------------------------------------*/
333#define CONFIG_M88E1111_PHY 1
334#define CONFIG_IBM_EMAC4_V4 1
Grant Erickson1740c1b2008-07-08 08:35:00 -0700335#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
Stefan Roese566806c2007-10-05 17:11:30 +0200336#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
337
338#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
339#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
340
341#define CONFIG_HAS_ETH0 1
342
Stefan Roese566806c2007-10-05 17:11:30 +0200343#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
344#define CONFIG_PHY1_ADDR 2
345
Adam Grahamf6b6c452008-09-03 12:26:59 -0700346/* Debug messages for the DDR autocalibration */
347#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
348
Stefan Roese490f2042008-06-06 15:55:03 +0200349/*
350 * Default environment variables
351 */
Stefan Roese566806c2007-10-05 17:11:30 +0200352#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200353 CONFIG_AMCC_DEF_ENV \
354 CONFIG_AMCC_DEF_ENV_POWERPC \
355 CONFIG_AMCC_DEF_ENV_PPC_OLD \
356 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese566806c2007-10-05 17:11:30 +0200357 "logversion=2\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200358 "kernel_addr=fc000000\0" \
Stefan Roese64e541f2008-04-11 07:02:29 +0200359 "fdt_addr=fc1e0000\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200360 "ramdisk_addr=fc200000\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200361 "pciconfighost=1\0" \
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200362 "pcie_mode=RP:RP\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200363 ""
Stefan Roese566806c2007-10-05 17:11:30 +0200364
365/*
Stefan Roese490f2042008-06-06 15:55:03 +0200366 * Commands additional to the ones defined in amcc-common.h
Stefan Roese566806c2007-10-05 17:11:30 +0200367 */
Stefan Roese4b1389e2009-07-21 14:06:29 +0200368#define CONFIG_CMD_CHIP_CONFIG
Stefan Roese566806c2007-10-05 17:11:30 +0200369#define CONFIG_CMD_DATE
Stefan Roese566806c2007-10-05 17:11:30 +0200370#define CONFIG_CMD_NAND
Stefan Roese566806c2007-10-05 17:11:30 +0200371#define CONFIG_CMD_PCI
Stefan Roese566806c2007-10-05 17:11:30 +0200372
Stefan Roesedd7c3022009-04-15 14:08:48 +0200373#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
Stefan Roesedd7c3022009-04-15 14:08:48 +0200374
Stefan Roese566806c2007-10-05 17:11:30 +0200375/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
377 CONFIG_SYS_POST_CPU | \
378 CONFIG_SYS_POST_ETHER | \
379 CONFIG_SYS_POST_I2C | \
Stefan Roesedd7c3022009-04-15 14:08:48 +0200380 CONFIG_SYS_POST_MEMORY_ON | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381 CONFIG_SYS_POST_UART)
Stefan Roese566806c2007-10-05 17:11:30 +0200382
383/* Define here the base-addresses of the UARTs to test in POST */
Stefan Roese5d7c73e2010-09-29 16:58:38 +0200384#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
385 CONFIG_SYS_NS16550_COM2 }
Stefan Roese566806c2007-10-05 17:11:30 +0200386
387#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
Stefan Roese566806c2007-10-05 17:11:30 +0200389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Stefan Roese566806c2007-10-05 17:11:30 +0200391
Stefan Roese566806c2007-10-05 17:11:30 +0200392/*-----------------------------------------------------------------------
393 * PCI stuff
394 *----------------------------------------------------------------------*/
395#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000396#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese566806c2007-10-05 17:11:30 +0200397#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
398#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
399#define CONFIG_PCI_CONFIG_HOST_BRIDGE
400
401/*-----------------------------------------------------------------------
402 * PCIe stuff
403 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
405#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
Stefan Roese566806c2007-10-05 17:11:30 +0200406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */
408#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */
409#define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
Stefan Roese566806c2007-10-05 17:11:30 +0200410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */
412#define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */
413#define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
Stefan Roese566806c2007-10-05 17:11:30 +0200414
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
416#define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
Stefan Roese566806c2007-10-05 17:11:30 +0200417
418/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
Stefan Roese566806c2007-10-05 17:11:30 +0200420
Stefan Roese566806c2007-10-05 17:11:30 +0200421/*-----------------------------------------------------------------------
Stefan Roese566806c2007-10-05 17:11:30 +0200422 * External Bus Controller (EBC) Setup
423 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */
Stefan Roese566806c2007-10-05 17:11:30 +0200425
426/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_EBC_PB0AP 0x05806500
428#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
Stefan Roese566806c2007-10-05 17:11:30 +0200429
430/* Memory Bank 1 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_EBC_PB1AP 0x018003c0
432#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
Stefan Roese566806c2007-10-05 17:11:30 +0200433
Stefan Roese9998b132010-01-21 11:37:31 +0100434/* Memory Bank 2 (FPGA) initialization */
435#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \
436 EBC_BXAP_FWT_ENCODE(6) | \
437 EBC_BXAP_BWT_ENCODE(1) | \
438 EBC_BXAP_BCE_DISABLE | \
439 EBC_BXAP_BCT_2TRANS | \
440 EBC_BXAP_CSN_ENCODE(0) | \
441 EBC_BXAP_OEN_ENCODE(0) | \
442 EBC_BXAP_WBN_ENCODE(3) | \
443 EBC_BXAP_WBF_ENCODE(1) | \
444 EBC_BXAP_TH_ENCODE(4) | \
445 EBC_BXAP_RE_DISABLED | \
446 EBC_BXAP_SOR_DELAYED | \
447 EBC_BXAP_BEM_WRITEONLY | \
448 EBC_BXAP_PEN_DISABLED)
449#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000)
Stefan Roese566806c2007-10-05 17:11:30 +0200450
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */
Stefan Roese566806c2007-10-05 17:11:30 +0200452
453/*-----------------------------------------------------------------------
Stefan Roese566806c2007-10-05 17:11:30 +0200454 * GPIO Setup
455 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100457{ \
458/* GPIO Core 0 */ \
459{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
460{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
461{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
462{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
463{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
464{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
465{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
466{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
Stefan Roese8be76092007-11-27 11:57:35 +0100467{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
468{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
469{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100470{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
471{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
472{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100473{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
474{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100475{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
Stefan Roese8be76092007-11-27 11:57:35 +0100476{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100477{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
478{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
479{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
480{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
481{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
482{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
483{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
484{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
485{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
486{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
487{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \
Stefan Roese8be76092007-11-27 11:57:35 +0100488{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
489{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
490{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
Stefan Roese9ea61b52007-11-17 14:52:29 +0100491} \
492}
Stefan Roese566806c2007-10-05 17:11:30 +0200493
Stefan Roese566806c2007-10-05 17:11:30 +0200494/*-----------------------------------------------------------------------
495 * Some Kilauea stuff..., mainly fpga registers
496 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE
Stefan Roese9998b132010-01-21 11:37:31 +0100498#define CONFIG_SYS_FPGA_FIFO_BASE (CONFIG_SYS_FPGA_BASE | (1 << 10))
Stefan Roese566806c2007-10-05 17:11:30 +0200499
500/* interrupt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000
502#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT 0x40000000
503#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT 0x20000000
504#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT 0x10000000
505#define CONFIG_SYS_FPGA_PHY0_INT 0x08000000
506#define CONFIG_SYS_FPGA_PHY1_INT 0x04000000
507#define CONFIG_SYS_FPGA_SLIC0_INT 0x02000000
508#define CONFIG_SYS_FPGA_SLIC1_INT 0x01000000
Stefan Roese566806c2007-10-05 17:11:30 +0200509
510/* DPRAM setting */
511/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */
513#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */
514#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE 0x00080000
515#define CONFIG_SYS_FPGA_DPRAM_RST 0x00040000
516#define CONFIG_SYS_FPGA_UART0_FO 0x00020000
517#define CONFIG_SYS_FPGA_UART1_FO 0x00010000
Stefan Roese566806c2007-10-05 17:11:30 +0200518
519/* loopback */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK 0x00004000
521#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK 0x00008000
522#define CONFIG_SYS_FPGA_SLIC0_ENABLE 0x00002000
523#define CONFIG_SYS_FPGA_SLIC1_ENABLE 0x00001000
524#define CONFIG_SYS_FPGA_SLIC0_CS 0x00000800
525#define CONFIG_SYS_FPGA_SLIC1_CS 0x00000400
526#define CONFIG_SYS_FPGA_USER_LED0 0x00000200
527#define CONFIG_SYS_FPGA_USER_LED1 0x00000100
Stefan Roese566806c2007-10-05 17:11:30 +0200528
Stefan Roese9998b132010-01-21 11:37:31 +0100529#define CONFIG_SYS_FPGA_MAGIC_MASK 0xffff0000
530#define CONFIG_SYS_FPGA_MAGIC 0xabcd0000
531#define CONFIG_SYS_FPGA_VER_MASK 0x0000ff00
532
Stefan Roese837c7302007-10-21 14:26:29 +0200533#endif /* __CONFIG_H */