Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * ISEE 2007 SL, <www.iseebcn.com> |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 6 | */ |
| 7 | #include <common.h> |
Enric Balletbo i Serra | f3b4bc4 | 2015-01-28 15:01:32 +0100 | [diff] [blame] | 8 | #include <status_led.h> |
Simon Glass | b3f4ca1 | 2014-10-22 21:37:15 -0600 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | #include <ns16550.h> |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 11 | #include <twl4030.h> |
Javier Martinez Canillas | 77eea28 | 2012-12-27 01:35:56 +0000 | [diff] [blame] | 12 | #include <netdev.h> |
Sanjeev Premi | 84c3b63 | 2011-09-08 10:51:01 -0400 | [diff] [blame] | 13 | #include <asm/gpio.h> |
Javier Martinez Canillas | 77eea28 | 2012-12-27 01:35:56 +0000 | [diff] [blame] | 14 | #include <asm/io.h> |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 15 | #include <asm/arch/mem.h> |
Enric Balletbo i Serra | f49d7b6 | 2010-11-04 15:34:33 -0400 | [diff] [blame] | 16 | #include <asm/arch/mmc_host_def.h> |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 17 | #include <asm/arch/mux.h> |
| 18 | #include <asm/arch/sys_proto.h> |
| 19 | #include <asm/mach-types.h> |
Javier Martinez Canillas | 77eea28 | 2012-12-27 01:35:56 +0000 | [diff] [blame] | 20 | #include "igep00x0.h" |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 21 | |
John Rigby | 2956532 | 2010-12-20 18:27:51 -0700 | [diff] [blame] | 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Ladislav Michl | b7e042d | 2016-07-12 20:28:27 +0200 | [diff] [blame] | 24 | const omap3_sysinfo sysinfo = { |
| 25 | DDR_STACKED, |
| 26 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) |
| 27 | "IGEPv2", |
| 28 | #endif |
| 29 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) |
| 30 | "IGEP COM MODULE/ELECTRON", |
| 31 | #endif |
| 32 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) |
| 33 | "IGEP COM PROTON", |
| 34 | #endif |
| 35 | #if defined(CONFIG_ENV_IS_IN_ONENAND) |
| 36 | "ONENAND", |
| 37 | #else |
| 38 | "NAND", |
| 39 | #endif |
| 40 | }; |
| 41 | |
Simon Glass | b3f4ca1 | 2014-10-22 21:37:15 -0600 | [diff] [blame] | 42 | static const struct ns16550_platdata igep_serial = { |
Adam Ford | 2f6ed3b | 2016-03-07 21:08:49 -0600 | [diff] [blame] | 43 | .base = OMAP34XX_UART3, |
| 44 | .reg_shift = 2, |
| 45 | .clock = V_NS16550_CLK |
Simon Glass | b3f4ca1 | 2014-10-22 21:37:15 -0600 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | U_BOOT_DEVICE(igep_uart) = { |
Thomas Chou | c7b9686 | 2015-11-19 21:48:12 +0800 | [diff] [blame] | 49 | "ns16550_serial", |
Simon Glass | b3f4ca1 | 2014-10-22 21:37:15 -0600 | [diff] [blame] | 50 | &igep_serial |
| 51 | }; |
| 52 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 53 | /* |
| 54 | * Routine: board_init |
| 55 | * Description: Early hardware init. |
| 56 | */ |
| 57 | int board_init(void) |
| 58 | { |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 59 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 60 | /* boot param addr */ |
| 61 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
| 62 | |
Enric Balletbo i Serra | f3b4bc4 | 2015-01-28 15:01:32 +0100 | [diff] [blame] | 63 | #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) |
| 64 | status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); |
| 65 | #endif |
| 66 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 67 | return 0; |
| 68 | } |
| 69 | |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 70 | #ifdef CONFIG_SPL_BUILD |
| 71 | /* |
| 72 | * Routine: omap_rev_string |
| 73 | * Description: For SPL builds output board rev |
| 74 | */ |
| 75 | void omap_rev_string(void) |
| 76 | { |
| 77 | } |
| 78 | |
| 79 | /* |
| 80 | * Routine: get_board_mem_timings |
| 81 | * Description: If we use SPL then there is no x-loader nor config header |
| 82 | * so we have to setup the DDR timings ourself on both banks. |
| 83 | */ |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 84 | void get_board_mem_timings(struct board_sdrc_timings *timings) |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 85 | { |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 86 | timings->mr = MICRON_V_MR_165; |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 87 | #ifdef CONFIG_BOOT_NAND |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 88 | timings->mcfg = MICRON_V_MCFG_200(256 << 20); |
| 89 | timings->ctrla = MICRON_V_ACTIMA_200; |
| 90 | timings->ctrlb = MICRON_V_ACTIMB_200; |
| 91 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 92 | #else |
| 93 | if (get_cpu_family() == CPU_OMAP34XX) { |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 94 | timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); |
| 95 | timings->ctrla = NUMONYX_V_ACTIMA_165; |
| 96 | timings->ctrlb = NUMONYX_V_ACTIMB_165; |
| 97 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 98 | |
| 99 | } else { |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 100 | timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); |
| 101 | timings->ctrla = NUMONYX_V_ACTIMA_200; |
| 102 | timings->ctrlb = NUMONYX_V_ACTIMB_200; |
| 103 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 104 | } |
| 105 | #endif |
| 106 | } |
| 107 | #endif |
| 108 | |
Javier Martinez Canillas | 77eea28 | 2012-12-27 01:35:56 +0000 | [diff] [blame] | 109 | #if defined(CONFIG_CMD_NET) |
Ladislav Michl | 6ed75ba | 2016-01-04 23:07:59 +0100 | [diff] [blame] | 110 | static void reset_net_chip(int gpio) |
| 111 | { |
| 112 | if (!gpio_request(gpio, "eth nrst")) { |
| 113 | gpio_direction_output(gpio, 1); |
| 114 | udelay(1); |
| 115 | gpio_set_value(gpio, 0); |
| 116 | udelay(40); |
| 117 | gpio_set_value(gpio, 1); |
| 118 | mdelay(10); |
| 119 | } |
| 120 | } |
| 121 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 122 | /* |
| 123 | * Routine: setup_net_chip |
| 124 | * Description: Setting up the configuration GPMC registers specific to the |
| 125 | * Ethernet hardware. |
| 126 | */ |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 127 | static void setup_net_chip(void) |
| 128 | { |
| 129 | struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
Ladislav Michl | b0c4763 | 2016-07-12 20:28:28 +0200 | [diff] [blame^] | 130 | static const u32 gpmc_lan_config[] = { |
| 131 | NET_LAN9221_GPMC_CONFIG1, |
| 132 | NET_LAN9221_GPMC_CONFIG2, |
| 133 | NET_LAN9221_GPMC_CONFIG3, |
| 134 | NET_LAN9221_GPMC_CONFIG4, |
| 135 | NET_LAN9221_GPMC_CONFIG5, |
| 136 | NET_LAN9221_GPMC_CONFIG6, |
| 137 | }; |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 138 | |
Ladislav Michl | 6ed75ba | 2016-01-04 23:07:59 +0100 | [diff] [blame] | 139 | enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], |
| 140 | CONFIG_SMC911X_BASE, GPMC_SIZE_16M); |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 141 | |
| 142 | /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ |
| 143 | writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
| 144 | /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ |
| 145 | writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); |
| 146 | /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ |
| 147 | writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, |
| 148 | &ctrl_base->gpmc_nadv_ale); |
| 149 | |
Ladislav Michl | 6ed75ba | 2016-01-04 23:07:59 +0100 | [diff] [blame] | 150 | reset_net_chip(64); |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 151 | } |
Ladislav Michl | b0c4763 | 2016-07-12 20:28:28 +0200 | [diff] [blame^] | 152 | |
| 153 | int board_eth_init(bd_t *bis) |
| 154 | { |
| 155 | #ifdef CONFIG_SMC911X |
| 156 | return smc911x_initialize(0, CONFIG_SMC911X_BASE); |
| 157 | #else |
| 158 | return 0; |
| 159 | #endif |
| 160 | } |
Javier Martinez Canillas | 77eea28 | 2012-12-27 01:35:56 +0000 | [diff] [blame] | 161 | #else |
| 162 | static inline void setup_net_chip(void) {} |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 163 | #endif |
| 164 | |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 165 | #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) |
Enric Balletbo i Serra | f49d7b6 | 2010-11-04 15:34:33 -0400 | [diff] [blame] | 166 | int board_mmc_init(bd_t *bis) |
| 167 | { |
Nikita Kiryanov | e3913f5 | 2012-12-03 02:19:47 +0000 | [diff] [blame] | 168 | return omap_mmc_init(0, 0, 0, -1, -1); |
Enric Balletbo i Serra | f49d7b6 | 2010-11-04 15:34:33 -0400 | [diff] [blame] | 169 | } |
| 170 | #endif |
| 171 | |
Paul Kocialkowski | aac5450 | 2014-11-08 20:55:47 +0100 | [diff] [blame] | 172 | #if defined(CONFIG_GENERIC_MMC) |
| 173 | void board_mmc_power_init(void) |
| 174 | { |
| 175 | twl4030_power_mmc_init(0); |
| 176 | } |
| 177 | #endif |
| 178 | |
Javier Martinez Canillas | a2fa28b | 2013-08-07 17:53:19 +0200 | [diff] [blame] | 179 | void set_fdt(void) |
| 180 | { |
| 181 | switch (gd->bd->bi_arch_number) { |
| 182 | case MACH_TYPE_IGEP0020: |
Enric Balletbò i Serra | 4037224 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 183 | setenv("fdtfile", "omap3-igep0020.dtb"); |
Javier Martinez Canillas | a2fa28b | 2013-08-07 17:53:19 +0200 | [diff] [blame] | 184 | break; |
| 185 | case MACH_TYPE_IGEP0030: |
Enric Balletbò i Serra | 4037224 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 186 | setenv("fdtfile", "omap3-igep0030.dtb"); |
Javier Martinez Canillas | a2fa28b | 2013-08-07 17:53:19 +0200 | [diff] [blame] | 187 | break; |
| 188 | } |
| 189 | } |
| 190 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 191 | /* |
| 192 | * Routine: misc_init_r |
| 193 | * Description: Configure board specific parts |
| 194 | */ |
| 195 | int misc_init_r(void) |
| 196 | { |
| 197 | twl4030_power_init(); |
| 198 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 199 | setup_net_chip(); |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 200 | |
Paul Kocialkowski | 679f82c | 2015-08-27 19:37:13 +0200 | [diff] [blame] | 201 | omap_die_id_display(); |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 202 | |
Javier Martinez Canillas | a2fa28b | 2013-08-07 17:53:19 +0200 | [diff] [blame] | 203 | set_fdt(); |
| 204 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 205 | return 0; |
| 206 | } |
| 207 | |
| 208 | /* |
| 209 | * Routine: set_muxconf_regs |
| 210 | * Description: Setting up the configuration Mux registers specific to the |
| 211 | * hardware. Many pins need to be moved from protect to primary |
| 212 | * mode. |
| 213 | */ |
| 214 | void set_muxconf_regs(void) |
| 215 | { |
| 216 | MUX_DEFAULT(); |
Javier Martinez Canillas | 77eea28 | 2012-12-27 01:35:56 +0000 | [diff] [blame] | 217 | |
| 218 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) |
| 219 | MUX_IGEP0020(); |
| 220 | #endif |
| 221 | |
| 222 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) |
| 223 | MUX_IGEP0030(); |
| 224 | #endif |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 225 | } |