blob: df4255b828a71eb5420967f5c0bd70ba45ffb394 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk71f95112003-06-15 22:40:42 +00002/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00003 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05004 * Andy Fleming
5 *
6 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00007 */
8
9#ifndef _MMC_H_
10#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000011
Andy Fleming272cc702008-10-30 16:41:01 -050012#include <linux/list.h>
Peng Fan3697e592016-09-01 11:13:38 +080013#include <linux/sizes.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000014#include <linux/compiler.h>
Mateusz Zalega07a2d422014-04-30 13:04:15 +020015#include <part.h>
Andy Fleming272cc702008-10-30 16:41:01 -050016
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010017#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
18#define MMC_SUPPORTS_TUNING
19#endif
20#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
21#define MMC_SUPPORTS_TUNING
22#endif
23
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020024/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
25#define SD_VERSION_SD (1U << 31)
26#define MMC_VERSION_MMC (1U << 30)
27
28#define MAKE_SDMMC_VERSION(a, b, c) \
29 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
30#define MAKE_SD_VERSION(a, b, c) \
31 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
32#define MAKE_MMC_VERSION(a, b, c) \
33 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
34
35#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
36 (((u32)(x) >> 16) & 0xff)
37#define EXTRACT_SDMMC_MINOR_VERSION(x) \
38 (((u32)(x) >> 8) & 0xff)
39#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
40 ((u32)(x) & 0xff)
41
42#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
43#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
44#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
45#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
46
47#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
48#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
49#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
50#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
51#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
52#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
53#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
54#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
55#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
Jean-Jacques Hiblotace1bed2018-02-09 12:09:28 +010056#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020057#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
58#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
59#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
Stefan Wahren1a3619c2016-06-16 17:54:06 +000060#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
Andy Fleming272cc702008-10-30 16:41:01 -050061
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020062#define MMC_CAP(mode) (1 << mode)
63#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
64#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
65#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +020066#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020067
68#define MMC_MODE_8BIT BIT(30)
69#define MMC_MODE_4BIT BIT(29)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +020070#define MMC_MODE_1BIT BIT(28)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020071#define MMC_MODE_SPI BIT(27)
72
Ɓukasz Majewski62722032012-03-12 22:07:18 +000073
Andy Fleming272cc702008-10-30 16:41:01 -050074#define SD_DATA_4BIT 0x00040000
75
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020076#define IS_SD(x) ((x)->version & SD_VERSION_SD)
Andrew Gabbasov3f2da752015-03-19 07:44:02 -050077#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
Andy Fleming272cc702008-10-30 16:41:01 -050078
79#define MMC_DATA_READ 1
80#define MMC_DATA_WRITE 2
81
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020082#define MMC_CMD_GO_IDLE_STATE 0
83#define MMC_CMD_SEND_OP_COND 1
84#define MMC_CMD_ALL_SEND_CID 2
85#define MMC_CMD_SET_RELATIVE_ADDR 3
86#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050087#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020088#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050089#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020090#define MMC_CMD_SEND_CSD 9
91#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050092#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020093#define MMC_CMD_SEND_STATUS 13
94#define MMC_CMD_SET_BLOCKLEN 16
95#define MMC_CMD_READ_SINGLE_BLOCK 17
96#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +020097#define MMC_CMD_SEND_TUNING_BLOCK 19
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +020098#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
Pierre Aubert91fdabc2014-04-24 10:30:06 +020099#define MMC_CMD_SET_BLOCK_COUNT 23
Andy Fleming272cc702008-10-30 16:41:01 -0500100#define MMC_CMD_WRITE_SINGLE_BLOCK 24
101#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +0000102#define MMC_CMD_ERASE_GROUP_START 35
103#define MMC_CMD_ERASE_GROUP_END 36
104#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200105#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +0000106#define MMC_CMD_SPI_READ_OCR 58
107#define MMC_CMD_SPI_CRC_ON_OFF 59
Amar3690d6d2013-04-27 11:42:58 +0530108#define MMC_CMD_RES_MAN 62
109
110#define MMC_CMD62_ARG1 0xefac62ec
111#define MMC_CMD62_ARG2 0xcbaea7
112
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200113
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200114#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -0500115#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200116#define SD_CMD_SEND_IF_COND 8
Otavio Salvadorf022d362015-02-17 10:42:43 -0200117#define SD_CMD_SWITCH_UHS18V 11
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200118
119#define SD_CMD_APP_SET_BUS_WIDTH 6
Peng Fan3697e592016-09-01 11:13:38 +0800120#define SD_CMD_APP_SD_STATUS 13
Lei Wene6f99a52011-06-22 17:03:31 +0000121#define SD_CMD_ERASE_WR_BLK_START 32
122#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200123#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -0500124#define SD_CMD_APP_SEND_SCR 51
125
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200126static inline bool mmc_is_tuning_cmd(uint cmdidx)
127{
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200128 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
129 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200130 return true;
131 return false;
132}
133
Andy Fleming272cc702008-10-30 16:41:01 -0500134/* SCR definitions in different words */
135#define SD_HIGHSPEED_BUSY 0x00020000
136#define SD_HIGHSPEED_SUPPORTED 0x00020000
137
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200138#define UHS_SDR12_BUS_SPEED 0
139#define HIGH_SPEED_BUS_SPEED 1
140#define UHS_SDR25_BUS_SPEED 1
141#define UHS_SDR50_BUS_SPEED 2
142#define UHS_SDR104_BUS_SPEED 3
143#define UHS_DDR50_BUS_SPEED 4
144
145#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
146#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
147#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
148#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
149#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
150
Thomas Chouabe2c932011-04-19 03:48:31 +0000151#define OCR_BUSY 0x80000000
152#define OCR_HCS 0x40000000
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200153#define OCR_S18R 0x1000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000154#define OCR_VOLTAGE_MASK 0x007FFF80
155#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500156
Eric Nelson1aa2d072015-12-07 07:50:01 -0700157#define MMC_ERASE_ARG 0x00000000
158#define MMC_SECURE_ERASE_ARG 0x80000000
159#define MMC_TRIM_ARG 0x00000001
160#define MMC_DISCARD_ARG 0x00000003
161#define MMC_SECURE_TRIM1_ARG 0x80000001
162#define MMC_SECURE_TRIM2_ARG 0x80008000
Lei Wene6f99a52011-06-22 17:03:31 +0000163
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000164#define MMC_STATUS_MASK (~0x0206BF7F)
Andrew Gabbasov6b2221b2014-04-03 04:34:32 -0500165#define MMC_STATUS_SWITCH_ERROR (1 << 7)
Thomas Chouabe2c932011-04-19 03:48:31 +0000166#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
167#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000168#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000169
Jan Kloetzked617c422012-02-05 22:29:12 +0000170#define MMC_STATE_PRG (7 << 9)
171
Andy Fleming272cc702008-10-30 16:41:01 -0500172#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
173#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
174#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
175#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
176#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
177#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
178#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
179#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
180#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
181#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
182#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
183#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
184#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
185#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
186#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
187#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
188#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
189
190#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
191#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
192 addressed by index which are
193 1 in value field */
194#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
195 addressed by index, which are
196 1 in value field */
197#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
198
199#define SD_SWITCH_CHECK 0
200#define SD_SWITCH_SWITCH 1
201
202/*
203 * EXT_CSD fields
204 */
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100205#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
206#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600207#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Markus Niebeld7b29122014-11-18 15:11:42 +0100208#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
Oliver Metz1937e5a2013-10-01 20:32:07 +0200209#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100210#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
Lei Wen0560db12011-10-03 20:35:10 +0000211#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Tom Rini33ace362014-02-07 14:15:20 -0500212#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Tomas Melincd3d4882016-11-25 11:01:03 +0200213#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100214#define EXT_CSD_WR_REL_PARAM 166 /* R */
215#define EXT_CSD_WR_REL_SET 167 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600216#define EXT_CSD_RPMB_MULT 168 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000217#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Amar3690d6d2013-04-27 11:42:58 +0530218#define EXT_CSD_BOOT_BUS_WIDTH 177
Lei Wen0560db12011-10-03 20:35:10 +0000219#define EXT_CSD_PART_CONF 179 /* R/W */
220#define EXT_CSD_BUS_WIDTH 183 /* R/W */
221#define EXT_CSD_HS_TIMING 185 /* R/W */
222#define EXT_CSD_REV 192 /* RO */
223#define EXT_CSD_CARD_TYPE 196 /* RO */
224#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
Stephen Warrenf866a462013-06-11 15:14:01 -0600225#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000226#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000227#define EXT_CSD_BOOT_MULT 226 /* RO */
Tomas Melincd3d4882016-11-25 11:01:03 +0200228#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500229
230/*
231 * EXT_CSD field definitions
232 */
233
Thomas Chouabe2c932011-04-19 03:48:31 +0000234#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
235#define EXT_CSD_CMD_SET_SECURE (1 << 1)
236#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500237
Thomas Chouabe2c932011-04-19 03:48:31 +0000238#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
239#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900240#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
241#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
242#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
243 | EXT_CSD_CARD_TYPE_DDR_1_2V)
Andy Fleming272cc702008-10-30 16:41:01 -0500244
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200245#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
246 /* SDR mode @1.8V I/O */
247#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
248 /* SDR mode @1.2V I/O */
249#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
250 EXT_CSD_CARD_TYPE_HS200_1_2V)
251
Andy Fleming272cc702008-10-30 16:41:01 -0500252#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
253#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
254#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900255#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
256#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200257#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200258
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200259#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
260#define EXT_CSD_TIMING_HS 1 /* HS */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200261#define EXT_CSD_TIMING_HS200 2 /* HS200 */
262
Amar3690d6d2013-04-27 11:42:58 +0530263#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
264#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
265#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
266#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
267
268#define EXT_CSD_BOOT_ACK(x) (x << 6)
269#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
270#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
271
Angelo Dureghellobdb60992017-08-01 14:27:10 +0200272#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
273#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
274#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
275
Tom Rini5a99b9d2014-02-05 10:24:22 -0500276#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
277#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
278#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
Amar3690d6d2013-04-27 11:42:58 +0530279
Markus Niebeld7b29122014-11-18 15:11:42 +0100280#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
281
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100282#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
283#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
284
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100285#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
286
287#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
288#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
289
Andy Fleming1de97f92008-10-30 16:31:39 -0500290#define R1_ILLEGAL_COMMAND (1 << 22)
291#define R1_APP_CMD (1 << 5)
292
Andy Fleming272cc702008-10-30 16:41:01 -0500293#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000294#define MMC_RSP_136 (1 << 1) /* 136 bit response */
295#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
296#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
297#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500298
Thomas Chouabe2c932011-04-19 03:48:31 +0000299#define MMC_RSP_NONE (0)
300#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500301#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
302 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000303#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
304#define MMC_RSP_R3 (MMC_RSP_PRESENT)
305#define MMC_RSP_R4 (MMC_RSP_PRESENT)
306#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
307#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
308#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500309
Lei Wenbc897b12011-05-02 16:26:26 +0000310#define MMCPART_NOAVAILABLE (0xff)
311#define PART_ACCESS_MASK (0x7)
312#define PART_SUPPORT (0x1)
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100313#define ENHNCD_SUPPORT (0x2)
Oliver Metz1937e5a2013-10-01 20:32:07 +0200314#define PART_ENH_ATTRIB (0x1f)
wdenk71f95112003-06-15 22:40:42 +0000315
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200316#define MMC_QUIRK_RETRY_SEND_CID BIT(0)
317#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
318
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200319enum mmc_voltage {
320 MMC_SIGNAL_VOLTAGE_000 = 0,
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200321 MMC_SIGNAL_VOLTAGE_120 = 1,
322 MMC_SIGNAL_VOLTAGE_180 = 2,
323 MMC_SIGNAL_VOLTAGE_330 = 4,
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200324};
325
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200326#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
327 MMC_SIGNAL_VOLTAGE_180 |\
328 MMC_SIGNAL_VOLTAGE_330)
329
Simon Glass8bfa1952013-04-03 08:54:30 +0000330/* Maximum block size for MMC */
331#define MMC_MAX_BLOCK_LEN 512
332
Amar3690d6d2013-04-27 11:42:58 +0530333/* The number of MMC physical partitions. These consist of:
334 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
335 */
336#define MMC_NUM_BOOT_PARTITION 2
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200337#define MMC_PART_RPMB 3 /* RPMB partition number */
Amar3690d6d2013-04-27 11:42:58 +0530338
Simon Glasse7ecf7c2015-06-23 15:38:48 -0600339/* Driver model support */
340
341/**
342 * struct mmc_uclass_priv - Holds information about a device used by the uclass
343 */
344struct mmc_uclass_priv {
345 struct mmc *mmc;
346};
347
348/**
349 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
350 *
351 * Provided that the device is already probed and ready for use, this value
352 * will be available.
353 *
354 * @dev: Device
355 * @return associated mmc struct pointer if available, else NULL
356 */
357struct mmc *mmc_get_mmc_dev(struct udevice *dev);
358
359/* End of driver model support */
360
Andy Fleming1de97f92008-10-30 16:31:39 -0500361struct mmc_cid {
362 unsigned long psn;
363 unsigned short oid;
364 unsigned char mid;
365 unsigned char prv;
366 unsigned char mdt;
367 char pnm[7];
368};
369
Andy Fleming272cc702008-10-30 16:41:01 -0500370struct mmc_cmd {
371 ushort cmdidx;
372 uint resp_type;
373 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530374 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500375};
376
377struct mmc_data {
378 union {
379 char *dest;
380 const char *src; /* src buffers don't get written to */
381 };
382 uint flags;
383 uint blocks;
384 uint blocksize;
385};
386
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200387/* forward decl. */
388struct mmc;
389
Simon Glasse7881d82017-07-29 11:35:31 -0600390#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass8ca51e52016-06-12 23:30:22 -0600391struct dm_mmc_ops {
392 /**
393 * send_cmd() - Send a command to the MMC device
394 *
395 * @dev: Device to receive the command
396 * @cmd: Command to send
397 * @data: Additional data to send/receive
398 * @return 0 if OK, -ve on error
399 */
400 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
401 struct mmc_data *data);
402
403 /**
404 * set_ios() - Set the I/O speed/width for an MMC device
405 *
406 * @dev: Device to update
407 * @return 0 if OK, -ve on error
408 */
409 int (*set_ios)(struct udevice *dev);
410
411 /**
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +0200412 * send_init_stream() - send the initialization stream: 74 clock cycles
413 * This is used after power up before sending the first command
414 *
415 * @dev: Device to update
416 */
417 void (*send_init_stream)(struct udevice *dev);
418
419 /**
Simon Glass8ca51e52016-06-12 23:30:22 -0600420 * get_cd() - See whether a card is present
421 *
422 * @dev: Device to check
423 * @return 0 if not present, 1 if present, -ve on error
424 */
425 int (*get_cd)(struct udevice *dev);
426
427 /**
428 * get_wp() - See whether a card has write-protect enabled
429 *
430 * @dev: Device to check
431 * @return 0 if write-enabled, 1 if write-protected, -ve on error
432 */
433 int (*get_wp)(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200434
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100435#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200436 /**
437 * execute_tuning() - Start the tuning process
438 *
439 * @dev: Device to start the tuning
440 * @opcode: Command opcode to send
441 * @return 0 if OK, -ve on error
442 */
443 int (*execute_tuning)(struct udevice *dev, uint opcode);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100444#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200445
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100446#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200447 /**
448 * wait_dat0() - wait until dat0 is in the target state
449 * (CLK must be running during the wait)
450 *
451 * @dev: Device to check
452 * @state: target state
453 * @timeout: timeout in us
454 * @return 0 if dat0 is in the target state, -ve on error
455 */
456 int (*wait_dat0)(struct udevice *dev, int state, int timeout);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100457#endif
Simon Glass8ca51e52016-06-12 23:30:22 -0600458};
459
460#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
461
462int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
463 struct mmc_data *data);
464int dm_mmc_set_ios(struct udevice *dev);
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +0200465void dm_mmc_send_init_stream(struct udevice *dev);
Simon Glass8ca51e52016-06-12 23:30:22 -0600466int dm_mmc_get_cd(struct udevice *dev);
467int dm_mmc_get_wp(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200468int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200469int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
Simon Glass8ca51e52016-06-12 23:30:22 -0600470
471/* Transition functions for compatibility */
472int mmc_set_ios(struct mmc *mmc);
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +0200473void mmc_send_init_stream(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600474int mmc_getcd(struct mmc *mmc);
475int mmc_getwp(struct mmc *mmc);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200476int mmc_execute_tuning(struct mmc *mmc, uint opcode);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200477int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
Simon Glass8ca51e52016-06-12 23:30:22 -0600478
479#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200480struct mmc_ops {
481 int (*send_cmd)(struct mmc *mmc,
482 struct mmc_cmd *cmd, struct mmc_data *data);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900483 int (*set_ios)(struct mmc *mmc);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200484 int (*init)(struct mmc *mmc);
485 int (*getcd)(struct mmc *mmc);
486 int (*getwp)(struct mmc *mmc);
487};
Simon Glass8ca51e52016-06-12 23:30:22 -0600488#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200489
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200490struct mmc_config {
491 const char *name;
Simon Glasse7881d82017-07-29 11:35:31 -0600492#if !CONFIG_IS_ENABLED(DM_MMC)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200493 const struct mmc_ops *ops;
Simon Glass8ca51e52016-06-12 23:30:22 -0600494#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200495 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500496 uint voltages;
Andy Fleming272cc702008-10-30 16:41:01 -0500497 uint f_min;
498 uint f_max;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200499 uint b_max;
500 unsigned char part_type;
501};
502
Peng Fan3697e592016-09-01 11:13:38 +0800503struct sd_ssr {
504 unsigned int au; /* In sectors */
505 unsigned int erase_timeout; /* In milliseconds */
506 unsigned int erase_offset; /* In milliseconds */
507};
508
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200509enum bus_mode {
510 MMC_LEGACY,
511 SD_LEGACY,
512 MMC_HS,
513 SD_HS,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100514 MMC_HS_52,
515 MMC_DDR_52,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200516 UHS_SDR12,
517 UHS_SDR25,
518 UHS_SDR50,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200519 UHS_DDR50,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100520 UHS_SDR104,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200521 MMC_HS_200,
522 MMC_MODES_END
523};
524
525const char *mmc_mode_name(enum bus_mode mode);
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +0200526void mmc_dump_capabilities(const char *text, uint caps);
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200527
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200528static inline bool mmc_is_mode_ddr(enum bus_mode mode)
529{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100530 if (mode == MMC_DDR_52)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200531 return true;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100532#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
533 else if (mode == UHS_DDR50)
534 return true;
535#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200536 else
537 return false;
538}
539
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200540#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
541 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
542 MMC_CAP(UHS_DDR50))
543
544static inline bool supports_uhs(uint caps)
545{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100546#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200547 return (caps & UHS_CAPS) ? true : false;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100548#else
549 return false;
550#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200551}
552
Simon Glass8ca51e52016-06-12 23:30:22 -0600553/*
554 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
555 * with mmc_get_mmc_dev().
556 *
557 * TODO struct mmc should be in mmc_private but it's hard to fix right now
558 */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200559struct mmc {
Simon Glassc4d660d2017-07-04 13:31:19 -0600560#if !CONFIG_IS_ENABLED(BLK)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200561 struct list_head link;
Simon Glass33fb2112016-05-01 13:52:41 -0600562#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200563 const struct mmc_config *cfg; /* provided configuration */
564 uint version;
565 void *priv;
566 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500567 int high_capacity;
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200568 bool clk_disable; /* true if the clock can be turned off */
Andy Fleming272cc702008-10-30 16:41:01 -0500569 uint bus_width;
570 uint clock;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200571 enum mmc_voltage signal_voltage;
Andy Fleming272cc702008-10-30 16:41:01 -0500572 uint card_caps;
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +0200573 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500574 uint ocr;
Markus Niebelab711882013-12-16 13:40:46 +0100575 uint dsr;
576 uint dsr_imp;
Andy Fleming272cc702008-10-30 16:41:01 -0500577 uint scr[2];
578 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530579 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500580 ushort rca;
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100581 u8 part_support;
582 u8 part_attr;
Diego Santa Cruz9e41a002014-12-23 10:50:33 +0100583 u8 wr_rel_set;
Tom Rini7ca0d3d2017-05-10 15:20:16 -0400584 u8 part_config;
Andy Fleming272cc702008-10-30 16:41:01 -0500585 uint tran_speed;
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200586 uint legacy_speed; /* speed for the legacy mode provided by the card */
Andy Fleming272cc702008-10-30 16:41:01 -0500587 uint read_bl_len;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100588#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Fleming272cc702008-10-30 16:41:01 -0500589 uint write_bl_len;
Diego Santa Cruza4ff9f82014-12-23 10:50:24 +0100590 uint erase_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100591#endif
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100592#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruz037dc0a2014-12-23 10:50:25 +0100593 uint hc_wp_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100594#endif
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100595#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fan3697e592016-09-01 11:13:38 +0800596 struct sd_ssr ssr; /* SD status register */
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100597#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500598 u64 capacity;
Stephen Warrenf866a462013-06-11 15:14:01 -0600599 u64 capacity_user;
600 u64 capacity_boot;
601 u64 capacity_rpmb;
602 u64 capacity_gp[4];
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100603#ifndef CONFIG_SPL_BUILD
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100604 u64 enh_user_start;
605 u64 enh_user_size;
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100606#endif
Simon Glassc4d660d2017-07-04 13:31:19 -0600607#if !CONFIG_IS_ENABLED(BLK)
Simon Glass4101f682016-02-29 15:25:34 -0700608 struct blk_desc block_dev;
Simon Glass33fb2112016-05-01 13:52:41 -0600609#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +0000610 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
611 char init_in_progress; /* 1 if we have done mmc_start_init() */
612 char preinit; /* start init as early as possible */
Andrew Gabbasov786e8f82014-12-01 06:59:09 -0600613 int ddr_mode;
Simon Glassc4d660d2017-07-04 13:31:19 -0600614#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glasscffe5d82016-05-01 13:52:34 -0600615 struct udevice *dev; /* Device for this MMC controller */
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +0200616#if CONFIG_IS_ENABLED(DM_REGULATOR)
617 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
618 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
619#endif
Simon Glasscffe5d82016-05-01 13:52:34 -0600620#endif
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +0200621 u8 *ext_csd;
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200622 u32 cardtype; /* cardtype read from the MMC */
623 enum mmc_voltage current_voltage;
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200624 enum bus_mode selected_mode; /* mode currently used */
625 enum bus_mode best_mode; /* best mode is the supported mode with the
626 * highest bandwidth. It may not always be the
627 * operating mode due to limitations when
628 * accessing the boot partitions
629 */
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200630 u32 quirks;
Andy Fleming272cc702008-10-30 16:41:01 -0500631};
632
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100633struct mmc_hwpart_conf {
634 struct {
635 uint enh_start; /* in 512-byte sectors */
636 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100637 unsigned wr_rel_change : 1;
638 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100639 } user;
640 struct {
641 uint size; /* in 512-byte sectors */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100642 unsigned enhanced : 1;
643 unsigned wr_rel_change : 1;
644 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100645 } gp_part[4];
646};
647
648enum mmc_hwpart_conf_mode {
649 MMC_HWPART_CONF_CHECK,
650 MMC_HWPART_CONF_SET,
651 MMC_HWPART_CONF_COMPLETE,
652};
653
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200654struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
Simon Glassad27dd52016-05-01 13:52:40 -0600655
656/**
657 * mmc_bind() - Set up a new MMC device ready for probing
658 *
659 * A child block device is bound with the IF_TYPE_MMC interface type. This
660 * allows the device to be used with CONFIG_BLK
661 *
662 * @dev: MMC device to set up
663 * @mmc: MMC struct
664 * @cfg: MMC configuration
665 * @return 0 if OK, -ve on error
666 */
667int mmc_bind(struct udevice *dev, struct mmc *mmc,
668 const struct mmc_config *cfg);
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200669void mmc_destroy(struct mmc *mmc);
Simon Glassad27dd52016-05-01 13:52:40 -0600670
671/**
672 * mmc_unbind() - Unbind a MMC device's child block device
673 *
674 * @dev: MMC device
675 * @return 0 if OK, -ve on error
676 */
677int mmc_unbind(struct udevice *dev);
Andy Fleming272cc702008-10-30 16:41:01 -0500678int mmc_initialize(bd_t *bis);
679int mmc_init(struct mmc *mmc);
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200680int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100681
682/**
683 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
684 *
685 * @dev: MMC device
686 * @cfg: MMC configuration
687 * @return 0 if OK, -ve on error
688 */
689int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
690
Andy Fleming272cc702008-10-30 16:41:01 -0500691int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200692
693/**
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200694 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
695 *
696 * @voltage: The mmc_voltage to convert
697 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
698 */
699int mmc_voltage_to_mv(enum mmc_voltage voltage);
700
701/**
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200702 * mmc_set_clock() - change the bus clock
703 * @mmc: MMC struct
704 * @clock: bus frequency in Hz
705 * @disable: flag indicating if the clock must on or off
706 * @return 0 if OK, -ve on error
707 */
708int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
709
Jaehoon Chung65117182018-01-26 19:25:29 +0900710#define MMC_CLK_ENABLE false
711#define MMC_CLK_DISABLE true
712
Andy Fleming272cc702008-10-30 16:41:01 -0500713struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700714int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500715void print_mmc_devices(char separator);
Kever Yang46683f32016-07-22 17:22:50 +0800716
717/**
718 * get_mmc_num() - get the total MMC device number
719 *
720 * @return 0 if there is no MMC device, else the number of devices
721 */
Lei Wenea6ebe22011-05-02 16:26:25 +0000722int get_mmc_num(void);
Marek Vasutb5b838f2016-12-01 02:06:33 +0100723int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100724int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
725 enum mmc_hwpart_conf_mode mode);
Simon Glass8ca51e52016-06-12 23:30:22 -0600726
Simon Glasse7881d82017-07-29 11:35:31 -0600727#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Reding48972d92012-01-02 01:15:37 +0000728int mmc_getcd(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200729int board_mmc_getcd(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000730int mmc_getwp(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200731int board_mmc_getwp(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600732#endif
733
Markus Niebelab711882013-12-16 13:40:46 +0100734int mmc_set_dsr(struct mmc *mmc, u16 val);
Amar3690d6d2013-04-27 11:42:58 +0530735/* Function to change the size of boot partition and rpmb partitions */
736int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
737 unsigned long rpmbsize);
Tom Rini792970b2014-02-05 10:24:21 -0500738/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
739int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
Tom Rini5a99b9d2014-02-05 10:24:22 -0500740/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
741int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
Tom Rini33ace362014-02-07 14:15:20 -0500742/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
743int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200744/* Functions to read / write the RPMB partition */
745int mmc_rpmb_set_key(struct mmc *mmc, void *key);
746int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
747int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
748 unsigned short cnt, unsigned char *key);
749int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
750 unsigned short cnt, unsigned char *key);
Tomas Melincd3d4882016-11-25 11:01:03 +0200751#ifdef CONFIG_CMD_BKOPS_ENABLE
752int mmc_set_bkops_enable(struct mmc *mmc);
753#endif
754
Che-Liang Chioue9550442012-11-28 15:21:13 +0000755/**
756 * Start device initialization and return immediately; it does not block on
Jon Nettleton6c09eba2018-06-11 15:26:19 +0300757 * polling OCR (operation condition register) status. Useful for checking
758 * the presence of SD/eMMC when no card detect logic is available.
759 *
760 * @param mmc Pointer to a MMC device struct
761 * @return 0 on success, <0 on error.
762 */
763int mmc_get_op_cond(struct mmc *mmc);
764
765/**
766 * Start device initialization and return immediately; it does not block on
Che-Liang Chioue9550442012-11-28 15:21:13 +0000767 * polling OCR (operation condition register) status. Then you should call
768 * mmc_init, which would block on polling OCR status and complete the device
769 * initializatin.
770 *
771 * @param mmc Pointer to a MMC device struct
Baruch Siach31d95002018-06-11 15:26:18 +0300772 * @return 0 on success, <0 on error.
Che-Liang Chioue9550442012-11-28 15:21:13 +0000773 */
774int mmc_start_init(struct mmc *mmc);
775
776/**
777 * Set preinit flag of mmc device.
778 *
779 * This will cause the device to be pre-inited during mmc_initialize(),
780 * which may save boot time if the device is not accessed until later.
781 * Some eMMC devices take 200-300ms to init, but unfortunately they
782 * must be sent a series of commands to even get them to start preparing
783 * for operation.
784 *
785 * @param mmc Pointer to a MMC device struct
786 * @param preinit preinit flag value
787 */
788void mmc_set_preinit(struct mmc *mmc, int preinit);
789
Paul Burton8687d5c2013-09-04 16:12:26 +0100790#ifdef CONFIG_MMC_SPI
Tom Rini0b2da7e2014-03-28 16:55:29 -0400791#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
Paul Burton8687d5c2013-09-04 16:12:26 +0100792#else
793#define mmc_host_is_spi(mmc) 0
794#endif
Thomas Choud52ebf12010-12-24 13:12:21 +0000795struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200796
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +0100797void board_mmc_power_init(void);
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200798int board_mmc_init(bd_t *bis);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200799int cpu_mmc_init(bd_t *bis);
Jeroen Hofsteeaeb80552014-10-08 22:58:05 +0200800int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
Clemens Gruberaa844fe2016-01-26 16:20:38 +0100801int mmc_get_env_dev(void);
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200802
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200803/* Set block count limit because of 16 bit register limit on some hardware*/
804#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
805#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
806#endif
807
Simon Glasscb5ec332016-05-01 13:52:27 -0600808/**
809 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
810 *
811 * @mmc: MMC device
812 * @return block device if found, else NULL
813 */
814struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
815
wdenk71f95112003-06-15 22:40:42 +0000816#endif /* _MMC_H_ */