blob: b80a259ff757b2e1af37f7a072b52fa628c0c2d0 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01002/*
3 * Copyright (C) 2005-2006 Atmel Corporation
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01004 */
5#include <common.h>
Wenyou Yang577aa3b2016-11-02 10:06:56 +08006#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -07007#include <cpu_func.h>
Simon Glassf1dcc192016-05-05 07:28:11 -06008#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Simon Glassc05ed002020-05-10 11:40:11 -060010#include <linux/delay.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010011
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010012/*
13 * The u-boot networking stack is a little weird. It seems like the
14 * networking core allocates receive buffers up front without any
15 * regard to the hardware that's supposed to actually receive those
16 * packets.
17 *
18 * The MACB receives packets into 128-byte receive buffers, so the
19 * buffers allocated by the core isn't very practical to use. We'll
20 * allocate our own, but we need one such buffer in case a packet
21 * wraps around the DMA ring so that we have to copy it.
22 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010024 * configuration header. This way, the core allocates one RX buffer
25 * and one TX buffer, each of which can hold a ethernet packet of
26 * maximum size.
27 *
28 * For some reason, the networking core unconditionally specifies a
29 * 32-byte packet "alignment" (which really should be called
30 * "padding"). MACB shouldn't need that, but we'll refrain from any
31 * core modifications here...
32 */
33
34#include <net.h>
Simon Glassf1dcc192016-05-05 07:28:11 -060035#ifndef CONFIG_DM_ETH
Ben Warren89973f82008-08-31 22:22:04 -070036#include <netdev.h>
Simon Glassf1dcc192016-05-05 07:28:11 -060037#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010038#include <malloc.h>
Semih Hazar0f751d62009-12-17 15:07:15 +020039#include <miiphy.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010040
41#include <linux/mii.h>
42#include <asm/io.h>
Masahiro Yamada9d86b892020-02-14 16:40:19 +090043#include <linux/dma-mapping.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010044#include <asm/arch/clk.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090045#include <linux/errno.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010046
47#include "macb.h"
48
Wenyou Yanga212b662016-05-17 13:11:35 +080049DECLARE_GLOBAL_DATA_PTR;
50
Ramon Friedc6d07bf2019-07-14 18:25:14 +030051/*
52 * These buffer sizes must be power of 2 and divisible
53 * by RX_BUFFER_MULTIPLE
54 */
55#define MACB_RX_BUFFER_SIZE 128
56#define GEM_RX_BUFFER_SIZE 2048
Ramon Fried9c295802019-07-16 22:04:36 +030057#define RX_BUFFER_MULTIPLE 64
Ramon Friedc6d07bf2019-07-14 18:25:14 +030058
59#define MACB_RX_RING_SIZE 32
Andreas Bießmannceef9832014-05-26 22:55:18 +020060#define MACB_TX_RING_SIZE 16
Ramon Friedc6d07bf2019-07-14 18:25:14 +030061
Andreas Bießmannceef9832014-05-26 22:55:18 +020062#define MACB_TX_TIMEOUT 1000
63#define MACB_AUTONEG_TIMEOUT 5000000
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010064
Wilson Lee4bf56912017-08-22 20:25:07 -070065#ifdef CONFIG_MACB_ZYNQ
66/* INCR4 AHB bursts */
67#define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
68/* Use full configured addressable space (8 Kb) */
69#define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
70/* Use full configured addressable space (4 Kb) */
71#define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
72/* Set RXBUF with use of 128 byte */
73#define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
74#define MACB_ZYNQ_GEM_DMACR_INIT \
75 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
76 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
77 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
78 MACB_ZYNQ_GEM_DMACR_RXBUF)
79#endif
80
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010081struct macb_dma_desc {
82 u32 addr;
83 u32 ctrl;
84};
85
Wu, Josh5ae0e382014-05-27 16:31:05 +080086#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
87#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
88#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
Wu, Joshade4ea42015-06-03 16:45:44 +080089#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
Wu, Josh5ae0e382014-05-27 16:31:05 +080090
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010091#define RXBUF_FRMLEN_MASK 0x00000fff
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010092#define TXBUF_FRMLEN_MASK 0x000007ff
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010093
94struct macb_device {
95 void *regs;
Anup Pateld0a04db2019-07-24 04:09:32 +000096
Anup Pateleff0e0c2019-07-24 04:09:37 +000097 bool is_big_endian;
98
Anup Pateld0a04db2019-07-24 04:09:32 +000099 const struct macb_config *config;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100100
101 unsigned int rx_tail;
102 unsigned int tx_head;
103 unsigned int tx_tail;
Simon Glassd5555b72016-05-05 07:28:09 -0600104 unsigned int next_rx_tail;
105 bool wrapped;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100106
107 void *rx_buffer;
108 void *tx_buffer;
109 struct macb_dma_desc *rx_ring;
110 struct macb_dma_desc *tx_ring;
Ramon Friedc6d07bf2019-07-14 18:25:14 +0300111 size_t rx_buffer_size;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100112
113 unsigned long rx_buffer_dma;
114 unsigned long rx_ring_dma;
115 unsigned long tx_ring_dma;
116
Wu, Joshade4ea42015-06-03 16:45:44 +0800117 struct macb_dma_desc *dummy_desc;
118 unsigned long dummy_desc_dma;
119
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100120 const struct device *dev;
Simon Glassf1dcc192016-05-05 07:28:11 -0600121#ifndef CONFIG_DM_ETH
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100122 struct eth_device netdev;
Simon Glassf1dcc192016-05-05 07:28:11 -0600123#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100124 unsigned short phy_addr;
Bo Shenb1a00062013-04-24 15:59:27 +0800125 struct mii_dev *bus;
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800126#ifdef CONFIG_PHYLIB
127 struct phy_device *phydev;
128#endif
Wenyou Yanga212b662016-05-17 13:11:35 +0800129
130#ifdef CONFIG_DM_ETH
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +0800131#ifdef CONFIG_CLK
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800132 unsigned long pclk_rate;
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +0800133#endif
Wenyou Yanga212b662016-05-17 13:11:35 +0800134 phy_interface_t phy_interface;
135#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100136};
Ramon Frieded3c64f2019-07-16 22:04:35 +0300137
138struct macb_config {
139 unsigned int dma_burst_length;
Anup Pateld0a04db2019-07-24 04:09:32 +0000140
141 int (*clk_init)(struct udevice *dev, ulong rate);
Ramon Frieded3c64f2019-07-16 22:04:35 +0300142};
143
Simon Glassf1dcc192016-05-05 07:28:11 -0600144#ifndef CONFIG_DM_ETH
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100145#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
Simon Glassf1dcc192016-05-05 07:28:11 -0600146#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100147
Bo Shend256be22013-04-24 15:59:28 +0800148static int macb_is_gem(struct macb_device *macb)
149{
Atish Patrafbcaa262019-02-25 08:14:42 +0000150 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
Bo Shend256be22013-04-24 15:59:28 +0800151}
152
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100153#ifndef cpu_is_sama5d2
154#define cpu_is_sama5d2() 0
155#endif
156
157#ifndef cpu_is_sama5d4
158#define cpu_is_sama5d4() 0
159#endif
160
161static int gem_is_gigabit_capable(struct macb_device *macb)
162{
163 /*
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400164 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100165 * configured to support only 10/100.
166 */
167 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
168}
169
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200170static void macb_mdio_write(struct macb_device *macb, u8 phy_adr, u8 reg,
171 u16 value)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100172{
173 unsigned long netctl;
174 unsigned long netstat;
175 unsigned long frame;
176
177 netctl = macb_readl(macb, NCR);
178 netctl |= MACB_BIT(MPE);
179 macb_writel(macb, NCR, netctl);
180
181 frame = (MACB_BF(SOF, 1)
182 | MACB_BF(RW, 1)
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200183 | MACB_BF(PHYA, phy_adr)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100184 | MACB_BF(REGA, reg)
185 | MACB_BF(CODE, 2)
186 | MACB_BF(DATA, value));
187 macb_writel(macb, MAN, frame);
188
189 do {
190 netstat = macb_readl(macb, NSR);
191 } while (!(netstat & MACB_BIT(IDLE)));
192
193 netctl = macb_readl(macb, NCR);
194 netctl &= ~MACB_BIT(MPE);
195 macb_writel(macb, NCR, netctl);
196}
197
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200198static u16 macb_mdio_read(struct macb_device *macb, u8 phy_adr, u8 reg)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100199{
200 unsigned long netctl;
201 unsigned long netstat;
202 unsigned long frame;
203
204 netctl = macb_readl(macb, NCR);
205 netctl |= MACB_BIT(MPE);
206 macb_writel(macb, NCR, netctl);
207
208 frame = (MACB_BF(SOF, 1)
209 | MACB_BF(RW, 2)
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200210 | MACB_BF(PHYA, phy_adr)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100211 | MACB_BF(REGA, reg)
212 | MACB_BF(CODE, 2));
213 macb_writel(macb, MAN, frame);
214
215 do {
216 netstat = macb_readl(macb, NSR);
217 } while (!(netstat & MACB_BIT(IDLE)));
218
219 frame = macb_readl(macb, MAN);
220
221 netctl = macb_readl(macb, NCR);
222 netctl &= ~MACB_BIT(MPE);
223 macb_writel(macb, NCR, netctl);
224
225 return MACB_BFEXT(DATA, frame);
226}
227
Joe Hershberger1b8c18b2013-06-24 19:06:38 -0500228void __weak arch_get_mdio_control(const char *name)
Shiraz Hashim416ce622012-12-13 17:22:52 +0530229{
230 return;
231}
232
Bo Shenb1a00062013-04-24 15:59:27 +0800233#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Semih Hazar0f751d62009-12-17 15:07:15 +0200234
Joe Hershberger5a49f172016-08-08 11:28:38 -0500235int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
Semih Hazar0f751d62009-12-17 15:07:15 +0200236{
Joe Hershberger5a49f172016-08-08 11:28:38 -0500237 u16 value = 0;
Simon Glassf1dcc192016-05-05 07:28:11 -0600238#ifdef CONFIG_DM_ETH
Joe Hershberger5a49f172016-08-08 11:28:38 -0500239 struct udevice *dev = eth_get_dev_by_name(bus->name);
Simon Glassf1dcc192016-05-05 07:28:11 -0600240 struct macb_device *macb = dev_get_priv(dev);
241#else
Joe Hershberger5a49f172016-08-08 11:28:38 -0500242 struct eth_device *dev = eth_get_dev_by_name(bus->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200243 struct macb_device *macb = to_macb(dev);
Simon Glassf1dcc192016-05-05 07:28:11 -0600244#endif
Semih Hazar0f751d62009-12-17 15:07:15 +0200245
Joe Hershberger5a49f172016-08-08 11:28:38 -0500246 arch_get_mdio_control(bus->name);
Josef Holzmayr7c564082019-10-02 21:22:52 +0200247 value = macb_mdio_read(macb, phy_adr, reg);
Semih Hazar0f751d62009-12-17 15:07:15 +0200248
Joe Hershberger5a49f172016-08-08 11:28:38 -0500249 return value;
Semih Hazar0f751d62009-12-17 15:07:15 +0200250}
251
Joe Hershberger5a49f172016-08-08 11:28:38 -0500252int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
253 u16 value)
Semih Hazar0f751d62009-12-17 15:07:15 +0200254{
Simon Glassf1dcc192016-05-05 07:28:11 -0600255#ifdef CONFIG_DM_ETH
Joe Hershberger5a49f172016-08-08 11:28:38 -0500256 struct udevice *dev = eth_get_dev_by_name(bus->name);
Simon Glassf1dcc192016-05-05 07:28:11 -0600257 struct macb_device *macb = dev_get_priv(dev);
258#else
Joe Hershberger5a49f172016-08-08 11:28:38 -0500259 struct eth_device *dev = eth_get_dev_by_name(bus->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200260 struct macb_device *macb = to_macb(dev);
Simon Glassf1dcc192016-05-05 07:28:11 -0600261#endif
Semih Hazar0f751d62009-12-17 15:07:15 +0200262
Joe Hershberger5a49f172016-08-08 11:28:38 -0500263 arch_get_mdio_control(bus->name);
Josef Holzmayr7c564082019-10-02 21:22:52 +0200264 macb_mdio_write(macb, phy_adr, reg, value);
Semih Hazar0f751d62009-12-17 15:07:15 +0200265
266 return 0;
267}
268#endif
269
Wu, Josh5ae0e382014-05-27 16:31:05 +0800270#define RX 1
271#define TX 0
272static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
273{
274 if (rx)
Heiko Schocher592a7492016-08-29 07:46:11 +0200275 invalidate_dcache_range(macb->rx_ring_dma,
276 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
277 PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800278 else
Heiko Schocher592a7492016-08-29 07:46:11 +0200279 invalidate_dcache_range(macb->tx_ring_dma,
280 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
281 PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800282}
283
284static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
285{
286 if (rx)
287 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200288 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800289 else
290 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200291 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800292}
293
294static inline void macb_flush_rx_buffer(struct macb_device *macb)
295{
296 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
Stefan Roese5ccd6572019-08-26 09:18:11 +0200297 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
298 PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800299}
300
301static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
302{
303 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
Stefan Roese5ccd6572019-08-26 09:18:11 +0200304 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
305 PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800306}
Semih Hazar0f751d62009-12-17 15:07:15 +0200307
Jon Loeliger07d38a12007-07-09 17:30:01 -0500308#if defined(CONFIG_CMD_NET)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100309
Simon Glassd5555b72016-05-05 07:28:09 -0600310static int _macb_send(struct macb_device *macb, const char *name, void *packet,
311 int length)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100312{
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100313 unsigned long paddr, ctrl;
314 unsigned int tx_head = macb->tx_head;
315 int i;
316
317 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
318
319 ctrl = length & TXBUF_FRMLEN_MASK;
Ramon Fried0a2827e2019-07-16 22:04:33 +0300320 ctrl |= MACB_BIT(TX_LAST);
Andreas Bießmannceef9832014-05-26 22:55:18 +0200321 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
Ramon Fried0a2827e2019-07-16 22:04:33 +0300322 ctrl |= MACB_BIT(TX_WRAP);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100323 macb->tx_head = 0;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200324 } else {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100325 macb->tx_head++;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200326 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100327
328 macb->tx_ring[tx_head].ctrl = ctrl;
329 macb->tx_ring[tx_head].addr = paddr;
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200330 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800331 macb_flush_ring_desc(macb, TX);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100332 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
333
334 /*
335 * I guess this is necessary because the networking core may
336 * re-use the transmit buffer as soon as we return...
337 */
Andreas Bießmannceef9832014-05-26 22:55:18 +0200338 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200339 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800340 macb_invalidate_ring_desc(macb, TX);
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200341 ctrl = macb->tx_ring[tx_head].ctrl;
Ramon Fried0a2827e2019-07-16 22:04:33 +0300342 if (ctrl & MACB_BIT(TX_USED))
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100343 break;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100344 udelay(1);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100345 }
346
Masahiro Yamada950c5962020-02-14 16:40:18 +0900347 dma_unmap_single(paddr, length, DMA_TO_DEVICE);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100348
Andreas Bießmannceef9832014-05-26 22:55:18 +0200349 if (i <= MACB_TX_TIMEOUT) {
Ramon Fried0a2827e2019-07-16 22:04:33 +0300350 if (ctrl & MACB_BIT(TX_UNDERRUN))
Simon Glassd5555b72016-05-05 07:28:09 -0600351 printf("%s: TX underrun\n", name);
Ramon Fried0a2827e2019-07-16 22:04:33 +0300352 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
Simon Glassd5555b72016-05-05 07:28:09 -0600353 printf("%s: TX buffers exhausted in mid frame\n", name);
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200354 } else {
Simon Glassd5555b72016-05-05 07:28:09 -0600355 printf("%s: TX timeout\n", name);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100356 }
357
358 /* No one cares anyway */
359 return 0;
360}
361
362static void reclaim_rx_buffers(struct macb_device *macb,
363 unsigned int new_tail)
364{
365 unsigned int i;
366
367 i = macb->rx_tail;
Wu, Josh5ae0e382014-05-27 16:31:05 +0800368
369 macb_invalidate_ring_desc(macb, RX);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100370 while (i > new_tail) {
Ramon Fried0a2827e2019-07-16 22:04:33 +0300371 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100372 i++;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200373 if (i > MACB_RX_RING_SIZE)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100374 i = 0;
375 }
376
377 while (i < new_tail) {
Ramon Fried0a2827e2019-07-16 22:04:33 +0300378 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100379 i++;
380 }
381
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200382 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800383 macb_flush_ring_desc(macb, RX);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100384 macb->rx_tail = new_tail;
385}
386
Simon Glassd5555b72016-05-05 07:28:09 -0600387static int _macb_recv(struct macb_device *macb, uchar **packetp)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100388{
Simon Glassd5555b72016-05-05 07:28:09 -0600389 unsigned int next_rx_tail = macb->next_rx_tail;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100390 void *buffer;
391 int length;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100392 u32 status;
393
Simon Glassd5555b72016-05-05 07:28:09 -0600394 macb->wrapped = false;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100395 for (;;) {
Wu, Josh5ae0e382014-05-27 16:31:05 +0800396 macb_invalidate_ring_desc(macb, RX);
397
Ramon Fried0a2827e2019-07-16 22:04:33 +0300398 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
Simon Glassd5555b72016-05-05 07:28:09 -0600399 return -EAGAIN;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100400
Simon Glassd5555b72016-05-05 07:28:09 -0600401 status = macb->rx_ring[next_rx_tail].ctrl;
Ramon Fried0a2827e2019-07-16 22:04:33 +0300402 if (status & MACB_BIT(RX_SOF)) {
Simon Glassd5555b72016-05-05 07:28:09 -0600403 if (next_rx_tail != macb->rx_tail)
404 reclaim_rx_buffers(macb, next_rx_tail);
405 macb->wrapped = false;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100406 }
407
Ramon Fried0a2827e2019-07-16 22:04:33 +0300408 if (status & MACB_BIT(RX_EOF)) {
Ramon Friedc6d07bf2019-07-14 18:25:14 +0300409 buffer = macb->rx_buffer +
410 macb->rx_buffer_size * macb->rx_tail;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100411 length = status & RXBUF_FRMLEN_MASK;
Wu, Josh5ae0e382014-05-27 16:31:05 +0800412
413 macb_invalidate_rx_buffer(macb);
Simon Glassd5555b72016-05-05 07:28:09 -0600414 if (macb->wrapped) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100415 unsigned int headlen, taillen;
416
Ramon Friedc6d07bf2019-07-14 18:25:14 +0300417 headlen = macb->rx_buffer_size *
418 (MACB_RX_RING_SIZE - macb->rx_tail);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100419 taillen = length - headlen;
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500420 memcpy((void *)net_rx_packets[0],
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100421 buffer, headlen);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500422 memcpy((void *)net_rx_packets[0] + headlen,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100423 macb->rx_buffer, taillen);
Simon Glassd5555b72016-05-05 07:28:09 -0600424 *packetp = (void *)net_rx_packets[0];
425 } else {
426 *packetp = buffer;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100427 }
428
Simon Glassd5555b72016-05-05 07:28:09 -0600429 if (++next_rx_tail >= MACB_RX_RING_SIZE)
430 next_rx_tail = 0;
431 macb->next_rx_tail = next_rx_tail;
432 return length;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100433 } else {
Simon Glassd5555b72016-05-05 07:28:09 -0600434 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
435 macb->wrapped = true;
436 next_rx_tail = 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100437 }
438 }
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200439 barrier();
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100440 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100441}
442
Simon Glassd5555b72016-05-05 07:28:09 -0600443static void macb_phy_reset(struct macb_device *macb, const char *name)
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200444{
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200445 int i;
446 u16 status, adv;
447
448 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200449 macb_mdio_write(macb, macb->phy_addr, MII_ADVERTISE, adv);
Simon Glassd5555b72016-05-05 07:28:09 -0600450 printf("%s: Starting autonegotiation...\n", name);
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200451 macb_mdio_write(macb, macb->phy_addr, MII_BMCR, (BMCR_ANENABLE
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200452 | BMCR_ANRESTART));
453
Andreas Bießmannceef9832014-05-26 22:55:18 +0200454 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200455 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200456 if (status & BMSR_ANEGCOMPLETE)
457 break;
458 udelay(100);
459 }
460
461 if (status & BMSR_ANEGCOMPLETE)
Simon Glassd5555b72016-05-05 07:28:09 -0600462 printf("%s: Autonegotiation complete\n", name);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200463 else
464 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600465 name, status);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200466}
467
Wenyou Yanga212b662016-05-17 13:11:35 +0800468static int macb_phy_find(struct macb_device *macb, const char *name)
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100469{
470 int i;
471 u16 phy_id;
472
473 /* Search for PHY... */
474 for (i = 0; i < 32; i++) {
475 macb->phy_addr = i;
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200476 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100477 if (phy_id != 0xffff) {
Wenyou Yanga212b662016-05-17 13:11:35 +0800478 printf("%s: PHY present at %d\n", name, i);
Wilson Lee4bf56912017-08-22 20:25:07 -0700479 return 0;
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100480 }
481 }
482
483 /* PHY isn't up to snuff */
Wenyou Yanga212b662016-05-17 13:11:35 +0800484 printf("%s: PHY not found\n", name);
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100485
Wilson Lee4bf56912017-08-22 20:25:07 -0700486 return -ENODEV;
487}
488
489/**
490 * macb_linkspd_cb - Linkspeed change callback function
Bin Menga5e3d232019-05-22 00:09:45 -0700491 * @dev/@regs: MACB udevice (DM version) or
492 * Base Register of MACB devices (non-DM version)
Wilson Lee4bf56912017-08-22 20:25:07 -0700493 * @speed: Linkspeed
494 * Returns 0 when operation success and negative errno number
495 * when operation failed.
496 */
Bin Menga5e3d232019-05-22 00:09:45 -0700497#ifdef CONFIG_DM_ETH
Anup Pateld0a04db2019-07-24 04:09:32 +0000498static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
499{
500 fdt_addr_t addr;
501 void *gemgxl_regs;
502
503 addr = dev_read_addr_index(dev, 1);
504 if (addr == FDT_ADDR_T_NONE)
505 return -ENODEV;
506
507 gemgxl_regs = (void __iomem *)addr;
508 if (!gemgxl_regs)
509 return -ENODEV;
510
511 /*
512 * SiFive GEMGXL TX clock operation mode:
513 *
514 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
515 * and output clock on GMII output signal GTX_CLK
516 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
517 */
518 writel(rate != 125000000, gemgxl_regs);
519 return 0;
520}
521
Bin Menga5e3d232019-05-22 00:09:45 -0700522int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
523{
Bin Meng3ef64442019-05-22 00:09:46 -0700524#ifdef CONFIG_CLK
Anup Pateld0a04db2019-07-24 04:09:32 +0000525 struct macb_device *macb = dev_get_priv(dev);
Bin Meng3ef64442019-05-22 00:09:46 -0700526 struct clk tx_clk;
527 ulong rate;
528 int ret;
529
Bin Meng3ef64442019-05-22 00:09:46 -0700530 switch (speed) {
531 case _10BASET:
532 rate = 2500000; /* 2.5 MHz */
533 break;
534 case _100BASET:
535 rate = 25000000; /* 25 MHz */
536 break;
537 case _1000BASET:
538 rate = 125000000; /* 125 MHz */
539 break;
540 default:
541 /* does not change anything */
542 return 0;
543 }
544
Anup Pateld0a04db2019-07-24 04:09:32 +0000545 if (macb->config->clk_init)
546 return macb->config->clk_init(dev, rate);
547
548 /*
549 * "tx_clk" is an optional clock source for MACB.
550 * Ignore if it does not exist in DT.
551 */
552 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
553 if (ret)
554 return 0;
555
Bin Meng3ef64442019-05-22 00:09:46 -0700556 if (tx_clk.dev) {
557 ret = clk_set_rate(&tx_clk, rate);
558 if (ret)
559 return ret;
560 }
561#endif
562
Bin Menga5e3d232019-05-22 00:09:45 -0700563 return 0;
564}
565#else
Wilson Lee4bf56912017-08-22 20:25:07 -0700566int __weak macb_linkspd_cb(void *regs, unsigned int speed)
567{
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100568 return 0;
569}
Bin Menga5e3d232019-05-22 00:09:45 -0700570#endif
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100571
Wenyou Yanga212b662016-05-17 13:11:35 +0800572#ifdef CONFIG_DM_ETH
573static int macb_phy_init(struct udevice *dev, const char *name)
574#else
Simon Glassd5555b72016-05-05 07:28:09 -0600575static int macb_phy_init(struct macb_device *macb, const char *name)
Wenyou Yanga212b662016-05-17 13:11:35 +0800576#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100577{
Wenyou Yanga212b662016-05-17 13:11:35 +0800578#ifdef CONFIG_DM_ETH
579 struct macb_device *macb = dev_get_priv(dev);
580#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100581 u32 ncfgr;
582 u16 phy_id, status, adv, lpa;
583 int media, speed, duplex;
Wilson Lee4bf56912017-08-22 20:25:07 -0700584 int ret;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100585 int i;
586
Simon Glassd5555b72016-05-05 07:28:09 -0600587 arch_get_mdio_control(name);
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100588 /* Auto-detect phy_addr */
Wilson Lee4bf56912017-08-22 20:25:07 -0700589 ret = macb_phy_find(macb, name);
590 if (ret)
591 return ret;
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100592
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100593 /* Check if the PHY is up to snuff... */
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200594 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100595 if (phy_id == 0xffff) {
Simon Glassd5555b72016-05-05 07:28:09 -0600596 printf("%s: No PHY present\n", name);
Wilson Lee4bf56912017-08-22 20:25:07 -0700597 return -ENODEV;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100598 }
599
Bo Shenb1a00062013-04-24 15:59:27 +0800600#ifdef CONFIG_PHYLIB
Wenyou Yanga212b662016-05-17 13:11:35 +0800601#ifdef CONFIG_DM_ETH
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800602 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
Wenyou Yanga212b662016-05-17 13:11:35 +0800603 macb->phy_interface);
604#else
Bo Shen8314ccd2013-08-19 10:35:47 +0800605 /* need to consider other phy interface mode */
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800606 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
Bo Shen8314ccd2013-08-19 10:35:47 +0800607 PHY_INTERFACE_MODE_RGMII);
Wenyou Yanga212b662016-05-17 13:11:35 +0800608#endif
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800609 if (!macb->phydev) {
Bo Shen8314ccd2013-08-19 10:35:47 +0800610 printf("phy_connect failed\n");
611 return -ENODEV;
612 }
613
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800614 phy_config(macb->phydev);
Bo Shenb1a00062013-04-24 15:59:27 +0800615#endif
616
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200617 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100618 if (!(status & BMSR_LSTATUS)) {
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200619 /* Try to re-negotiate if we don't have link already. */
Simon Glassd5555b72016-05-05 07:28:09 -0600620 macb_phy_reset(macb, name);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200621
Andreas Bießmannceef9832014-05-26 22:55:18 +0200622 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200623 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
Stefan Roese7bf9bca2019-03-27 11:20:19 +0100624 if (status & BMSR_LSTATUS) {
625 /*
626 * Delay a bit after the link is established,
627 * so that the next xfer does not fail
628 */
629 mdelay(10);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100630 break;
Stefan Roese7bf9bca2019-03-27 11:20:19 +0100631 }
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200632 udelay(100);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100633 }
634 }
635
636 if (!(status & BMSR_LSTATUS)) {
637 printf("%s: link down (status: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600638 name, status);
Wilson Lee4bf56912017-08-22 20:25:07 -0700639 return -ENETDOWN;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100640 }
Bo Shend256be22013-04-24 15:59:28 +0800641
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100642 /* First check for GMAC and that it is GiB capable */
643 if (gem_is_gigabit_capable(macb)) {
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200644 lpa = macb_mdio_read(macb, macb->phy_addr, MII_STAT1000);
Bo Shend256be22013-04-24 15:59:28 +0800645
Radu Pirea0dc97fc2019-06-07 14:18:36 +0300646 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
647 LPA_1000XHALF)) {
648 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
649 1 : 0);
Andreas Bießmann47609572014-09-18 23:46:48 +0200650
651 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600652 name,
Bo Shend256be22013-04-24 15:59:28 +0800653 duplex ? "full" : "half",
654 lpa);
655
656 ncfgr = macb_readl(macb, NCFGR);
Andreas Bießmann47609572014-09-18 23:46:48 +0200657 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
658 ncfgr |= GEM_BIT(GBE);
659
Bo Shend256be22013-04-24 15:59:28 +0800660 if (duplex)
661 ncfgr |= MACB_BIT(FD);
Andreas Bießmann47609572014-09-18 23:46:48 +0200662
Bo Shend256be22013-04-24 15:59:28 +0800663 macb_writel(macb, NCFGR, ncfgr);
664
Bin Menga5e3d232019-05-22 00:09:45 -0700665#ifdef CONFIG_DM_ETH
666 ret = macb_linkspd_cb(dev, _1000BASET);
667#else
Wilson Lee4bf56912017-08-22 20:25:07 -0700668 ret = macb_linkspd_cb(macb->regs, _1000BASET);
Bin Menga5e3d232019-05-22 00:09:45 -0700669#endif
Wilson Lee4bf56912017-08-22 20:25:07 -0700670 if (ret)
671 return ret;
672
673 return 0;
Bo Shend256be22013-04-24 15:59:28 +0800674 }
675 }
676
677 /* fall back for EMAC checking */
Josef Holzmayr0d3044c2019-10-02 21:22:51 +0200678 adv = macb_mdio_read(macb, macb->phy_addr, MII_ADVERTISE);
679 lpa = macb_mdio_read(macb, macb->phy_addr, MII_LPA);
Bo Shend256be22013-04-24 15:59:28 +0800680 media = mii_nway_result(lpa & adv);
681 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
682 ? 1 : 0);
683 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
684 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600685 name,
Bo Shend256be22013-04-24 15:59:28 +0800686 speed ? "100" : "10",
687 duplex ? "full" : "half",
688 lpa);
689
690 ncfgr = macb_readl(macb, NCFGR);
Bo Shenc83cb5f2015-03-04 13:35:16 +0800691 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
Wilson Lee4bf56912017-08-22 20:25:07 -0700692 if (speed) {
Bo Shend256be22013-04-24 15:59:28 +0800693 ncfgr |= MACB_BIT(SPD);
Bin Menga5e3d232019-05-22 00:09:45 -0700694#ifdef CONFIG_DM_ETH
695 ret = macb_linkspd_cb(dev, _100BASET);
696#else
Wilson Lee4bf56912017-08-22 20:25:07 -0700697 ret = macb_linkspd_cb(macb->regs, _100BASET);
Bin Menga5e3d232019-05-22 00:09:45 -0700698#endif
Wilson Lee4bf56912017-08-22 20:25:07 -0700699 } else {
Bin Menga5e3d232019-05-22 00:09:45 -0700700#ifdef CONFIG_DM_ETH
701 ret = macb_linkspd_cb(dev, _10BASET);
702#else
Wilson Lee4bf56912017-08-22 20:25:07 -0700703 ret = macb_linkspd_cb(macb->regs, _10BASET);
Bin Menga5e3d232019-05-22 00:09:45 -0700704#endif
Wilson Lee4bf56912017-08-22 20:25:07 -0700705 }
706
707 if (ret)
708 return ret;
709
Bo Shend256be22013-04-24 15:59:28 +0800710 if (duplex)
711 ncfgr |= MACB_BIT(FD);
712 macb_writel(macb, NCFGR, ncfgr);
713
Wilson Lee4bf56912017-08-22 20:25:07 -0700714 return 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100715}
716
Wu, Joshade4ea42015-06-03 16:45:44 +0800717static int gmac_init_multi_queues(struct macb_device *macb)
718{
719 int i, num_queues = 1;
720 u32 queue_mask;
721
722 /* bit 0 is never set but queue 0 always exists */
723 queue_mask = gem_readl(macb, DCFG6) & 0xff;
724 queue_mask |= 0x1;
725
726 for (i = 1; i < MACB_MAX_QUEUES; i++)
727 if (queue_mask & (1 << i))
728 num_queues++;
729
Ramon Fried0a2827e2019-07-16 22:04:33 +0300730 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
Wu, Joshade4ea42015-06-03 16:45:44 +0800731 macb->dummy_desc->addr = 0;
732 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200733 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
Wu, Joshade4ea42015-06-03 16:45:44 +0800734
735 for (i = 1; i < num_queues; i++)
736 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
737
738 return 0;
739}
740
Ramon Fried9c295802019-07-16 22:04:36 +0300741static void gmac_configure_dma(struct macb_device *macb)
742{
743 u32 buffer_size;
744 u32 dmacfg;
745
Ramon Friedc6d07bf2019-07-14 18:25:14 +0300746 buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
Ramon Fried9c295802019-07-16 22:04:36 +0300747 dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
748 dmacfg |= GEM_BF(RXBS, buffer_size);
749
Anup Pateld0a04db2019-07-24 04:09:32 +0000750 if (macb->config->dma_burst_length)
751 dmacfg = GEM_BFINS(FBLDO,
752 macb->config->dma_burst_length, dmacfg);
Ramon Fried9c295802019-07-16 22:04:36 +0300753
754 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
755 dmacfg &= ~GEM_BIT(ENDIA_PKT);
756
Anup Pateleff0e0c2019-07-24 04:09:37 +0000757 if (macb->is_big_endian)
Ramon Fried9c295802019-07-16 22:04:36 +0300758 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
Anup Pateleff0e0c2019-07-24 04:09:37 +0000759 else
760 dmacfg &= ~GEM_BIT(ENDIA_DESC);
Ramon Fried9c295802019-07-16 22:04:36 +0300761
762 dmacfg &= ~GEM_BIT(ADDR64);
763 gem_writel(macb, DMACFG, dmacfg);
764}
765
Wenyou Yanga212b662016-05-17 13:11:35 +0800766#ifdef CONFIG_DM_ETH
767static int _macb_init(struct udevice *dev, const char *name)
768#else
Simon Glassd5555b72016-05-05 07:28:09 -0600769static int _macb_init(struct macb_device *macb, const char *name)
Wenyou Yanga212b662016-05-17 13:11:35 +0800770#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100771{
Wenyou Yanga212b662016-05-17 13:11:35 +0800772#ifdef CONFIG_DM_ETH
773 struct macb_device *macb = dev_get_priv(dev);
774#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100775 unsigned long paddr;
Wilson Lee4bf56912017-08-22 20:25:07 -0700776 int ret;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100777 int i;
778
779 /*
780 * macb_halt should have been called at some point before now,
781 * so we'll assume the controller is idle.
782 */
783
784 /* initialize DMA descriptors */
785 paddr = macb->rx_buffer_dma;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200786 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
787 if (i == (MACB_RX_RING_SIZE - 1))
Ramon Fried0a2827e2019-07-16 22:04:33 +0300788 paddr |= MACB_BIT(RX_WRAP);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100789 macb->rx_ring[i].addr = paddr;
790 macb->rx_ring[i].ctrl = 0;
Ramon Friedc6d07bf2019-07-14 18:25:14 +0300791 paddr += macb->rx_buffer_size;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100792 }
Wu, Josh5ae0e382014-05-27 16:31:05 +0800793 macb_flush_ring_desc(macb, RX);
794 macb_flush_rx_buffer(macb);
795
Andreas Bießmannceef9832014-05-26 22:55:18 +0200796 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100797 macb->tx_ring[i].addr = 0;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200798 if (i == (MACB_TX_RING_SIZE - 1))
Ramon Fried0a2827e2019-07-16 22:04:33 +0300799 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
800 MACB_BIT(TX_WRAP);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100801 else
Ramon Fried0a2827e2019-07-16 22:04:33 +0300802 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100803 }
Wu, Josh5ae0e382014-05-27 16:31:05 +0800804 macb_flush_ring_desc(macb, TX);
805
Andreas Bießmannceef9832014-05-26 22:55:18 +0200806 macb->rx_tail = 0;
807 macb->tx_head = 0;
808 macb->tx_tail = 0;
Simon Glassd5555b72016-05-05 07:28:09 -0600809 macb->next_rx_tail = 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100810
Wilson Lee4bf56912017-08-22 20:25:07 -0700811#ifdef CONFIG_MACB_ZYNQ
Michal Simek7f6b0f32020-03-26 15:01:29 +0100812 gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
Wilson Lee4bf56912017-08-22 20:25:07 -0700813#endif
814
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100815 macb_writel(macb, RBQP, macb->rx_ring_dma);
816 macb_writel(macb, TBQP, macb->tx_ring_dma);
817
Bo Shend256be22013-04-24 15:59:28 +0800818 if (macb_is_gem(macb)) {
Ramon Fried9c295802019-07-16 22:04:36 +0300819 /* Initialize DMA properties */
820 gmac_configure_dma(macb);
Wu, Joshade4ea42015-06-03 16:45:44 +0800821 /* Check the multi queue and initialize the queue for tx */
822 gmac_init_multi_queues(macb);
823
Bo Shencabf61c2014-11-10 15:24:01 +0800824 /*
825 * When the GMAC IP with GE feature, this bit is used to
826 * select interface between RGMII and GMII.
827 * When the GMAC IP without GE feature, this bit is used
828 * to select interface between RMII and MII.
829 */
Wenyou Yanga212b662016-05-17 13:11:35 +0800830#ifdef CONFIG_DM_ETH
Wenyou Yang6de046e2017-04-20 11:13:13 +0800831 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
832 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
Ramon Fried6c636512019-07-16 22:03:00 +0300833 gem_writel(macb, USRIO, GEM_BIT(RGMII));
Wenyou Yanga212b662016-05-17 13:11:35 +0800834 else
Ramon Fried6c636512019-07-16 22:03:00 +0300835 gem_writel(macb, USRIO, 0);
Ramon Fried5a1899f2019-07-16 22:04:34 +0300836
837 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
838 unsigned int ncfgr = macb_readl(macb, NCFGR);
839
840 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
841 macb_writel(macb, NCFGR, ncfgr);
842 }
Wenyou Yanga212b662016-05-17 13:11:35 +0800843#else
Bo Shencabf61c2014-11-10 15:24:01 +0800844#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
Ramon Fried6c636512019-07-16 22:03:00 +0300845 gem_writel(macb, USRIO, GEM_BIT(RGMII));
Bo Shend256be22013-04-24 15:59:28 +0800846#else
Ramon Fried6c636512019-07-16 22:03:00 +0300847 gem_writel(macb, USRIO, 0);
Bo Shend256be22013-04-24 15:59:28 +0800848#endif
Wenyou Yanga212b662016-05-17 13:11:35 +0800849#endif
Bo Shend256be22013-04-24 15:59:28 +0800850 } else {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100851 /* choose RMII or MII mode. This depends on the board */
Wenyou Yanga212b662016-05-17 13:11:35 +0800852#ifdef CONFIG_DM_ETH
853#ifdef CONFIG_AT91FAMILY
854 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
855 macb_writel(macb, USRIO,
856 MACB_BIT(RMII) | MACB_BIT(CLKEN));
857 } else {
858 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
859 }
860#else
861 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
862 macb_writel(macb, USRIO, 0);
863 else
864 macb_writel(macb, USRIO, MACB_BIT(MII));
865#endif
866#else
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100867#ifdef CONFIG_RMII
Bo Shend8f64b42013-04-24 15:59:26 +0800868#ifdef CONFIG_AT91FAMILY
Stelian Pop7263ef12008-01-03 21:15:56 +0000869 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
870#else
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100871 macb_writel(macb, USRIO, 0);
Stelian Pop7263ef12008-01-03 21:15:56 +0000872#endif
873#else
Bo Shend8f64b42013-04-24 15:59:26 +0800874#ifdef CONFIG_AT91FAMILY
Stelian Pop7263ef12008-01-03 21:15:56 +0000875 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100876#else
877 macb_writel(macb, USRIO, MACB_BIT(MII));
878#endif
Stelian Pop7263ef12008-01-03 21:15:56 +0000879#endif /* CONFIG_RMII */
Wenyou Yanga212b662016-05-17 13:11:35 +0800880#endif
Bo Shend256be22013-04-24 15:59:28 +0800881 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100882
Wenyou Yanga212b662016-05-17 13:11:35 +0800883#ifdef CONFIG_DM_ETH
Wilson Lee4bf56912017-08-22 20:25:07 -0700884 ret = macb_phy_init(dev, name);
Wenyou Yanga212b662016-05-17 13:11:35 +0800885#else
Wilson Lee4bf56912017-08-22 20:25:07 -0700886 ret = macb_phy_init(macb, name);
Wenyou Yanga212b662016-05-17 13:11:35 +0800887#endif
Wilson Lee4bf56912017-08-22 20:25:07 -0700888 if (ret)
889 return ret;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100890
891 /* Enable TX and RX */
892 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
893
Ben Warren422b1a02008-01-09 18:15:53 -0500894 return 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100895}
896
Simon Glassd5555b72016-05-05 07:28:09 -0600897static void _macb_halt(struct macb_device *macb)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100898{
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100899 u32 ncr, tsr;
900
901 /* Halt the controller and wait for any ongoing transmission to end. */
902 ncr = macb_readl(macb, NCR);
903 ncr |= MACB_BIT(THALT);
904 macb_writel(macb, NCR, ncr);
905
906 do {
907 tsr = macb_readl(macb, TSR);
908 } while (tsr & MACB_BIT(TGO));
909
910 /* Disable TX and RX, and clear statistics */
911 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
912}
913
Simon Glassd5555b72016-05-05 07:28:09 -0600914static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
Ben Warren6bb46792010-06-01 11:55:42 -0700915{
Ben Warren6bb46792010-06-01 11:55:42 -0700916 u32 hwaddr_bottom;
917 u16 hwaddr_top;
918
919 /* set hardware address */
Simon Glassd5555b72016-05-05 07:28:09 -0600920 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
921 enetaddr[2] << 16 | enetaddr[3] << 24;
Ben Warren6bb46792010-06-01 11:55:42 -0700922 macb_writel(macb, SA1B, hwaddr_bottom);
Simon Glassd5555b72016-05-05 07:28:09 -0600923 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
Ben Warren6bb46792010-06-01 11:55:42 -0700924 macb_writel(macb, SA1T, hwaddr_top);
925 return 0;
926}
927
Bo Shend256be22013-04-24 15:59:28 +0800928static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
929{
930 u32 config;
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +0800931#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800932 unsigned long macb_hz = macb->pclk_rate;
933#else
Bo Shend256be22013-04-24 15:59:28 +0800934 unsigned long macb_hz = get_macb_pclk_rate(id);
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800935#endif
Bo Shend256be22013-04-24 15:59:28 +0800936
937 if (macb_hz < 20000000)
938 config = MACB_BF(CLK, MACB_CLK_DIV8);
939 else if (macb_hz < 40000000)
940 config = MACB_BF(CLK, MACB_CLK_DIV16);
941 else if (macb_hz < 80000000)
942 config = MACB_BF(CLK, MACB_CLK_DIV32);
943 else
944 config = MACB_BF(CLK, MACB_CLK_DIV64);
945
946 return config;
947}
948
949static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
950{
951 u32 config;
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800952
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +0800953#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800954 unsigned long macb_hz = macb->pclk_rate;
955#else
Bo Shend256be22013-04-24 15:59:28 +0800956 unsigned long macb_hz = get_macb_pclk_rate(id);
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800957#endif
Bo Shend256be22013-04-24 15:59:28 +0800958
959 if (macb_hz < 20000000)
960 config = GEM_BF(CLK, GEM_CLK_DIV8);
961 else if (macb_hz < 40000000)
962 config = GEM_BF(CLK, GEM_CLK_DIV16);
963 else if (macb_hz < 80000000)
964 config = GEM_BF(CLK, GEM_CLK_DIV32);
965 else if (macb_hz < 120000000)
966 config = GEM_BF(CLK, GEM_CLK_DIV48);
967 else if (macb_hz < 160000000)
968 config = GEM_BF(CLK, GEM_CLK_DIV64);
Ramon Fried9e65f802019-07-16 22:04:32 +0300969 else if (macb_hz < 240000000)
Bo Shend256be22013-04-24 15:59:28 +0800970 config = GEM_BF(CLK, GEM_CLK_DIV96);
Ramon Fried9e65f802019-07-16 22:04:32 +0300971 else if (macb_hz < 320000000)
972 config = GEM_BF(CLK, GEM_CLK_DIV128);
973 else
974 config = GEM_BF(CLK, GEM_CLK_DIV224);
Bo Shend256be22013-04-24 15:59:28 +0800975
976 return config;
977}
978
Bo Shen32e4f6b2013-09-18 15:07:44 +0800979/*
980 * Get the DMA bus width field of the network configuration register that we
981 * should program. We find the width from decoding the design configuration
982 * register to find the maximum supported data bus width.
983 */
984static u32 macb_dbw(struct macb_device *macb)
985{
986 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
987 case 4:
988 return GEM_BF(DBW, GEM_DBW128);
989 case 2:
990 return GEM_BF(DBW, GEM_DBW64);
991 case 1:
992 default:
993 return GEM_BF(DBW, GEM_DBW32);
994 }
995}
996
Simon Glassd5555b72016-05-05 07:28:09 -0600997static void _macb_eth_initialize(struct macb_device *macb)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100998{
Simon Glassd5555b72016-05-05 07:28:09 -0600999 int id = 0; /* This is not used by functions we call */
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001000 u32 ncfgr;
1001
Ramon Friedc6d07bf2019-07-14 18:25:14 +03001002 if (macb_is_gem(macb))
1003 macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
1004 else
1005 macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1006
Simon Glassd5555b72016-05-05 07:28:09 -06001007 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
Ramon Friedc6d07bf2019-07-14 18:25:14 +03001008 macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
1009 MACB_RX_RING_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001010 &macb->rx_buffer_dma);
Wu, Josh5ae0e382014-05-27 16:31:05 +08001011 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001012 &macb->rx_ring_dma);
Wu, Josh5ae0e382014-05-27 16:31:05 +08001013 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001014 &macb->tx_ring_dma);
Wu, Joshade4ea42015-06-03 16:45:44 +08001015 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
1016 &macb->dummy_desc_dma);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001017
Simon Glassd5555b72016-05-05 07:28:09 -06001018 /*
1019 * Do some basic initialization so that we at least can talk
1020 * to the PHY
1021 */
1022 if (macb_is_gem(macb)) {
1023 ncfgr = gem_mdc_clk_div(id, macb);
1024 ncfgr |= macb_dbw(macb);
1025 } else {
1026 ncfgr = macb_mdc_clk_div(id, macb);
1027 }
1028
1029 macb_writel(macb, NCFGR, ncfgr);
1030}
1031
Simon Glassf1dcc192016-05-05 07:28:11 -06001032#ifndef CONFIG_DM_ETH
Simon Glassd5555b72016-05-05 07:28:09 -06001033static int macb_send(struct eth_device *netdev, void *packet, int length)
1034{
1035 struct macb_device *macb = to_macb(netdev);
1036
1037 return _macb_send(macb, netdev->name, packet, length);
1038}
1039
1040static int macb_recv(struct eth_device *netdev)
1041{
1042 struct macb_device *macb = to_macb(netdev);
1043 uchar *packet;
1044 int length;
1045
1046 macb->wrapped = false;
1047 for (;;) {
1048 macb->next_rx_tail = macb->rx_tail;
1049 length = _macb_recv(macb, &packet);
1050 if (length >= 0) {
1051 net_process_received_packet(packet, length);
1052 reclaim_rx_buffers(macb, macb->next_rx_tail);
Heinrich Schuchardt6cdf0722018-03-18 11:32:53 +01001053 } else {
Simon Glassd5555b72016-05-05 07:28:09 -06001054 return length;
1055 }
1056 }
1057}
1058
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +09001059static int macb_init(struct eth_device *netdev, struct bd_info *bd)
Simon Glassd5555b72016-05-05 07:28:09 -06001060{
1061 struct macb_device *macb = to_macb(netdev);
1062
1063 return _macb_init(macb, netdev->name);
1064}
1065
1066static void macb_halt(struct eth_device *netdev)
1067{
1068 struct macb_device *macb = to_macb(netdev);
1069
1070 return _macb_halt(macb);
1071}
1072
1073static int macb_write_hwaddr(struct eth_device *netdev)
1074{
1075 struct macb_device *macb = to_macb(netdev);
1076
1077 return _macb_write_hwaddr(macb, netdev->enetaddr);
1078}
1079
1080int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1081{
1082 struct macb_device *macb;
1083 struct eth_device *netdev;
1084
1085 macb = malloc(sizeof(struct macb_device));
1086 if (!macb) {
1087 printf("Error: Failed to allocate memory for MACB%d\n", id);
1088 return -1;
1089 }
1090 memset(macb, 0, sizeof(struct macb_device));
1091
1092 netdev = &macb->netdev;
Wu, Josh5ae0e382014-05-27 16:31:05 +08001093
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001094 macb->regs = regs;
1095 macb->phy_addr = phy_addr;
1096
Bo Shend256be22013-04-24 15:59:28 +08001097 if (macb_is_gem(macb))
1098 sprintf(netdev->name, "gmac%d", id);
1099 else
1100 sprintf(netdev->name, "macb%d", id);
1101
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001102 netdev->init = macb_init;
1103 netdev->halt = macb_halt;
1104 netdev->send = macb_send;
1105 netdev->recv = macb_recv;
Ben Warren6bb46792010-06-01 11:55:42 -07001106 netdev->write_hwaddr = macb_write_hwaddr;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001107
Simon Glassd5555b72016-05-05 07:28:09 -06001108 _macb_eth_initialize(macb);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001109
1110 eth_register(netdev);
1111
Bo Shenb1a00062013-04-24 15:59:27 +08001112#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Joe Hershberger5a49f172016-08-08 11:28:38 -05001113 int retval;
1114 struct mii_dev *mdiodev = mdio_alloc();
1115 if (!mdiodev)
1116 return -ENOMEM;
1117 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1118 mdiodev->read = macb_miiphy_read;
1119 mdiodev->write = macb_miiphy_write;
1120
1121 retval = mdio_register(mdiodev);
1122 if (retval < 0)
1123 return retval;
Bo Shenb1a00062013-04-24 15:59:27 +08001124 macb->bus = miiphy_get_dev_by_name(netdev->name);
Semih Hazar0f751d62009-12-17 15:07:15 +02001125#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001126 return 0;
1127}
Simon Glassf1dcc192016-05-05 07:28:11 -06001128#endif /* !CONFIG_DM_ETH */
1129
1130#ifdef CONFIG_DM_ETH
1131
1132static int macb_start(struct udevice *dev)
1133{
Wenyou Yanga212b662016-05-17 13:11:35 +08001134 return _macb_init(dev, dev->name);
Simon Glassf1dcc192016-05-05 07:28:11 -06001135}
1136
1137static int macb_send(struct udevice *dev, void *packet, int length)
1138{
1139 struct macb_device *macb = dev_get_priv(dev);
1140
1141 return _macb_send(macb, dev->name, packet, length);
1142}
1143
1144static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1145{
1146 struct macb_device *macb = dev_get_priv(dev);
1147
1148 macb->next_rx_tail = macb->rx_tail;
1149 macb->wrapped = false;
1150
1151 return _macb_recv(macb, packetp);
1152}
1153
1154static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1155{
1156 struct macb_device *macb = dev_get_priv(dev);
1157
1158 reclaim_rx_buffers(macb, macb->next_rx_tail);
1159
1160 return 0;
1161}
1162
1163static void macb_stop(struct udevice *dev)
1164{
1165 struct macb_device *macb = dev_get_priv(dev);
1166
1167 _macb_halt(macb);
1168}
1169
1170static int macb_write_hwaddr(struct udevice *dev)
1171{
1172 struct eth_pdata *plat = dev_get_platdata(dev);
1173 struct macb_device *macb = dev_get_priv(dev);
1174
1175 return _macb_write_hwaddr(macb, plat->enetaddr);
1176}
1177
1178static const struct eth_ops macb_eth_ops = {
1179 .start = macb_start,
1180 .send = macb_send,
1181 .recv = macb_recv,
1182 .stop = macb_stop,
1183 .free_pkt = macb_free_pkt,
1184 .write_hwaddr = macb_write_hwaddr,
1185};
1186
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +08001187#ifdef CONFIG_CLK
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001188static int macb_enable_clk(struct udevice *dev)
1189{
1190 struct macb_device *macb = dev_get_priv(dev);
1191 struct clk clk;
1192 ulong clk_rate;
1193 int ret;
1194
1195 ret = clk_get_by_index(dev, 0, &clk);
1196 if (ret)
1197 return -EINVAL;
1198
Wilson Lee4bf56912017-08-22 20:25:07 -07001199 /*
Anup Patel2e242f52019-02-25 08:14:36 +00001200 * If clock driver didn't support enable or disable then
1201 * we get -ENOSYS from clk_enable(). To handle this, we
1202 * don't fail for ret == -ENOSYS.
Wilson Lee4bf56912017-08-22 20:25:07 -07001203 */
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001204 ret = clk_enable(&clk);
Anup Patel2e242f52019-02-25 08:14:36 +00001205 if (ret && ret != -ENOSYS)
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001206 return ret;
1207
1208 clk_rate = clk_get_rate(&clk);
1209 if (!clk_rate)
1210 return -EINVAL;
1211
1212 macb->pclk_rate = clk_rate;
1213
1214 return 0;
1215}
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +08001216#endif
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001217
Ramon Frieded3c64f2019-07-16 22:04:35 +03001218static const struct macb_config default_gem_config = {
1219 .dma_burst_length = 16,
Anup Pateld0a04db2019-07-24 04:09:32 +00001220 .clk_init = NULL,
Ramon Frieded3c64f2019-07-16 22:04:35 +03001221};
1222
Simon Glassf1dcc192016-05-05 07:28:11 -06001223static int macb_eth_probe(struct udevice *dev)
1224{
1225 struct eth_pdata *pdata = dev_get_platdata(dev);
1226 struct macb_device *macb = dev_get_priv(dev);
Wenyou Yanga212b662016-05-17 13:11:35 +08001227 const char *phy_mode;
Anup Pateld0a04db2019-07-24 04:09:32 +00001228 int ret;
Wenyou Yanga212b662016-05-17 13:11:35 +08001229
Simon Glasse160f7d2017-01-17 16:52:55 -07001230 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1231 NULL);
Wenyou Yanga212b662016-05-17 13:11:35 +08001232 if (phy_mode)
1233 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1234 if (macb->phy_interface == -1) {
1235 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1236 return -EINVAL;
1237 }
Wenyou Yanga212b662016-05-17 13:11:35 +08001238
Simon Glassf1dcc192016-05-05 07:28:11 -06001239 macb->regs = (void *)pdata->iobase;
1240
Anup Pateleff0e0c2019-07-24 04:09:37 +00001241 macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
1242
Anup Pateld0a04db2019-07-24 04:09:32 +00001243 macb->config = (struct macb_config *)dev_get_driver_data(dev);
1244 if (!macb->config)
1245 macb->config = &default_gem_config;
Ramon Frieded3c64f2019-07-16 22:04:35 +03001246
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +08001247#ifdef CONFIG_CLK
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001248 ret = macb_enable_clk(dev);
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001249 if (ret)
1250 return ret;
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +08001251#endif
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001252
Simon Glassf1dcc192016-05-05 07:28:11 -06001253 _macb_eth_initialize(macb);
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001254
Simon Glassf1dcc192016-05-05 07:28:11 -06001255#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001256 macb->bus = mdio_alloc();
1257 if (!macb->bus)
Joe Hershberger5a49f172016-08-08 11:28:38 -05001258 return -ENOMEM;
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001259 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1260 macb->bus->read = macb_miiphy_read;
1261 macb->bus->write = macb_miiphy_write;
Joe Hershberger5a49f172016-08-08 11:28:38 -05001262
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001263 ret = mdio_register(macb->bus);
1264 if (ret < 0)
1265 return ret;
Simon Glassf1dcc192016-05-05 07:28:11 -06001266 macb->bus = miiphy_get_dev_by_name(dev->name);
1267#endif
1268
1269 return 0;
1270}
1271
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001272static int macb_eth_remove(struct udevice *dev)
1273{
1274 struct macb_device *macb = dev_get_priv(dev);
1275
1276#ifdef CONFIG_PHYLIB
1277 free(macb->phydev);
1278#endif
1279 mdio_unregister(macb->bus);
1280 mdio_free(macb->bus);
1281
1282 return 0;
1283}
1284
Wilson Lee4bf56912017-08-22 20:25:07 -07001285/**
1286 * macb_late_eth_ofdata_to_platdata
1287 * @dev: udevice struct
1288 * Returns 0 when operation success and negative errno number
1289 * when operation failed.
1290 */
1291int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1292{
1293 return 0;
1294}
1295
Simon Glassf1dcc192016-05-05 07:28:11 -06001296static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1297{
1298 struct eth_pdata *pdata = dev_get_platdata(dev);
1299
Ramon Fried9043c4e2018-12-27 19:58:42 +02001300 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1301 if (!pdata->iobase)
1302 return -EINVAL;
Wilson Lee4bf56912017-08-22 20:25:07 -07001303
1304 return macb_late_eth_ofdata_to_platdata(dev);
Simon Glassf1dcc192016-05-05 07:28:11 -06001305}
1306
Ramon Frieded3c64f2019-07-16 22:04:35 +03001307static const struct macb_config sama5d4_config = {
1308 .dma_burst_length = 4,
Anup Pateld0a04db2019-07-24 04:09:32 +00001309 .clk_init = NULL,
1310};
1311
1312static const struct macb_config sifive_config = {
1313 .dma_burst_length = 16,
1314 .clk_init = macb_sifive_clk_init,
Ramon Frieded3c64f2019-07-16 22:04:35 +03001315};
1316
Simon Glassf1dcc192016-05-05 07:28:11 -06001317static const struct udevice_id macb_eth_ids[] = {
1318 { .compatible = "cdns,macb" },
Wenyou Yang75460252017-04-14 14:36:05 +08001319 { .compatible = "cdns,at91sam9260-macb" },
Nicolas Ferre39fa4162019-09-27 13:08:32 +00001320 { .compatible = "cdns,sam9x60-macb" },
Wenyou Yang75460252017-04-14 14:36:05 +08001321 { .compatible = "atmel,sama5d2-gem" },
1322 { .compatible = "atmel,sama5d3-gem" },
Ramon Frieded3c64f2019-07-16 22:04:35 +03001323 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
Wilson Lee4bf56912017-08-22 20:25:07 -07001324 { .compatible = "cdns,zynq-gem" },
Anup Pateld0a04db2019-07-24 04:09:32 +00001325 { .compatible = "sifive,fu540-c000-gem",
1326 .data = (ulong)&sifive_config },
Simon Glassf1dcc192016-05-05 07:28:11 -06001327 { }
1328};
1329
1330U_BOOT_DRIVER(eth_macb) = {
1331 .name = "eth_macb",
1332 .id = UCLASS_ETH,
1333 .of_match = macb_eth_ids,
1334 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1335 .probe = macb_eth_probe,
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001336 .remove = macb_eth_remove,
Simon Glassf1dcc192016-05-05 07:28:11 -06001337 .ops = &macb_eth_ops,
1338 .priv_auto_alloc_size = sizeof(struct macb_device),
1339 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1340};
1341#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001342
Jon Loeliger07d38a12007-07-09 17:30:01 -05001343#endif