blob: f6cb708c370fe9aad610d107102839d667927204 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08002/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02003 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08005 */
6
Patrick Delaunaya3ce8d62020-11-06 19:01:56 +01007#define LOG_CATEGORY UCLASS_SERIAL
8
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08009#include <common.h>
Vikas Manochafd03b832017-02-12 10:25:46 -080010#include <clk.h>
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080011#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Patrice Chotardf828fa42018-12-04 14:11:36 +010013#include <reset.h>
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080014#include <serial.h>
Patrick Delaunay215c8be2018-05-17 14:50:42 +020015#include <watchdog.h>
16#include <asm/io.h>
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090017#include <asm/arch/stm32.h>
Patrick Delaunaya3ce8d62020-11-06 19:01:56 +010018#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060019#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060020#include <linux/delay.h>
Patrice Chotardae74de02018-01-12 09:23:49 +010021#include "serial_stm32.h"
Simon Glass336d4612020-02-03 07:36:16 -070022#include <dm/device_compat.h>
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080023
Patrick Delaunay215c8be2018-05-17 14:50:42 +020024static void _stm32_serial_setbrg(fdt_addr_t base,
25 struct stm32_uart_info *uart_info,
26 u32 clock_rate,
27 int baudrate)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080028{
Patrick Delaunay215c8be2018-05-17 14:50:42 +020029 bool stm32f4 = uart_info->stm32f4;
Patrice Chotard27265ce2017-07-18 09:29:08 +020030 u32 int_div, mantissa, fraction, oversampling;
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090031
Patrick Delaunay215c8be2018-05-17 14:50:42 +020032 int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020033
34 if (int_div < 16) {
35 oversampling = 8;
Patrice Chotard60a996b2017-09-27 15:44:50 +020036 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020037 } else {
38 oversampling = 16;
Patrice Chotard60a996b2017-09-27 15:44:50 +020039 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020040 }
41
42 mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
43 fraction = int_div % oversampling;
44
Patrice Chotard60a996b2017-09-27 15:44:50 +020045 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
Patrick Delaunay215c8be2018-05-17 14:50:42 +020046}
47
48static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
49{
Simon Glass8a8d24b2020-12-03 16:55:23 -070050 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrick Delaunay215c8be2018-05-17 14:50:42 +020051
52 _stm32_serial_setbrg(plat->base, plat->uart_info,
53 plat->clock_rate, baudrate);
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080054
55 return 0;
56}
57
Patrice Chotardfbd5c722018-08-03 15:07:39 +020058static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
Patrick Delaunaybc709a42018-05-17 14:50:45 +020059{
Simon Glass8a8d24b2020-12-03 16:55:23 -070060 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrick Delaunaybc709a42018-05-17 14:50:45 +020061 bool stm32f4 = plat->uart_info->stm32f4;
62 u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
63 u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
64 u32 config = 0;
Patrice Chotardfbd5c722018-08-03 15:07:39 +020065 uint parity = SERIAL_GET_PARITY(serial_config);
66 uint bits = SERIAL_GET_BITS(serial_config);
67 uint stop = SERIAL_GET_STOP(serial_config);
Patrick Delaunaybc709a42018-05-17 14:50:45 +020068
Patrice Chotardfbd5c722018-08-03 15:07:39 +020069 /*
70 * only parity config is implemented, check if other serial settings
71 * are the default one.
72 * (STM32F4 serial IP didn't support parity setting)
73 */
74 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
75 return -ENOTSUPP; /* not supported in driver*/
Patrick Delaunaybc709a42018-05-17 14:50:45 +020076
77 clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
78 /* update usart configuration (uart need to be disable)
Patrice Chotardfbd5c722018-08-03 15:07:39 +020079 * PCE: parity check enable
Patrick Delaunaybc709a42018-05-17 14:50:45 +020080 * PS : '0' : Even / '1' : Odd
81 * M[1:0] = '00' : 8 Data bits
82 * M[1:0] = '01' : 9 Data bits with parity
83 */
84 switch (parity) {
85 default:
86 case SERIAL_PAR_NONE:
87 config = 0;
88 break;
89 case SERIAL_PAR_ODD:
90 config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
91 break;
92 case SERIAL_PAR_EVEN:
93 config = USART_CR1_PCE | USART_CR1_M0;
94 break;
95 }
Patrice Chotardfbd5c722018-08-03 15:07:39 +020096
Patrick Delaunaybc709a42018-05-17 14:50:45 +020097 clrsetbits_le32(cr1,
98 USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
99 USART_CR1_M0,
100 config);
101 setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
102
103 return 0;
104}
105
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800106static int stm32_serial_getc(struct udevice *dev)
107{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700108 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrice Chotard60a996b2017-09-27 15:44:50 +0200109 bool stm32f4 = plat->uart_info->stm32f4;
110 fdt_addr_t base = plat->base;
Patrice Chotard7b3b74d2018-04-20 08:59:06 +0200111 u32 isr = readl(base + ISR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800112
Patrice Chotardbe1a6f72018-05-17 14:50:43 +0200113 if ((isr & USART_ISR_RXNE) == 0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800114 return -EAGAIN;
115
Patrick Delaunay132518f2019-07-30 19:16:46 +0200116 if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) {
Patrice Chotard7b3b74d2018-04-20 08:59:06 +0200117 if (!stm32f4)
Patrick Delaunaybc709a42018-05-17 14:50:45 +0200118 setbits_le32(base + ICR_OFFSET,
Patrick Delaunay132518f2019-07-30 19:16:46 +0200119 USART_ICR_PCECF | USART_ICR_ORECF |
120 USART_ICR_FECF);
Patrice Chotard7b3b74d2018-04-20 08:59:06 +0200121 else
122 readl(base + RDR_OFFSET(stm32f4));
123 return -EIO;
124 }
125
Patrice Chotard60a996b2017-09-27 15:44:50 +0200126 return readl(base + RDR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800127}
128
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200129static int _stm32_serial_putc(fdt_addr_t base,
130 struct stm32_uart_info *uart_info,
131 const char c)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800132{
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200133 bool stm32f4 = uart_info->stm32f4;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800134
Patrice Chotardbe1a6f72018-05-17 14:50:43 +0200135 if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800136 return -EAGAIN;
137
Patrice Chotard60a996b2017-09-27 15:44:50 +0200138 writel(c, base + TDR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800139
140 return 0;
141}
142
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200143static int stm32_serial_putc(struct udevice *dev, const char c)
144{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700145 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200146
147 return _stm32_serial_putc(plat->base, plat->uart_info, c);
148}
149
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800150static int stm32_serial_pending(struct udevice *dev, bool input)
151{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700152 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrice Chotard60a996b2017-09-27 15:44:50 +0200153 bool stm32f4 = plat->uart_info->stm32f4;
154 fdt_addr_t base = plat->base;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800155
156 if (input)
Patrice Chotard60a996b2017-09-27 15:44:50 +0200157 return readl(base + ISR_OFFSET(stm32f4)) &
Patrice Chotardbe1a6f72018-05-17 14:50:43 +0200158 USART_ISR_RXNE ? 1 : 0;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800159 else
Patrice Chotard60a996b2017-09-27 15:44:50 +0200160 return readl(base + ISR_OFFSET(stm32f4)) &
Patrice Chotardbe1a6f72018-05-17 14:50:43 +0200161 USART_ISR_TXE ? 0 : 1;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800162}
163
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200164static void _stm32_serial_init(fdt_addr_t base,
165 struct stm32_uart_info *uart_info)
166{
167 bool stm32f4 = uart_info->stm32f4;
168 u8 uart_enable_bit = uart_info->uart_enable_bit;
169
170 /* Disable uart-> enable fifo -> enable uart */
171 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
172 BIT(uart_enable_bit));
173 if (uart_info->has_fifo)
174 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
175 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
176 BIT(uart_enable_bit));
177}
178
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800179static int stm32_serial_probe(struct udevice *dev)
180{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700181 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Patrice Chotard9a212d72017-09-27 15:44:53 +0200182 struct clk clk;
Patrice Chotardf828fa42018-12-04 14:11:36 +0100183 struct reset_ctl reset;
Patrice Chotard9a212d72017-09-27 15:44:53 +0200184 int ret;
Patrice Chotard60a996b2017-09-27 15:44:50 +0200185
186 plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
Vikas Manochafd03b832017-02-12 10:25:46 -0800187
Vikas Manochafd03b832017-02-12 10:25:46 -0800188 ret = clk_get_by_index(dev, 0, &clk);
189 if (ret < 0)
190 return ret;
191
192 ret = clk_enable(&clk);
193 if (ret) {
194 dev_err(dev, "failed to enable clock\n");
195 return ret;
196 }
Vikas Manochafd03b832017-02-12 10:25:46 -0800197
Patrice Chotardf828fa42018-12-04 14:11:36 +0100198 ret = reset_get_by_index(dev, 0, &reset);
199 if (!ret) {
200 reset_assert(&reset);
201 udelay(2);
202 reset_deassert(&reset);
203 }
204
Patrice Chotard27265ce2017-07-18 09:29:08 +0200205 plat->clock_rate = clk_get_rate(&clk);
Patrick Delaunay585289b2019-06-21 15:26:41 +0200206 if (!plat->clock_rate) {
Patrice Chotard27265ce2017-07-18 09:29:08 +0200207 clk_disable(&clk);
Patrick Delaunay585289b2019-06-21 15:26:41 +0200208 return -EINVAL;
Patrice Chotard27265ce2017-07-18 09:29:08 +0200209 };
210
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200211 _stm32_serial_init(plat->base, plat->uart_info);
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800212
213 return 0;
214}
215
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800216static const struct udevice_id stm32_serial_id[] = {
Patrice Chotard6c30f152017-09-27 15:44:52 +0200217 { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
Patrice Chotard2a7ecc52017-09-27 15:44:51 +0200218 { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
219 { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800220 {}
221};
222
Simon Glassd1998a92020-12-03 16:55:21 -0700223static int stm32_serial_of_to_plat(struct udevice *dev)
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800224{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700225 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800226
Masahiro Yamada25484932020-07-17 14:36:48 +0900227 plat->base = dev_read_addr(dev);
Patrice Chotard60a996b2017-09-27 15:44:50 +0200228 if (plat->base == FDT_ADDR_T_NONE)
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800229 return -EINVAL;
230
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800231 return 0;
232}
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800233
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800234static const struct dm_serial_ops stm32_serial_ops = {
235 .putc = stm32_serial_putc,
236 .pending = stm32_serial_pending,
237 .getc = stm32_serial_getc,
238 .setbrg = stm32_serial_setbrg,
Patrice Chotardfbd5c722018-08-03 15:07:39 +0200239 .setconfig = stm32_serial_setconfig
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800240};
241
242U_BOOT_DRIVER(serial_stm32) = {
Patrice Chotardae74de02018-01-12 09:23:49 +0100243 .name = "serial_stm32",
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800244 .id = UCLASS_SERIAL,
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800245 .of_match = of_match_ptr(stm32_serial_id),
Simon Glassd1998a92020-12-03 16:55:21 -0700246 .of_to_plat = of_match_ptr(stm32_serial_of_to_plat),
Simon Glass8a8d24b2020-12-03 16:55:23 -0700247 .plat_auto = sizeof(struct stm32x7_serial_plat),
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800248 .ops = &stm32_serial_ops,
249 .probe = stm32_serial_probe,
Bin Meng46879192018-10-24 06:36:36 -0700250#if !CONFIG_IS_ENABLED(OF_CONTROL)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800251 .flags = DM_FLAG_PRE_RELOC,
Bin Meng46879192018-10-24 06:36:36 -0700252#endif
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800253};
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200254
255#ifdef CONFIG_DEBUG_UART_STM32
256#include <debug_uart.h>
257static inline struct stm32_uart_info *_debug_uart_info(void)
258{
259 struct stm32_uart_info *uart_info;
260
261#if defined(CONFIG_STM32F4)
262 uart_info = &stm32f4_info;
263#elif defined(CONFIG_STM32F7)
264 uart_info = &stm32f7_info;
265#else
266 uart_info = &stm32h7_info;
267#endif
268 return uart_info;
269}
270
271static inline void _debug_uart_init(void)
272{
273 fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
274 struct stm32_uart_info *uart_info = _debug_uart_info();
275
276 _stm32_serial_init(base, uart_info);
277 _stm32_serial_setbrg(base, uart_info,
278 CONFIG_DEBUG_UART_CLOCK,
279 CONFIG_BAUDRATE);
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200280}
281
282static inline void _debug_uart_putc(int c)
283{
284 fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
285 struct stm32_uart_info *uart_info = _debug_uart_info();
286
287 while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
Patrick Delaunay66dba9a2019-04-18 17:32:51 +0200288 ;
Patrick Delaunay215c8be2018-05-17 14:50:42 +0200289}
290
291DEBUG_UART_FUNCS
292#endif