Blame - arch/arm/mach-socfpga/Kconfig - platform/external/u-boot

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Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Dalon Westergreen	f0fb4fa	2017-02-10 17:15:34 -0800	[diff] [blame]	3	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
				4	default 0xa2
				5
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	6	config TARGET_SOCFPGA_ARRIA5
				7	bool
Dinh Nguyen	ed77aeb	2015-12-02 13:31:25 -0600	[diff] [blame]	8	select TARGET_SOCFPGA_GEN5
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	9
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	10	config TARGET_SOCFPGA_ARRIA10
				11	bool
Tien Fong Chee	901af3e	2017-12-05 15:58:03 +0800	[diff] [blame]	12	select ALTERA_SDRAM
Michal Simek	58008cb	2018-07-23 15:55:15 +0200	[diff] [blame]	13	select SPL_BOARD_INIT if SPL
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	14
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	15	config TARGET_SOCFPGA_CYCLONE5
				16	bool
Dinh Nguyen	ed77aeb	2015-12-02 13:31:25 -0600	[diff] [blame]	17	select TARGET_SOCFPGA_GEN5
				18
				19	config TARGET_SOCFPGA_GEN5
				20	bool
Ley Foon Tan	707cd01	2017-04-05 17:32:51 +0800	[diff] [blame]	21	select ALTERA_SDRAM
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	22
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	23	config TARGET_SOCFPGA_STRATIX10
				24	bool
				25	select ARMV8_MULTIENTRY
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	26	select ARMV8_SET_SMPEN
Michal Simek	58008cb	2018-07-23 15:55:15 +0200	[diff] [blame]	27	select ARMV8_SPIN_TABLE
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	28
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	29	choice
				30	prompt "Altera SOCFPGA board select"
Joe Hershberger	a26cd04	2015-05-12 14:46:23 -0500	[diff] [blame]	31	optional
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	32
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	33	config TARGET_SOCFPGA_ARRIA10_SOCDK
				34	bool "Altera SOCFPGA SoCDK (Arria 10)"
				35	select TARGET_SOCFPGA_ARRIA10
				36
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	37	config TARGET_SOCFPGA_ARRIA5_SOCDK
				38	bool "Altera SOCFPGA SoCDK (Arria V)"
				39	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	40
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	41	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				42	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				43	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	44
Marek Vasut	7fb4643	2018-02-24 23:34:00 +0100	[diff] [blame]	45	config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
				46	bool "Devboards DBM-SoC1 (Cyclone V)"
				47	select TARGET_SOCFPGA_CYCLONE5
				48
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	49	config TARGET_SOCFPGA_EBV_SOCRATES
				50	bool "EBV SoCrates (Cyclone V)"
				51	select TARGET_SOCFPGA_CYCLONE5
				52
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	53	config TARGET_SOCFPGA_IS1
				54	bool "IS1 (Cyclone V)"
				55	select TARGET_SOCFPGA_CYCLONE5
				56
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	57	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				58	bool "samtec VIN\|ING FPGA (Cyclone V)"
Tom Rini	e5ec481	2017-01-22 19:43:11 -0500	[diff] [blame]	59	select BOARD_LATE_INIT
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	60	select TARGET_SOCFPGA_CYCLONE5
				61
Marek Vasut	cf0a8da	2016-06-08 02:57:05 +0200	[diff] [blame]	62	config TARGET_SOCFPGA_SR1500
				63	bool "SR1500 (Cyclone V)"
				64	select TARGET_SOCFPGA_CYCLONE5
				65
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	66	config TARGET_SOCFPGA_STRATIX10_SOCDK
				67	bool "Intel SOCFPGA SoCDK (Stratix 10)"
				68	select TARGET_SOCFPGA_STRATIX10
				69
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	70	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				71	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				72	select TARGET_SOCFPGA_CYCLONE5
				73
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	74	config TARGET_SOCFPGA_TERASIC_DE10_NANO
				75	bool "Terasic DE10-Nano (Cyclone V)"
				76	select TARGET_SOCFPGA_CYCLONE5
				77
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	78	config TARGET_SOCFPGA_TERASIC_DE1_SOC
				79	bool "Terasic DE1-SoC (Cyclone V)"
				80	select TARGET_SOCFPGA_CYCLONE5
				81
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	82	config TARGET_SOCFPGA_TERASIC_SOCKIT
				83	bool "Terasic SoCkit (Cyclone V)"
				84	select TARGET_SOCFPGA_CYCLONE5
				85
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	86	endchoice
				87
				88	config SYS_BOARD
Marek Vasut	f089240	2015-08-10 21:24:53 +0200	[diff] [blame]	89	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	90	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	f089240	2015-08-10 21:24:53 +0200	[diff] [blame]	91	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	7fb4643	2018-02-24 23:34:00 +0100	[diff] [blame]	92	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	93	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	94	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	95	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	96	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	97	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	98	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	ae9996c	2015-11-18 11:06:09 +0100	[diff] [blame]	99	default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	100	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	101	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	102
				103	config SYS_VENDOR
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	104	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	105	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	106	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	107	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	7fb4643	2018-02-24 23:34:00 +0100	[diff] [blame]	108	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	109	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	110	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	111	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	112	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	113	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	114	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	115
				116	config SYS_SOC
				117	default "socfpga"
				118
				119	config SYS_CONFIG_NAME
Dinh Nguyen	3cbc7b8	2015-09-22 17:01:32 -0500	[diff] [blame]	120	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	121	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen	3cbc7b8	2015-09-22 17:01:32 -0500	[diff] [blame]	122	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	7fb4643	2018-02-24 23:34:00 +0100	[diff] [blame]	123	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	124	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	125	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	126	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	127	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	128	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	129	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	ae9996c	2015-11-18 11:06:09 +0100	[diff] [blame]	130	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	131	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	132	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	133
				134	endif