blob: 1f30f71d25f8cda5ac77f6a6a9ca07fe9ed38d51 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk71f95112003-06-15 22:40:42 +00002/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00003 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05004 * Andy Fleming
5 *
6 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00007 */
8
9#ifndef _MMC_H_
10#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000011
Andy Fleming272cc702008-10-30 16:41:01 -050012#include <linux/list.h>
Peng Fan3697e592016-09-01 11:13:38 +080013#include <linux/sizes.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000014#include <linux/compiler.h>
Mateusz Zalega07a2d422014-04-30 13:04:15 +020015#include <part.h>
Andy Fleming272cc702008-10-30 16:41:01 -050016
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010017#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
18#define MMC_SUPPORTS_TUNING
19#endif
20#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
21#define MMC_SUPPORTS_TUNING
22#endif
23
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020024/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
25#define SD_VERSION_SD (1U << 31)
26#define MMC_VERSION_MMC (1U << 30)
27
28#define MAKE_SDMMC_VERSION(a, b, c) \
29 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
30#define MAKE_SD_VERSION(a, b, c) \
31 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
32#define MAKE_MMC_VERSION(a, b, c) \
33 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
34
35#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
36 (((u32)(x) >> 16) & 0xff)
37#define EXTRACT_SDMMC_MINOR_VERSION(x) \
38 (((u32)(x) >> 8) & 0xff)
39#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
40 ((u32)(x) & 0xff)
41
42#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
43#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
44#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
45#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
46
47#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
48#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
49#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
50#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
51#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
52#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
53#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
54#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
55#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
Jean-Jacques Hiblotace1bed2018-02-09 12:09:28 +010056#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020057#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
58#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
59#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
Stefan Wahren1a3619c2016-06-16 17:54:06 +000060#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
Andy Fleming272cc702008-10-30 16:41:01 -050061
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020062#define MMC_CAP(mode) (1 << mode)
63#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
64#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
65#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +020066#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
Peng Fan3dd26262018-08-10 14:07:54 +080067#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020068
69#define MMC_MODE_8BIT BIT(30)
70#define MMC_MODE_4BIT BIT(29)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +020071#define MMC_MODE_1BIT BIT(28)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020072#define MMC_MODE_SPI BIT(27)
73
Ɓukasz Majewski62722032012-03-12 22:07:18 +000074
Andy Fleming272cc702008-10-30 16:41:01 -050075#define SD_DATA_4BIT 0x00040000
76
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020077#define IS_SD(x) ((x)->version & SD_VERSION_SD)
Andrew Gabbasov3f2da752015-03-19 07:44:02 -050078#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
Andy Fleming272cc702008-10-30 16:41:01 -050079
80#define MMC_DATA_READ 1
81#define MMC_DATA_WRITE 2
82
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020083#define MMC_CMD_GO_IDLE_STATE 0
84#define MMC_CMD_SEND_OP_COND 1
85#define MMC_CMD_ALL_SEND_CID 2
86#define MMC_CMD_SET_RELATIVE_ADDR 3
87#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050088#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020089#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050090#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020091#define MMC_CMD_SEND_CSD 9
92#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050093#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020094#define MMC_CMD_SEND_STATUS 13
95#define MMC_CMD_SET_BLOCKLEN 16
96#define MMC_CMD_READ_SINGLE_BLOCK 17
97#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +020098#define MMC_CMD_SEND_TUNING_BLOCK 19
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +020099#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200100#define MMC_CMD_SET_BLOCK_COUNT 23
Andy Fleming272cc702008-10-30 16:41:01 -0500101#define MMC_CMD_WRITE_SINGLE_BLOCK 24
102#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +0000103#define MMC_CMD_ERASE_GROUP_START 35
104#define MMC_CMD_ERASE_GROUP_END 36
105#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200106#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +0000107#define MMC_CMD_SPI_READ_OCR 58
108#define MMC_CMD_SPI_CRC_ON_OFF 59
Amar3690d6d2013-04-27 11:42:58 +0530109#define MMC_CMD_RES_MAN 62
110
111#define MMC_CMD62_ARG1 0xefac62ec
112#define MMC_CMD62_ARG2 0xcbaea7
113
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200114
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200115#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -0500116#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200117#define SD_CMD_SEND_IF_COND 8
Otavio Salvadorf022d362015-02-17 10:42:43 -0200118#define SD_CMD_SWITCH_UHS18V 11
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200119
120#define SD_CMD_APP_SET_BUS_WIDTH 6
Peng Fan3697e592016-09-01 11:13:38 +0800121#define SD_CMD_APP_SD_STATUS 13
Lei Wene6f99a52011-06-22 17:03:31 +0000122#define SD_CMD_ERASE_WR_BLK_START 32
123#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200124#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -0500125#define SD_CMD_APP_SEND_SCR 51
126
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200127static inline bool mmc_is_tuning_cmd(uint cmdidx)
128{
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200129 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
130 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200131 return true;
132 return false;
133}
134
Andy Fleming272cc702008-10-30 16:41:01 -0500135/* SCR definitions in different words */
136#define SD_HIGHSPEED_BUSY 0x00020000
137#define SD_HIGHSPEED_SUPPORTED 0x00020000
138
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200139#define UHS_SDR12_BUS_SPEED 0
140#define HIGH_SPEED_BUS_SPEED 1
141#define UHS_SDR25_BUS_SPEED 1
142#define UHS_SDR50_BUS_SPEED 2
143#define UHS_SDR104_BUS_SPEED 3
144#define UHS_DDR50_BUS_SPEED 4
145
146#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
147#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
148#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
149#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
150#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
151
Thomas Chouabe2c932011-04-19 03:48:31 +0000152#define OCR_BUSY 0x80000000
153#define OCR_HCS 0x40000000
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200154#define OCR_S18R 0x1000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000155#define OCR_VOLTAGE_MASK 0x007FFF80
156#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500157
Eric Nelson1aa2d072015-12-07 07:50:01 -0700158#define MMC_ERASE_ARG 0x00000000
159#define MMC_SECURE_ERASE_ARG 0x80000000
160#define MMC_TRIM_ARG 0x00000001
161#define MMC_DISCARD_ARG 0x00000003
162#define MMC_SECURE_TRIM1_ARG 0x80000001
163#define MMC_SECURE_TRIM2_ARG 0x80008000
Lei Wene6f99a52011-06-22 17:03:31 +0000164
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000165#define MMC_STATUS_MASK (~0x0206BF7F)
Andrew Gabbasov6b2221b2014-04-03 04:34:32 -0500166#define MMC_STATUS_SWITCH_ERROR (1 << 7)
Thomas Chouabe2c932011-04-19 03:48:31 +0000167#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
168#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000169#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000170
Jan Kloetzked617c422012-02-05 22:29:12 +0000171#define MMC_STATE_PRG (7 << 9)
172
Andy Fleming272cc702008-10-30 16:41:01 -0500173#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
174#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
175#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
176#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
177#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
178#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
179#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
180#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
181#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
182#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
183#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
184#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
185#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
186#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
187#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
188#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
189#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
190
191#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
192#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
193 addressed by index which are
194 1 in value field */
195#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
196 addressed by index, which are
197 1 in value field */
198#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
199
200#define SD_SWITCH_CHECK 0
201#define SD_SWITCH_SWITCH 1
202
203/*
204 * EXT_CSD fields
205 */
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100206#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
207#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600208#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Markus Niebeld7b29122014-11-18 15:11:42 +0100209#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
Oliver Metz1937e5a2013-10-01 20:32:07 +0200210#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100211#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
Lei Wen0560db12011-10-03 20:35:10 +0000212#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Tom Rini33ace362014-02-07 14:15:20 -0500213#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Tomas Melincd3d4882016-11-25 11:01:03 +0200214#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100215#define EXT_CSD_WR_REL_PARAM 166 /* R */
216#define EXT_CSD_WR_REL_SET 167 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600217#define EXT_CSD_RPMB_MULT 168 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000218#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Amar3690d6d2013-04-27 11:42:58 +0530219#define EXT_CSD_BOOT_BUS_WIDTH 177
Lei Wen0560db12011-10-03 20:35:10 +0000220#define EXT_CSD_PART_CONF 179 /* R/W */
221#define EXT_CSD_BUS_WIDTH 183 /* R/W */
222#define EXT_CSD_HS_TIMING 185 /* R/W */
223#define EXT_CSD_REV 192 /* RO */
224#define EXT_CSD_CARD_TYPE 196 /* RO */
225#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
Stephen Warrenf866a462013-06-11 15:14:01 -0600226#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000227#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000228#define EXT_CSD_BOOT_MULT 226 /* RO */
Tomas Melincd3d4882016-11-25 11:01:03 +0200229#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500230
231/*
232 * EXT_CSD field definitions
233 */
234
Thomas Chouabe2c932011-04-19 03:48:31 +0000235#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
236#define EXT_CSD_CMD_SET_SECURE (1 << 1)
237#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500238
Thomas Chouabe2c932011-04-19 03:48:31 +0000239#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
240#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900241#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
242#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
243#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
244 | EXT_CSD_CARD_TYPE_DDR_1_2V)
Andy Fleming272cc702008-10-30 16:41:01 -0500245
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200246#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
247 /* SDR mode @1.8V I/O */
248#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
249 /* SDR mode @1.2V I/O */
250#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
251 EXT_CSD_CARD_TYPE_HS200_1_2V)
Peng Fan3dd26262018-08-10 14:07:54 +0800252#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
253#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
254#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
255 EXT_CSD_CARD_TYPE_HS400_1_2V)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200256
Andy Fleming272cc702008-10-30 16:41:01 -0500257#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
258#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
259#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900260#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
261#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200262#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200263
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200264#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
265#define EXT_CSD_TIMING_HS 1 /* HS */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200266#define EXT_CSD_TIMING_HS200 2 /* HS200 */
Peng Fan3dd26262018-08-10 14:07:54 +0800267#define EXT_CSD_TIMING_HS400 3 /* HS400 */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200268
Amar3690d6d2013-04-27 11:42:58 +0530269#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
270#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
271#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
272#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
273
274#define EXT_CSD_BOOT_ACK(x) (x << 6)
275#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
276#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
277
Angelo Dureghellobdb60992017-08-01 14:27:10 +0200278#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
279#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
280#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
281
Tom Rini5a99b9d2014-02-05 10:24:22 -0500282#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
283#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
284#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
Amar3690d6d2013-04-27 11:42:58 +0530285
Markus Niebeld7b29122014-11-18 15:11:42 +0100286#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
287
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100288#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
289#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
290
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100291#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
292
293#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
294#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
295
Andy Fleming1de97f92008-10-30 16:31:39 -0500296#define R1_ILLEGAL_COMMAND (1 << 22)
297#define R1_APP_CMD (1 << 5)
298
Andy Fleming272cc702008-10-30 16:41:01 -0500299#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000300#define MMC_RSP_136 (1 << 1) /* 136 bit response */
301#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
302#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
303#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500304
Thomas Chouabe2c932011-04-19 03:48:31 +0000305#define MMC_RSP_NONE (0)
306#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500307#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
308 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000309#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
310#define MMC_RSP_R3 (MMC_RSP_PRESENT)
311#define MMC_RSP_R4 (MMC_RSP_PRESENT)
312#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
313#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
314#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500315
Lei Wenbc897b12011-05-02 16:26:26 +0000316#define MMCPART_NOAVAILABLE (0xff)
317#define PART_ACCESS_MASK (0x7)
318#define PART_SUPPORT (0x1)
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100319#define ENHNCD_SUPPORT (0x2)
Oliver Metz1937e5a2013-10-01 20:32:07 +0200320#define PART_ENH_ATTRIB (0x1f)
wdenk71f95112003-06-15 22:40:42 +0000321
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200322#define MMC_QUIRK_RETRY_SEND_CID BIT(0)
323#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
324
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200325enum mmc_voltage {
326 MMC_SIGNAL_VOLTAGE_000 = 0,
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200327 MMC_SIGNAL_VOLTAGE_120 = 1,
328 MMC_SIGNAL_VOLTAGE_180 = 2,
329 MMC_SIGNAL_VOLTAGE_330 = 4,
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200330};
331
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200332#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
333 MMC_SIGNAL_VOLTAGE_180 |\
334 MMC_SIGNAL_VOLTAGE_330)
335
Simon Glass8bfa1952013-04-03 08:54:30 +0000336/* Maximum block size for MMC */
337#define MMC_MAX_BLOCK_LEN 512
338
Amar3690d6d2013-04-27 11:42:58 +0530339/* The number of MMC physical partitions. These consist of:
340 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
341 */
342#define MMC_NUM_BOOT_PARTITION 2
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200343#define MMC_PART_RPMB 3 /* RPMB partition number */
Amar3690d6d2013-04-27 11:42:58 +0530344
Simon Glasse7ecf7c2015-06-23 15:38:48 -0600345/* Driver model support */
346
347/**
348 * struct mmc_uclass_priv - Holds information about a device used by the uclass
349 */
350struct mmc_uclass_priv {
351 struct mmc *mmc;
352};
353
354/**
355 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
356 *
357 * Provided that the device is already probed and ready for use, this value
358 * will be available.
359 *
360 * @dev: Device
361 * @return associated mmc struct pointer if available, else NULL
362 */
363struct mmc *mmc_get_mmc_dev(struct udevice *dev);
364
365/* End of driver model support */
366
Andy Fleming1de97f92008-10-30 16:31:39 -0500367struct mmc_cid {
368 unsigned long psn;
369 unsigned short oid;
370 unsigned char mid;
371 unsigned char prv;
372 unsigned char mdt;
373 char pnm[7];
374};
375
Andy Fleming272cc702008-10-30 16:41:01 -0500376struct mmc_cmd {
377 ushort cmdidx;
378 uint resp_type;
379 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530380 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500381};
382
383struct mmc_data {
384 union {
385 char *dest;
386 const char *src; /* src buffers don't get written to */
387 };
388 uint flags;
389 uint blocks;
390 uint blocksize;
391};
392
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200393/* forward decl. */
394struct mmc;
395
Simon Glasse7881d82017-07-29 11:35:31 -0600396#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass8ca51e52016-06-12 23:30:22 -0600397struct dm_mmc_ops {
398 /**
399 * send_cmd() - Send a command to the MMC device
400 *
401 * @dev: Device to receive the command
402 * @cmd: Command to send
403 * @data: Additional data to send/receive
404 * @return 0 if OK, -ve on error
405 */
406 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
407 struct mmc_data *data);
408
409 /**
410 * set_ios() - Set the I/O speed/width for an MMC device
411 *
412 * @dev: Device to update
413 * @return 0 if OK, -ve on error
414 */
415 int (*set_ios)(struct udevice *dev);
416
417 /**
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +0200418 * send_init_stream() - send the initialization stream: 74 clock cycles
419 * This is used after power up before sending the first command
420 *
421 * @dev: Device to update
422 */
423 void (*send_init_stream)(struct udevice *dev);
424
425 /**
Simon Glass8ca51e52016-06-12 23:30:22 -0600426 * get_cd() - See whether a card is present
427 *
428 * @dev: Device to check
429 * @return 0 if not present, 1 if present, -ve on error
430 */
431 int (*get_cd)(struct udevice *dev);
432
433 /**
434 * get_wp() - See whether a card has write-protect enabled
435 *
436 * @dev: Device to check
437 * @return 0 if write-enabled, 1 if write-protected, -ve on error
438 */
439 int (*get_wp)(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200440
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100441#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200442 /**
443 * execute_tuning() - Start the tuning process
444 *
445 * @dev: Device to start the tuning
446 * @opcode: Command opcode to send
447 * @return 0 if OK, -ve on error
448 */
449 int (*execute_tuning)(struct udevice *dev, uint opcode);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100450#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200451
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100452#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200453 /**
454 * wait_dat0() - wait until dat0 is in the target state
455 * (CLK must be running during the wait)
456 *
457 * @dev: Device to check
458 * @state: target state
459 * @timeout: timeout in us
460 * @return 0 if dat0 is in the target state, -ve on error
461 */
462 int (*wait_dat0)(struct udevice *dev, int state, int timeout);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100463#endif
Simon Glass8ca51e52016-06-12 23:30:22 -0600464};
465
466#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
467
468int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
469 struct mmc_data *data);
470int dm_mmc_set_ios(struct udevice *dev);
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +0200471void dm_mmc_send_init_stream(struct udevice *dev);
Simon Glass8ca51e52016-06-12 23:30:22 -0600472int dm_mmc_get_cd(struct udevice *dev);
473int dm_mmc_get_wp(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200474int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200475int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
Simon Glass8ca51e52016-06-12 23:30:22 -0600476
477/* Transition functions for compatibility */
478int mmc_set_ios(struct mmc *mmc);
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +0200479void mmc_send_init_stream(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600480int mmc_getcd(struct mmc *mmc);
481int mmc_getwp(struct mmc *mmc);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200482int mmc_execute_tuning(struct mmc *mmc, uint opcode);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200483int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
Simon Glass8ca51e52016-06-12 23:30:22 -0600484
485#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200486struct mmc_ops {
487 int (*send_cmd)(struct mmc *mmc,
488 struct mmc_cmd *cmd, struct mmc_data *data);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900489 int (*set_ios)(struct mmc *mmc);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200490 int (*init)(struct mmc *mmc);
491 int (*getcd)(struct mmc *mmc);
492 int (*getwp)(struct mmc *mmc);
493};
Simon Glass8ca51e52016-06-12 23:30:22 -0600494#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200495
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200496struct mmc_config {
497 const char *name;
Simon Glasse7881d82017-07-29 11:35:31 -0600498#if !CONFIG_IS_ENABLED(DM_MMC)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200499 const struct mmc_ops *ops;
Simon Glass8ca51e52016-06-12 23:30:22 -0600500#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200501 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500502 uint voltages;
Andy Fleming272cc702008-10-30 16:41:01 -0500503 uint f_min;
504 uint f_max;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200505 uint b_max;
506 unsigned char part_type;
507};
508
Peng Fan3697e592016-09-01 11:13:38 +0800509struct sd_ssr {
510 unsigned int au; /* In sectors */
511 unsigned int erase_timeout; /* In milliseconds */
512 unsigned int erase_offset; /* In milliseconds */
513};
514
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200515enum bus_mode {
516 MMC_LEGACY,
517 SD_LEGACY,
518 MMC_HS,
519 SD_HS,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100520 MMC_HS_52,
521 MMC_DDR_52,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200522 UHS_SDR12,
523 UHS_SDR25,
524 UHS_SDR50,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200525 UHS_DDR50,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100526 UHS_SDR104,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200527 MMC_HS_200,
Peng Fan3dd26262018-08-10 14:07:54 +0800528 MMC_HS_400,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200529 MMC_MODES_END
530};
531
532const char *mmc_mode_name(enum bus_mode mode);
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +0200533void mmc_dump_capabilities(const char *text, uint caps);
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200534
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200535static inline bool mmc_is_mode_ddr(enum bus_mode mode)
536{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100537 if (mode == MMC_DDR_52)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200538 return true;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100539#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
540 else if (mode == UHS_DDR50)
541 return true;
542#endif
Peng Fan3dd26262018-08-10 14:07:54 +0800543#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
544 else if (mode == MMC_HS_400)
545 return true;
546#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200547 else
548 return false;
549}
550
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200551#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
552 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
553 MMC_CAP(UHS_DDR50))
554
555static inline bool supports_uhs(uint caps)
556{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100557#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200558 return (caps & UHS_CAPS) ? true : false;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100559#else
560 return false;
561#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200562}
563
Simon Glass8ca51e52016-06-12 23:30:22 -0600564/*
565 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
566 * with mmc_get_mmc_dev().
567 *
568 * TODO struct mmc should be in mmc_private but it's hard to fix right now
569 */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200570struct mmc {
Simon Glassc4d660d2017-07-04 13:31:19 -0600571#if !CONFIG_IS_ENABLED(BLK)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200572 struct list_head link;
Simon Glass33fb2112016-05-01 13:52:41 -0600573#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200574 const struct mmc_config *cfg; /* provided configuration */
575 uint version;
576 void *priv;
577 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500578 int high_capacity;
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200579 bool clk_disable; /* true if the clock can be turned off */
Andy Fleming272cc702008-10-30 16:41:01 -0500580 uint bus_width;
581 uint clock;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200582 enum mmc_voltage signal_voltage;
Andy Fleming272cc702008-10-30 16:41:01 -0500583 uint card_caps;
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +0200584 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500585 uint ocr;
Markus Niebelab711882013-12-16 13:40:46 +0100586 uint dsr;
587 uint dsr_imp;
Andy Fleming272cc702008-10-30 16:41:01 -0500588 uint scr[2];
589 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530590 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500591 ushort rca;
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100592 u8 part_support;
593 u8 part_attr;
Diego Santa Cruz9e41a002014-12-23 10:50:33 +0100594 u8 wr_rel_set;
Tom Rini7ca0d3d2017-05-10 15:20:16 -0400595 u8 part_config;
Andy Fleming272cc702008-10-30 16:41:01 -0500596 uint tran_speed;
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200597 uint legacy_speed; /* speed for the legacy mode provided by the card */
Andy Fleming272cc702008-10-30 16:41:01 -0500598 uint read_bl_len;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100599#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Fleming272cc702008-10-30 16:41:01 -0500600 uint write_bl_len;
Diego Santa Cruza4ff9f82014-12-23 10:50:24 +0100601 uint erase_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100602#endif
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100603#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruz037dc0a2014-12-23 10:50:25 +0100604 uint hc_wp_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100605#endif
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100606#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fan3697e592016-09-01 11:13:38 +0800607 struct sd_ssr ssr; /* SD status register */
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100608#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500609 u64 capacity;
Stephen Warrenf866a462013-06-11 15:14:01 -0600610 u64 capacity_user;
611 u64 capacity_boot;
612 u64 capacity_rpmb;
613 u64 capacity_gp[4];
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100614#ifndef CONFIG_SPL_BUILD
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100615 u64 enh_user_start;
616 u64 enh_user_size;
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100617#endif
Simon Glassc4d660d2017-07-04 13:31:19 -0600618#if !CONFIG_IS_ENABLED(BLK)
Simon Glass4101f682016-02-29 15:25:34 -0700619 struct blk_desc block_dev;
Simon Glass33fb2112016-05-01 13:52:41 -0600620#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +0000621 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
622 char init_in_progress; /* 1 if we have done mmc_start_init() */
623 char preinit; /* start init as early as possible */
Andrew Gabbasov786e8f82014-12-01 06:59:09 -0600624 int ddr_mode;
Simon Glassc4d660d2017-07-04 13:31:19 -0600625#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glasscffe5d82016-05-01 13:52:34 -0600626 struct udevice *dev; /* Device for this MMC controller */
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +0200627#if CONFIG_IS_ENABLED(DM_REGULATOR)
628 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
629 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
630#endif
Simon Glasscffe5d82016-05-01 13:52:34 -0600631#endif
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +0200632 u8 *ext_csd;
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200633 u32 cardtype; /* cardtype read from the MMC */
634 enum mmc_voltage current_voltage;
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200635 enum bus_mode selected_mode; /* mode currently used */
636 enum bus_mode best_mode; /* best mode is the supported mode with the
637 * highest bandwidth. It may not always be the
638 * operating mode due to limitations when
639 * accessing the boot partitions
640 */
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200641 u32 quirks;
Andy Fleming272cc702008-10-30 16:41:01 -0500642};
643
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100644struct mmc_hwpart_conf {
645 struct {
646 uint enh_start; /* in 512-byte sectors */
647 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100648 unsigned wr_rel_change : 1;
649 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100650 } user;
651 struct {
652 uint size; /* in 512-byte sectors */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100653 unsigned enhanced : 1;
654 unsigned wr_rel_change : 1;
655 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100656 } gp_part[4];
657};
658
659enum mmc_hwpart_conf_mode {
660 MMC_HWPART_CONF_CHECK,
661 MMC_HWPART_CONF_SET,
662 MMC_HWPART_CONF_COMPLETE,
663};
664
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200665struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
Simon Glassad27dd52016-05-01 13:52:40 -0600666
667/**
668 * mmc_bind() - Set up a new MMC device ready for probing
669 *
670 * A child block device is bound with the IF_TYPE_MMC interface type. This
671 * allows the device to be used with CONFIG_BLK
672 *
673 * @dev: MMC device to set up
674 * @mmc: MMC struct
675 * @cfg: MMC configuration
676 * @return 0 if OK, -ve on error
677 */
678int mmc_bind(struct udevice *dev, struct mmc *mmc,
679 const struct mmc_config *cfg);
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200680void mmc_destroy(struct mmc *mmc);
Simon Glassad27dd52016-05-01 13:52:40 -0600681
682/**
683 * mmc_unbind() - Unbind a MMC device's child block device
684 *
685 * @dev: MMC device
686 * @return 0 if OK, -ve on error
687 */
688int mmc_unbind(struct udevice *dev);
Andy Fleming272cc702008-10-30 16:41:01 -0500689int mmc_initialize(bd_t *bis);
690int mmc_init(struct mmc *mmc);
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200691int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100692
Marek Vasutfceea992019-01-29 04:45:51 +0100693#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
694 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
695 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
696int mmc_deinit(struct mmc *mmc);
697#endif
698
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100699/**
700 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
701 *
702 * @dev: MMC device
703 * @cfg: MMC configuration
704 * @return 0 if OK, -ve on error
705 */
706int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
707
Andy Fleming272cc702008-10-30 16:41:01 -0500708int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200709
710/**
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200711 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
712 *
713 * @voltage: The mmc_voltage to convert
714 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
715 */
716int mmc_voltage_to_mv(enum mmc_voltage voltage);
717
718/**
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200719 * mmc_set_clock() - change the bus clock
720 * @mmc: MMC struct
721 * @clock: bus frequency in Hz
722 * @disable: flag indicating if the clock must on or off
723 * @return 0 if OK, -ve on error
724 */
725int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
726
Jaehoon Chung65117182018-01-26 19:25:29 +0900727#define MMC_CLK_ENABLE false
728#define MMC_CLK_DISABLE true
729
Andy Fleming272cc702008-10-30 16:41:01 -0500730struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700731int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500732void print_mmc_devices(char separator);
Kever Yang46683f32016-07-22 17:22:50 +0800733
734/**
735 * get_mmc_num() - get the total MMC device number
736 *
737 * @return 0 if there is no MMC device, else the number of devices
738 */
Lei Wenea6ebe22011-05-02 16:26:25 +0000739int get_mmc_num(void);
Marek Vasutb5b838f2016-12-01 02:06:33 +0100740int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100741int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
742 enum mmc_hwpart_conf_mode mode);
Simon Glass8ca51e52016-06-12 23:30:22 -0600743
Simon Glasse7881d82017-07-29 11:35:31 -0600744#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Reding48972d92012-01-02 01:15:37 +0000745int mmc_getcd(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200746int board_mmc_getcd(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000747int mmc_getwp(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200748int board_mmc_getwp(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600749#endif
750
Markus Niebelab711882013-12-16 13:40:46 +0100751int mmc_set_dsr(struct mmc *mmc, u16 val);
Amar3690d6d2013-04-27 11:42:58 +0530752/* Function to change the size of boot partition and rpmb partitions */
753int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
754 unsigned long rpmbsize);
Tom Rini792970b2014-02-05 10:24:21 -0500755/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
756int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
Tom Rini5a99b9d2014-02-05 10:24:22 -0500757/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
758int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
Tom Rini33ace362014-02-07 14:15:20 -0500759/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
760int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200761/* Functions to read / write the RPMB partition */
762int mmc_rpmb_set_key(struct mmc *mmc, void *key);
763int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
764int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
765 unsigned short cnt, unsigned char *key);
766int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
767 unsigned short cnt, unsigned char *key);
Jens Wiklander4853ad32018-09-25 16:40:08 +0200768
769/**
770 * mmc_rpmb_route_frames() - route RPMB data frames
771 * @mmc Pointer to a MMC device struct
772 * @req Request data frames
773 * @reqlen Length of data frames in bytes
774 * @rsp Supplied buffer for response data frames
775 * @rsplen Length of supplied buffer for response data frames
776 *
777 * The RPMB data frames are routed to/from some external entity, for
778 * example a Trusted Exectuion Environment in an arm TrustZone protected
779 * secure world. It's expected that it's the external entity who is in
780 * control of the RPMB key.
781 *
782 * Returns 0 on success, < 0 on error.
783 */
784int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
785 void *rsp, unsigned long rsplen);
786
Tomas Melincd3d4882016-11-25 11:01:03 +0200787#ifdef CONFIG_CMD_BKOPS_ENABLE
788int mmc_set_bkops_enable(struct mmc *mmc);
789#endif
790
Che-Liang Chioue9550442012-11-28 15:21:13 +0000791/**
792 * Start device initialization and return immediately; it does not block on
Jon Nettleton6c09eba2018-06-11 15:26:19 +0300793 * polling OCR (operation condition register) status. Useful for checking
794 * the presence of SD/eMMC when no card detect logic is available.
795 *
796 * @param mmc Pointer to a MMC device struct
797 * @return 0 on success, <0 on error.
798 */
799int mmc_get_op_cond(struct mmc *mmc);
800
801/**
802 * Start device initialization and return immediately; it does not block on
Che-Liang Chioue9550442012-11-28 15:21:13 +0000803 * polling OCR (operation condition register) status. Then you should call
804 * mmc_init, which would block on polling OCR status and complete the device
805 * initializatin.
806 *
807 * @param mmc Pointer to a MMC device struct
Baruch Siach31d95002018-06-11 15:26:18 +0300808 * @return 0 on success, <0 on error.
Che-Liang Chioue9550442012-11-28 15:21:13 +0000809 */
810int mmc_start_init(struct mmc *mmc);
811
812/**
813 * Set preinit flag of mmc device.
814 *
815 * This will cause the device to be pre-inited during mmc_initialize(),
816 * which may save boot time if the device is not accessed until later.
817 * Some eMMC devices take 200-300ms to init, but unfortunately they
818 * must be sent a series of commands to even get them to start preparing
819 * for operation.
820 *
821 * @param mmc Pointer to a MMC device struct
822 * @param preinit preinit flag value
823 */
824void mmc_set_preinit(struct mmc *mmc, int preinit);
825
Paul Burton8687d5c2013-09-04 16:12:26 +0100826#ifdef CONFIG_MMC_SPI
Tom Rini0b2da7e2014-03-28 16:55:29 -0400827#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
Paul Burton8687d5c2013-09-04 16:12:26 +0100828#else
829#define mmc_host_is_spi(mmc) 0
830#endif
Thomas Choud52ebf12010-12-24 13:12:21 +0000831struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200832
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +0100833void board_mmc_power_init(void);
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200834int board_mmc_init(bd_t *bis);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200835int cpu_mmc_init(bd_t *bis);
Jeroen Hofsteeaeb80552014-10-08 22:58:05 +0200836int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
Rajesh Bhagat43d17c42019-01-12 07:30:51 +0000837# ifdef CONFIG_SYS_MMC_ENV_PART
838extern uint mmc_get_env_part(struct mmc *mmc);
839# endif
Clemens Gruberaa844fe2016-01-26 16:20:38 +0100840int mmc_get_env_dev(void);
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200841
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200842/* Set block count limit because of 16 bit register limit on some hardware*/
843#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
844#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
845#endif
846
Simon Glasscb5ec332016-05-01 13:52:27 -0600847/**
848 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
849 *
850 * @mmc: MMC device
851 * @return block device if found, else NULL
852 */
853struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
854
wdenk71f95112003-06-15 22:40:42 +0000855#endif /* _MMC_H_ */