Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (c) 2018 Microsemi Corporation |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 4d72caa | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 7 | #include <image.h> |
Simon Glass | 5255932 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame^] | 9 | #include <log.h> |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 10 | #include <asm/io.h> |
| 11 | #include <asm/addrspace.h> |
| 12 | #include <asm/types.h> |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 13 | #include <spi.h> |
Lars Povlsen | 4deb096 | 2019-01-02 09:52:26 +0100 | [diff] [blame] | 14 | #include <led.h> |
Gregory CLEMENT | 2f8d067 | 2019-01-17 17:07:14 +0100 | [diff] [blame] | 15 | #include <wait_bit.h> |
Horatiu Vultur | 06d270c | 2019-04-24 11:27:58 +0200 | [diff] [blame] | 16 | #include <miiphy.h> |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
Lars Povlsen | e9f1492 | 2018-12-20 09:56:05 +0100 | [diff] [blame] | 20 | enum { |
| 21 | BOARD_TYPE_PCB120 = 0xAABBCC00, |
| 22 | BOARD_TYPE_PCB123, |
| 23 | }; |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 24 | |
Gregory CLEMENT | 2f8d067 | 2019-01-17 17:07:14 +0100 | [diff] [blame] | 25 | void mscc_switch_reset(bool enter) |
| 26 | { |
| 27 | /* Nasty workaround to avoid GPIO19 (DDR!) being reset */ |
| 28 | mscc_gpio_set_alternate(19, 2); |
| 29 | |
| 30 | debug("applying SwC reset\n"); |
| 31 | |
| 32 | writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); |
| 33 | writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); |
| 34 | |
| 35 | if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST, |
| 36 | PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false)) |
| 37 | pr_err("Tiemout while waiting for switch reset\n"); |
| 38 | |
| 39 | /* |
| 40 | * Reset GPIO19 mode back as regular GPIO, output, high (DDR |
| 41 | * not reset) (Order is important) |
| 42 | */ |
| 43 | setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); |
| 44 | writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); |
| 45 | mscc_gpio_set_alternate(19, 0); |
| 46 | } |
| 47 | |
Horatiu Vultur | 06d270c | 2019-04-24 11:27:58 +0200 | [diff] [blame] | 48 | int board_phy_config(struct phy_device *phydev) |
| 49 | { |
| 50 | if (gd->board_type == BOARD_TYPE_PCB123) |
| 51 | return 0; |
| 52 | |
| 53 | phy_write(phydev, 0, 31, 0x10); |
| 54 | phy_write(phydev, 0, 18, 0x80F0); |
| 55 | while (phy_read(phydev, 0, 18) & 0x8000) |
| 56 | ; |
| 57 | phy_write(phydev, 0, 31, 0); |
| 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 62 | void board_debug_uart_init(void) |
| 63 | { |
| 64 | /* too early for the pinctrl driver, so configure the UART pins here */ |
Lars Povlsen | e9f1492 | 2018-12-20 09:56:05 +0100 | [diff] [blame] | 65 | mscc_gpio_set_alternate(6, 1); |
| 66 | mscc_gpio_set_alternate(7, 1); |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | int board_early_init_r(void) |
| 70 | { |
| 71 | /* Prepare SPI controller to be used in master mode */ |
| 72 | writel(0, BASE_CFG + ICPU_SW_MODE); |
| 73 | clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, |
| 74 | ICPU_GENERAL_CTRL_IF_SI_OWNER_M, |
| 75 | ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); |
| 76 | |
| 77 | /* Address of boot parameters */ |
| 78 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; |
Lars Povlsen | 4deb096 | 2019-01-02 09:52:26 +0100 | [diff] [blame] | 79 | |
| 80 | /* LED setup */ |
| 81 | if (IS_ENABLED(CONFIG_LED)) |
| 82 | led_default_state(); |
| 83 | |
Gregory CLEMENT | 6787c1e | 2018-12-14 16:16:49 +0100 | [diff] [blame] | 84 | return 0; |
| 85 | } |
Lars Povlsen | e9f1492 | 2018-12-20 09:56:05 +0100 | [diff] [blame] | 86 | |
| 87 | static void do_board_detect(void) |
| 88 | { |
| 89 | u16 dummy = 0; |
| 90 | |
| 91 | /* Enable MIIM */ |
| 92 | mscc_gpio_set_alternate(14, 1); |
| 93 | mscc_gpio_set_alternate(15, 1); |
| 94 | if (mscc_phy_rd(1, 0, 0, &dummy) == 0) |
| 95 | gd->board_type = BOARD_TYPE_PCB120; |
| 96 | else |
| 97 | gd->board_type = BOARD_TYPE_PCB123; |
| 98 | } |
| 99 | |
| 100 | #if defined(CONFIG_MULTI_DTB_FIT) |
| 101 | int board_fit_config_name_match(const char *name) |
| 102 | { |
| 103 | if (gd->board_type == BOARD_TYPE_PCB120 && |
| 104 | strcmp(name, "ocelot_pcb120") == 0) |
| 105 | return 0; |
| 106 | |
| 107 | if (gd->board_type == BOARD_TYPE_PCB123 && |
| 108 | strcmp(name, "ocelot_pcb123") == 0) |
| 109 | return 0; |
| 110 | |
| 111 | return -1; |
| 112 | } |
| 113 | #endif |
| 114 | |
| 115 | #if defined(CONFIG_DTB_RESELECT) |
| 116 | int embedded_dtb_select(void) |
| 117 | { |
| 118 | do_board_detect(); |
| 119 | fdtdec_setup(); |
| 120 | |
| 121 | return 0; |
| 122 | } |
| 123 | #endif |