Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2009 |
| 4 | * Marvell Semiconductor <www.marvell.com> |
| 5 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
| 6 | * |
| 7 | * (C) Copyright 2003 |
| 8 | * Ingo Assmus <ingo.assmus@keymile.com> |
| 9 | * |
| 10 | * based on - Driver for MV64360X ethernet ports |
| 11 | * Copyright (C) 2002 rabeeh@galileo.co.il |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <common.h> |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 15 | #include <dm.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame^] | 16 | #include <log.h> |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 17 | #include <net.h> |
| 18 | #include <malloc.h> |
| 19 | #include <miiphy.h> |
Chris Packham | 5194ed7 | 2018-06-09 20:46:16 +1200 | [diff] [blame] | 20 | #include <wait_bit.h> |
Lei Wen | a7efd71 | 2011-10-18 20:11:42 +0530 | [diff] [blame] | 21 | #include <asm/io.h> |
Masahiro Yamada | 1221ce4 | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 22 | #include <linux/errno.h> |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 23 | #include <asm/types.h> |
Lei Wen | a7efd71 | 2011-10-18 20:11:42 +0530 | [diff] [blame] | 24 | #include <asm/system.h> |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 25 | #include <asm/byteorder.h> |
Anatolij Gustschin | 36aaa91 | 2011-10-29 10:09:22 +0000 | [diff] [blame] | 26 | #include <asm/arch/cpu.h> |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 27 | |
Trevor Woerner | bb0fb4c | 2020-05-06 08:02:40 -0400 | [diff] [blame] | 28 | #if defined(CONFIG_ARCH_KIRKWOOD) |
Stefan Roese | 3dc23f7 | 2014-10-22 12:13:06 +0200 | [diff] [blame] | 29 | #include <asm/arch/soc.h> |
Trevor Woerner | b16a331 | 2020-05-06 08:02:38 -0400 | [diff] [blame] | 30 | #elif defined(CONFIG_ARCH_ORION5X) |
Albert Aribaud | d3c9ffd | 2010-07-12 22:24:29 +0200 | [diff] [blame] | 31 | #include <asm/arch/orion5x.h> |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 32 | #endif |
| 33 | |
Albert Aribaud | 9b6bcdc | 2010-07-12 22:24:27 +0200 | [diff] [blame] | 34 | #include "mvgbe.h" |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 35 | |
Albert Aribaud | 49fa6ed | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | |
Luka Perkov | 5aa2297 | 2013-11-11 07:27:53 +0100 | [diff] [blame] | 38 | #ifndef CONFIG_MVGBE_PORTS |
| 39 | # define CONFIG_MVGBE_PORTS {0, 0} |
| 40 | #endif |
| 41 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 42 | #define MV_PHY_ADR_REQUEST 0xee |
| 43 | #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) |
Simon Kagstrom | bb1ca3b | 2009-08-20 10:12:28 +0200 | [diff] [blame] | 44 | |
Sebastian Hesselbarth | cd3ca3f | 2012-12-04 09:32:00 +0100 | [diff] [blame] | 45 | #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
Chris Packham | 5194ed7 | 2018-06-09 20:46:16 +1200 | [diff] [blame] | 46 | static int smi_wait_ready(struct mvgbe_device *dmvgbe) |
| 47 | { |
| 48 | int ret; |
| 49 | |
| 50 | ret = wait_for_bit_le32(&MVGBE_SMI_REG, MVGBE_PHY_SMI_BUSY_MASK, false, |
| 51 | MVGBE_PHY_SMI_TIMEOUT_MS, false); |
| 52 | if (ret) { |
| 53 | printf("Error: SMI busy timeout\n"); |
| 54 | return ret; |
| 55 | } |
| 56 | |
| 57 | return 0; |
| 58 | } |
| 59 | |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 60 | static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr, |
| 61 | int devad, int reg_ofs) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 62 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 63 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 64 | u32 smi_reg; |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 65 | u32 timeout; |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 66 | u16 data = 0; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 67 | |
| 68 | /* Phyadr read request */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 69 | if (phy_adr == MV_PHY_ADR_REQUEST && |
| 70 | reg_ofs == MV_PHY_ADR_REQUEST) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 71 | /* */ |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 72 | data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); |
| 73 | return data; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 74 | } |
| 75 | /* check parameters */ |
| 76 | if (phy_adr > PHYADR_MASK) { |
| 77 | printf("Err..(%s) Invalid PHY address %d\n", |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 78 | __func__, phy_adr); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 79 | return -EFAULT; |
| 80 | } |
| 81 | if (reg_ofs > PHYREG_MASK) { |
| 82 | printf("Err..(%s) Invalid register offset %d\n", |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 83 | __func__, reg_ofs); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 84 | return -EFAULT; |
| 85 | } |
| 86 | |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 87 | /* wait till the SMI is not busy */ |
Chris Packham | 5194ed7 | 2018-06-09 20:46:16 +1200 | [diff] [blame] | 88 | if (smi_wait_ready(dmvgbe) < 0) |
| 89 | return -EFAULT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 90 | |
| 91 | /* fill the phy address and regiser offset and read opcode */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 92 | smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) |
| 93 | | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS) |
| 94 | | MVGBE_PHY_SMI_OPCODE_READ; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 95 | |
| 96 | /* write the smi register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 97 | MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 98 | |
| 99 | /*wait till read value is ready */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 100 | timeout = MVGBE_PHY_SMI_TIMEOUT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 101 | |
| 102 | do { |
| 103 | /* read smi register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 104 | smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 105 | if (timeout-- == 0) { |
| 106 | printf("Err..(%s) SMI read ready timeout\n", |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 107 | __func__); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 108 | return -EFAULT; |
| 109 | } |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 110 | } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 111 | |
| 112 | /* Wait for the data to update in the SMI register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 113 | for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++) |
| 114 | ; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 115 | |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 116 | data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 117 | |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 118 | debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs, |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 119 | data); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 120 | |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 121 | return data; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | /* |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 125 | * smi_reg_read - miiphy_read callback function. |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 126 | * |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 127 | * Returns 16bit phy register value, or -EFAULT on error |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 128 | */ |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 129 | static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad, |
| 130 | int reg_ofs) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 131 | { |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 132 | #ifdef CONFIG_DM_ETH |
| 133 | struct mvgbe_device *dmvgbe = bus->priv; |
| 134 | #else |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 135 | struct eth_device *dev = eth_get_dev_by_name(bus->name); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 136 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 137 | #endif |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 138 | |
| 139 | return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs); |
| 140 | } |
| 141 | |
| 142 | static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr, |
| 143 | int devad, int reg_ofs, u16 data) |
| 144 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 145 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 146 | u32 smi_reg; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 147 | |
| 148 | /* Phyadr write request*/ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 149 | if (phy_adr == MV_PHY_ADR_REQUEST && |
| 150 | reg_ofs == MV_PHY_ADR_REQUEST) { |
| 151 | MVGBE_REG_WR(regs->phyadr, data); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | /* check parameters */ |
| 156 | if (phy_adr > PHYADR_MASK) { |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 157 | printf("Err..(%s) Invalid phy address\n", __func__); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 158 | return -EINVAL; |
| 159 | } |
| 160 | if (reg_ofs > PHYREG_MASK) { |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 161 | printf("Err..(%s) Invalid register offset\n", __func__); |
Chris Packham | 5194ed7 | 2018-06-09 20:46:16 +1200 | [diff] [blame] | 162 | return -EFAULT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | /* wait till the SMI is not busy */ |
Chris Packham | 5194ed7 | 2018-06-09 20:46:16 +1200 | [diff] [blame] | 166 | if (smi_wait_ready(dmvgbe) < 0) |
| 167 | return -EFAULT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 168 | |
| 169 | /* fill the phy addr and reg offset and write opcode and data */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 170 | smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS); |
| 171 | smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) |
| 172 | | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS); |
| 173 | smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 174 | |
| 175 | /* write the smi register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 176 | MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 177 | |
| 178 | return 0; |
| 179 | } |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 180 | |
| 181 | /* |
| 182 | * smi_reg_write - miiphy_write callback function. |
| 183 | * |
| 184 | * Returns 0 if write succeed, -EFAULT on error |
| 185 | */ |
| 186 | static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, |
| 187 | int reg_ofs, u16 data) |
| 188 | { |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 189 | #ifdef CONFIG_DM_ETH |
| 190 | struct mvgbe_device *dmvgbe = bus->priv; |
| 191 | #else |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 192 | struct eth_device *dev = eth_get_dev_by_name(bus->name); |
| 193 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 194 | #endif |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 195 | |
| 196 | return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data); |
| 197 | } |
Stefan Bigler | cc79697 | 2012-03-26 00:02:13 +0000 | [diff] [blame] | 198 | #endif |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 199 | |
| 200 | /* Stop and checks all queues */ |
| 201 | static void stop_queue(u32 * qreg) |
| 202 | { |
| 203 | u32 reg_data; |
| 204 | |
| 205 | reg_data = readl(qreg); |
| 206 | |
| 207 | if (reg_data & 0xFF) { |
| 208 | /* Issue stop command for active channels only */ |
| 209 | writel((reg_data << 8), qreg); |
| 210 | |
| 211 | /* Wait for all queue activity to terminate. */ |
| 212 | do { |
| 213 | /* |
| 214 | * Check port cause register that all queues |
| 215 | * are stopped |
| 216 | */ |
| 217 | reg_data = readl(qreg); |
| 218 | } |
| 219 | while (reg_data & 0xFF); |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * set_access_control - Config address decode parameters for Ethernet unit |
| 225 | * |
| 226 | * This function configures the address decode parameters for the Gigabit |
| 227 | * Ethernet Controller according the given parameters struct. |
| 228 | * |
| 229 | * @regs Register struct pointer. |
| 230 | * @param Address decode parameter struct. |
| 231 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 232 | static void set_access_control(struct mvgbe_registers *regs, |
| 233 | struct mvgbe_winparam *param) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 234 | { |
| 235 | u32 access_prot_reg; |
| 236 | |
| 237 | /* Set access control register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 238 | access_prot_reg = MVGBE_REG_RD(regs->epap); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 239 | /* clear window permission */ |
| 240 | access_prot_reg &= (~(3 << (param->win * 2))); |
| 241 | access_prot_reg |= (param->access_ctrl << (param->win * 2)); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 242 | MVGBE_REG_WR(regs->epap, access_prot_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 243 | |
| 244 | /* Set window Size reg (SR) */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 245 | MVGBE_REG_WR(regs->barsz[param->win].size, |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 246 | (((param->size / 0x10000) - 1) << 16)); |
| 247 | |
| 248 | /* Set window Base address reg (BA) */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 249 | MVGBE_REG_WR(regs->barsz[param->win].bar, |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 250 | (param->target | param->attrib | param->base_addr)); |
| 251 | /* High address remap reg (HARR) */ |
| 252 | if (param->win < 4) |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 253 | MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 254 | |
| 255 | /* Base address enable reg (BARER) */ |
| 256 | if (param->enable == 1) |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 257 | MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 258 | else |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 259 | MVGBE_REG_BITS_SET(regs->bare, (1 << param->win)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 260 | } |
| 261 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 262 | static void set_dram_access(struct mvgbe_registers *regs) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 263 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 264 | struct mvgbe_winparam win_param; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 265 | int i; |
| 266 | |
| 267 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 268 | /* Set access parameters for DRAM bank i */ |
| 269 | win_param.win = i; /* Use Ethernet window i */ |
| 270 | /* Window target - DDR */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 271 | win_param.target = MVGBE_TARGET_DRAM; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 272 | /* Enable full access */ |
| 273 | win_param.access_ctrl = EWIN_ACCESS_FULL; |
| 274 | win_param.high_addr = 0; |
Albert Aribaud | 49fa6ed | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 275 | /* Get bank base and size */ |
| 276 | win_param.base_addr = gd->bd->bi_dram[i].start; |
| 277 | win_param.size = gd->bd->bi_dram[i].size; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 278 | if (win_param.size == 0) |
| 279 | win_param.enable = 0; |
| 280 | else |
| 281 | win_param.enable = 1; /* Enable the access */ |
| 282 | |
| 283 | /* Enable DRAM bank */ |
| 284 | switch (i) { |
| 285 | case 0: |
| 286 | win_param.attrib = EBAR_DRAM_CS0; |
| 287 | break; |
| 288 | case 1: |
| 289 | win_param.attrib = EBAR_DRAM_CS1; |
| 290 | break; |
| 291 | case 2: |
| 292 | win_param.attrib = EBAR_DRAM_CS2; |
| 293 | break; |
| 294 | case 3: |
| 295 | win_param.attrib = EBAR_DRAM_CS3; |
| 296 | break; |
| 297 | default: |
Albert Aribaud | 49fa6ed | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 298 | /* invalid bank, disable access */ |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 299 | win_param.enable = 0; |
| 300 | win_param.attrib = 0; |
| 301 | break; |
| 302 | } |
| 303 | /* Set the access control for address window(EPAPR) RD/WR */ |
| 304 | set_access_control(regs, &win_param); |
| 305 | } |
| 306 | } |
| 307 | |
| 308 | /* |
| 309 | * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables |
| 310 | * |
| 311 | * Go through all the DA filter tables (Unicast, Special Multicast & Other |
| 312 | * Multicast) and set each entry to 0. |
| 313 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 314 | static void port_init_mac_tables(struct mvgbe_registers *regs) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 315 | { |
| 316 | int table_index; |
| 317 | |
| 318 | /* Clear DA filter unicast table (Ex_dFUT) */ |
| 319 | for (table_index = 0; table_index < 4; ++table_index) |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 320 | MVGBE_REG_WR(regs->dfut[table_index], 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 321 | |
| 322 | for (table_index = 0; table_index < 64; ++table_index) { |
| 323 | /* Clear DA filter special multicast table (Ex_dFSMT) */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 324 | MVGBE_REG_WR(regs->dfsmt[table_index], 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 325 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 326 | MVGBE_REG_WR(regs->dfomt[table_index], 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 327 | } |
| 328 | } |
| 329 | |
| 330 | /* |
| 331 | * port_uc_addr - This function Set the port unicast address table |
| 332 | * |
| 333 | * This function locates the proper entry in the Unicast table for the |
| 334 | * specified MAC nibble and sets its properties according to function |
| 335 | * parameters. |
| 336 | * This function add/removes MAC addresses from the port unicast address |
| 337 | * table. |
| 338 | * |
| 339 | * @uc_nibble Unicast MAC Address last nibble. |
| 340 | * @option 0 = Add, 1 = remove address. |
| 341 | * |
| 342 | * RETURN: 1 if output succeeded. 0 if option parameter is invalid. |
| 343 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 344 | static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble, |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 345 | int option) |
| 346 | { |
| 347 | u32 unicast_reg; |
| 348 | u32 tbl_offset; |
| 349 | u32 reg_offset; |
| 350 | |
| 351 | /* Locate the Unicast table entry */ |
| 352 | uc_nibble = (0xf & uc_nibble); |
| 353 | /* Register offset from unicast table base */ |
| 354 | tbl_offset = (uc_nibble / 4); |
| 355 | /* Entry offset within the above register */ |
| 356 | reg_offset = uc_nibble % 4; |
| 357 | |
| 358 | switch (option) { |
| 359 | case REJECT_MAC_ADDR: |
| 360 | /* |
| 361 | * Clear accepts frame bit at specified unicast |
| 362 | * DA table entry |
| 363 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 364 | unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 365 | unicast_reg &= (0xFF << (8 * reg_offset)); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 366 | MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 367 | break; |
| 368 | case ACCEPT_MAC_ADDR: |
| 369 | /* Set accepts frame bit at unicast DA filter table entry */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 370 | unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 371 | unicast_reg &= (0xFF << (8 * reg_offset)); |
| 372 | unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 373 | MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 374 | break; |
| 375 | default: |
| 376 | return 0; |
| 377 | } |
| 378 | return 1; |
| 379 | } |
| 380 | |
| 381 | /* |
| 382 | * port_uc_addr_set - This function Set the port Unicast address. |
| 383 | */ |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 384 | static void port_uc_addr_set(struct mvgbe_device *dmvgbe, u8 *p_addr) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 385 | { |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 386 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 387 | u32 mac_h; |
| 388 | u32 mac_l; |
| 389 | |
| 390 | mac_l = (p_addr[4] << 8) | (p_addr[5]); |
| 391 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | |
| 392 | (p_addr[3] << 0); |
| 393 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 394 | MVGBE_REG_WR(regs->macal, mac_l); |
| 395 | MVGBE_REG_WR(regs->macah, mac_h); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 396 | |
| 397 | /* Accept frames of this address */ |
| 398 | port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); |
| 399 | } |
| 400 | |
| 401 | /* |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 402 | * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 403 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 404 | static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 405 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 406 | struct mvgbe_rxdesc *p_rx_desc; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 407 | int i; |
| 408 | |
| 409 | /* initialize the Rx descriptors ring */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 410 | p_rx_desc = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 411 | for (i = 0; i < RINGSZ; i++) { |
| 412 | p_rx_desc->cmd_sts = |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 413 | MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 414 | p_rx_desc->buf_size = PKTSIZE_ALIGN; |
| 415 | p_rx_desc->byte_cnt = 0; |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 416 | p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 417 | if (i == (RINGSZ - 1)) |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 418 | p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 419 | else { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 420 | p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *) |
| 421 | ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 422 | p_rx_desc = p_rx_desc->nxtdesc_p; |
| 423 | } |
| 424 | } |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 425 | dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 426 | } |
| 427 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 428 | static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr, |
| 429 | const char *name) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 430 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 431 | struct mvgbe_registers *regs = dmvgbe->regs; |
Sascha Silbe | 0611c60 | 2013-08-11 17:08:23 +0200 | [diff] [blame] | 432 | #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ |
| 433 | !defined(CONFIG_PHYLIB) && \ |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 434 | !defined(CONFIG_DM_ETH) && \ |
Sascha Silbe | 0611c60 | 2013-08-11 17:08:23 +0200 | [diff] [blame] | 435 | defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 436 | int i; |
Prafulla Wadaskar | aba8237 | 2009-09-09 15:59:19 +0530 | [diff] [blame] | 437 | #endif |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 438 | /* setup RX rings */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 439 | mvgbe_init_rx_desc_ring(dmvgbe); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 440 | |
| 441 | /* Clear the ethernet port interrupts */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 442 | MVGBE_REG_WR(regs->ic, 0); |
| 443 | MVGBE_REG_WR(regs->ice, 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 444 | /* Unmask RX buffer and TX end interrupt */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 445 | MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 446 | /* Unmask phy and link status changes interrupts */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 447 | MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 448 | |
| 449 | set_dram_access(regs); |
| 450 | port_init_mac_tables(regs); |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 451 | port_uc_addr_set(dmvgbe, enetaddr); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 452 | |
| 453 | /* Assign port configuration and command. */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 454 | MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL); |
| 455 | MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); |
| 456 | MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 457 | |
| 458 | /* Assign port SDMA configuration */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 459 | MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); |
| 460 | MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); |
| 461 | MVGBE_REG_WR(regs->tqx[0].tqxtbc, |
| 462 | (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 463 | /* Turn off the port/RXUQ bandwidth limitation */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 464 | MVGBE_REG_WR(regs->pmtu, 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 465 | |
| 466 | /* Set maximum receive buffer to 9700 bytes */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 467 | MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE |
| 468 | | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 469 | |
Prafulla Wadaskar | f0588fd | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 470 | /* Enable port initially */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 471 | MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); |
Prafulla Wadaskar | f0588fd | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 472 | |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 473 | /* |
| 474 | * Set ethernet MTU for leaky bucket mechanism to 0 - this will |
| 475 | * disable the leaky bucket mechanism . |
| 476 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 477 | MVGBE_REG_WR(regs->pmtu, 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 478 | |
| 479 | /* Assignment of Rx CRDB of given RXUQ */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 480 | MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr); |
Albert Aribaud | c19a20d | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 481 | /* ensure previous write is done before enabling Rx DMA */ |
| 482 | isb(); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 483 | /* Enable port Rx. */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 484 | MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 485 | |
Sebastian Hesselbarth | cd3ca3f | 2012-12-04 09:32:00 +0100 | [diff] [blame] | 486 | #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ |
| 487 | !defined(CONFIG_PHYLIB) && \ |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 488 | !defined(CONFIG_DM_ETH) && \ |
Sebastian Hesselbarth | cd3ca3f | 2012-12-04 09:32:00 +0100 | [diff] [blame] | 489 | defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 490 | /* Wait up to 5s for the link status */ |
| 491 | for (i = 0; i < 5; i++) { |
| 492 | u16 phyadr; |
| 493 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 494 | miiphy_read(name, MV_PHY_ADR_REQUEST, |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 495 | MV_PHY_ADR_REQUEST, &phyadr); |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 496 | /* Return if we get link up */ |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 497 | if (miiphy_link(name, phyadr)) |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 498 | return 0; |
| 499 | udelay(1000000); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 500 | } |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 501 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 502 | printf("No link on %s\n", name); |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 503 | return -1; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 504 | #endif |
| 505 | return 0; |
| 506 | } |
| 507 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 508 | #ifndef CONFIG_DM_ETH |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 509 | static int mvgbe_init(struct eth_device *dev) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 510 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 511 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 512 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 513 | return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name); |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 514 | } |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 515 | #endif |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 516 | |
| 517 | static void __mvgbe_halt(struct mvgbe_device *dmvgbe) |
| 518 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 519 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 520 | |
| 521 | /* Disable all gigE address decoder */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 522 | MVGBE_REG_WR(regs->bare, 0x3f); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 523 | |
| 524 | stop_queue(®s->tqc); |
| 525 | stop_queue(®s->rqc); |
| 526 | |
Prafulla Wadaskar | f0588fd | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 527 | /* Disable port */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 528 | MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 529 | /* Set port is not reset */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 530 | MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 531 | #ifdef CONFIG_SYS_MII_MODE |
| 532 | /* Set MMI interface up */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 533 | MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 534 | #endif |
| 535 | /* Disable & mask ethernet port interrupts */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 536 | MVGBE_REG_WR(regs->ic, 0); |
| 537 | MVGBE_REG_WR(regs->ice, 0); |
| 538 | MVGBE_REG_WR(regs->pim, 0); |
| 539 | MVGBE_REG_WR(regs->peim, 0); |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 540 | } |
| 541 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 542 | #ifndef CONFIG_DM_ETH |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 543 | static int mvgbe_halt(struct eth_device *dev) |
| 544 | { |
| 545 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 546 | |
| 547 | __mvgbe_halt(dmvgbe); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 548 | |
| 549 | return 0; |
| 550 | } |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 551 | #endif |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 552 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 553 | #ifdef CONFIG_DM_ETH |
| 554 | static int mvgbe_write_hwaddr(struct udevice *dev) |
| 555 | { |
| 556 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 557 | |
| 558 | port_uc_addr_set(dev_get_priv(dev), pdata->enetaddr); |
| 559 | |
| 560 | return 0; |
| 561 | } |
| 562 | #else |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 563 | static int mvgbe_write_hwaddr(struct eth_device *dev) |
Prafulla Wadaskar | b5ce63e | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 564 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 565 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
Prafulla Wadaskar | b5ce63e | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 566 | |
| 567 | /* Programs net device MAC address after initialization */ |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 568 | port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr); |
Prafulla Wadaskar | b5ce63e | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 569 | return 0; |
| 570 | } |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 571 | #endif |
Prafulla Wadaskar | b5ce63e | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 572 | |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 573 | static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr, |
| 574 | int datasize) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 575 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 576 | struct mvgbe_registers *regs = dmvgbe->regs; |
| 577 | struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc; |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 578 | void *p = (void *)dataptr; |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 579 | u32 cmd_sts; |
Anatolij Gustschin | e6e556c | 2011-11-19 08:59:36 +0000 | [diff] [blame] | 580 | u32 txuq0_reg_addr; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 581 | |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 582 | /* Copy buffer if it's misaligned */ |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 583 | if ((u32) dataptr & 0x07) { |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 584 | if (datasize > PKTSIZE_ALIGN) { |
| 585 | printf("Non-aligned data too large (%d)\n", |
| 586 | datasize); |
| 587 | return -1; |
| 588 | } |
| 589 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 590 | memcpy(dmvgbe->p_aligned_txbuf, p, datasize); |
| 591 | p = dmvgbe->p_aligned_txbuf; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 592 | } |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 593 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 594 | p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; |
| 595 | p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; |
| 596 | p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; |
| 597 | p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 598 | p_txdesc->buf_ptr = (u8 *) p; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 599 | p_txdesc->byte_cnt = datasize; |
| 600 | |
Albert Aribaud | c19a20d | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 601 | /* Set this tc desc as zeroth TXUQ */ |
Anatolij Gustschin | e6e556c | 2011-11-19 08:59:36 +0000 | [diff] [blame] | 602 | txuq0_reg_addr = (u32)®s->tcqdp[TXUQ]; |
| 603 | writel((u32) p_txdesc, txuq0_reg_addr); |
Albert Aribaud | c19a20d | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 604 | |
| 605 | /* ensure tx desc writes above are performed before we start Tx DMA */ |
| 606 | isb(); |
| 607 | |
| 608 | /* Apply send command using zeroth TXUQ */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 609 | MVGBE_REG_WR(regs->tqc, (1 << TXUQ)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 610 | |
| 611 | /* |
| 612 | * wait for packet xmit completion |
| 613 | */ |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 614 | cmd_sts = readl(&p_txdesc->cmd_sts); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 615 | while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 616 | /* return fail if error is detected */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 617 | if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == |
| 618 | (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) && |
| 619 | cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 620 | printf("Err..(%s) in xmit packet\n", __func__); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 621 | return -1; |
| 622 | } |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 623 | cmd_sts = readl(&p_txdesc->cmd_sts); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 624 | }; |
| 625 | return 0; |
| 626 | } |
| 627 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 628 | #ifndef CONFIG_DM_ETH |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 629 | static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 630 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 631 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 632 | |
| 633 | return __mvgbe_send(dmvgbe, dataptr, datasize); |
| 634 | } |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 635 | #endif |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 636 | |
| 637 | static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp) |
| 638 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 639 | struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 640 | u32 cmd_sts; |
| 641 | u32 timeout = 0; |
Anatolij Gustschin | e6e556c | 2011-11-19 08:59:36 +0000 | [diff] [blame] | 642 | u32 rxdesc_curr_addr; |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 643 | unsigned char *data; |
| 644 | int rx_bytes = 0; |
| 645 | |
| 646 | *packetp = NULL; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 647 | |
| 648 | /* wait untill rx packet available or timeout */ |
| 649 | do { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 650 | if (timeout < MVGBE_PHY_SMI_TIMEOUT) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 651 | timeout++; |
| 652 | else { |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 653 | debug("%s time out...\n", __func__); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 654 | return -1; |
| 655 | } |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 656 | } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 657 | |
| 658 | if (p_rxdesc_curr->byte_cnt != 0) { |
| 659 | debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 660 | __func__, (u32) p_rxdesc_curr->byte_cnt, |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 661 | (u32) p_rxdesc_curr->buf_ptr, |
| 662 | (u32) p_rxdesc_curr->cmd_sts); |
| 663 | } |
| 664 | |
| 665 | /* |
| 666 | * In case received a packet without first/last bits on |
| 667 | * OR the error summary bit is on, |
| 668 | * the packets needs to be dropeed. |
| 669 | */ |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 670 | cmd_sts = readl(&p_rxdesc_curr->cmd_sts); |
| 671 | |
| 672 | if ((cmd_sts & |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 673 | (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) |
| 674 | != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 675 | |
| 676 | printf("Err..(%s) Dropping packet spread on" |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 677 | " multiple descriptors\n", __func__); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 678 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 679 | } else if (cmd_sts & MVGBE_ERROR_SUMMARY) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 680 | |
| 681 | printf("Err..(%s) Dropping packet with errors\n", |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 682 | __func__); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 683 | |
| 684 | } else { |
| 685 | /* !!! call higher layer processing */ |
| 686 | debug("%s: Sending Received packet to" |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 687 | " upper layer (net_process_received_packet)\n", |
| 688 | __func__); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 689 | |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 690 | data = (p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET); |
| 691 | rx_bytes = (int)(p_rxdesc_curr->byte_cnt - |
| 692 | RX_BUF_OFFSET); |
| 693 | |
| 694 | *packetp = data; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 695 | } |
| 696 | /* |
| 697 | * free these descriptors and point next in the ring |
| 698 | */ |
| 699 | p_rxdesc_curr->cmd_sts = |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 700 | MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 701 | p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; |
| 702 | p_rxdesc_curr->byte_cnt = 0; |
| 703 | |
Anatolij Gustschin | e6e556c | 2011-11-19 08:59:36 +0000 | [diff] [blame] | 704 | rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr; |
| 705 | writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr); |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 706 | |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 707 | return rx_bytes; |
| 708 | } |
| 709 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 710 | #ifndef CONFIG_DM_ETH |
Chris Packham | e9bf75c | 2018-07-09 21:33:59 +1200 | [diff] [blame] | 711 | static int mvgbe_recv(struct eth_device *dev) |
| 712 | { |
| 713 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 714 | uchar *packet; |
| 715 | int ret; |
| 716 | |
| 717 | ret = __mvgbe_recv(dmvgbe, &packet); |
| 718 | if (ret < 0) |
| 719 | return ret; |
| 720 | |
| 721 | net_process_received_packet(packet, ret); |
| 722 | |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 723 | return 0; |
| 724 | } |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 725 | #endif |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 726 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 727 | #if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH) |
| 728 | #if defined(CONFIG_DM_ETH) |
| 729 | static struct phy_device *__mvgbe_phy_init(struct udevice *dev, |
| 730 | struct mii_dev *bus, |
| 731 | phy_interface_t phy_interface, |
| 732 | int phyid) |
| 733 | #else |
| 734 | static struct phy_device *__mvgbe_phy_init(struct eth_device *dev, |
| 735 | struct mii_dev *bus, |
| 736 | phy_interface_t phy_interface, |
| 737 | int phyid) |
| 738 | #endif |
| 739 | { |
| 740 | struct phy_device *phydev; |
| 741 | |
| 742 | /* Set phy address of the port */ |
| 743 | miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST, |
| 744 | phyid); |
| 745 | |
| 746 | phydev = phy_connect(bus, phyid, dev, phy_interface); |
| 747 | if (!phydev) { |
| 748 | printf("phy_connect failed\n"); |
| 749 | return NULL; |
| 750 | } |
| 751 | |
| 752 | phy_config(phydev); |
| 753 | phy_startup(phydev); |
| 754 | |
| 755 | return phydev; |
| 756 | } |
| 757 | #endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */ |
| 758 | |
| 759 | #if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH) |
Sebastian Hesselbarth | cd3ca3f | 2012-12-04 09:32:00 +0100 | [diff] [blame] | 760 | int mvgbe_phylib_init(struct eth_device *dev, int phyid) |
| 761 | { |
| 762 | struct mii_dev *bus; |
| 763 | struct phy_device *phydev; |
| 764 | int ret; |
| 765 | |
| 766 | bus = mdio_alloc(); |
| 767 | if (!bus) { |
| 768 | printf("mdio_alloc failed\n"); |
| 769 | return -ENOMEM; |
| 770 | } |
Chris Packham | 6ecf9e2 | 2016-11-01 10:48:32 +1300 | [diff] [blame] | 771 | bus->read = smi_reg_read; |
| 772 | bus->write = smi_reg_write; |
Ben Whitten | 192bc69 | 2015-12-30 13:05:58 +0000 | [diff] [blame] | 773 | strcpy(bus->name, dev->name); |
Sebastian Hesselbarth | cd3ca3f | 2012-12-04 09:32:00 +0100 | [diff] [blame] | 774 | |
| 775 | ret = mdio_register(bus); |
| 776 | if (ret) { |
| 777 | printf("mdio_register failed\n"); |
| 778 | free(bus); |
| 779 | return -ENOMEM; |
| 780 | } |
| 781 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 782 | phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid); |
| 783 | if (!phydev) |
Sebastian Hesselbarth | cd3ca3f | 2012-12-04 09:32:00 +0100 | [diff] [blame] | 784 | return -ENODEV; |
Sebastian Hesselbarth | cd3ca3f | 2012-12-04 09:32:00 +0100 | [diff] [blame] | 785 | |
| 786 | return 0; |
| 787 | } |
| 788 | #endif |
| 789 | |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 790 | static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe) |
| 791 | { |
| 792 | dmvgbe->p_rxdesc = memalign(PKTALIGN, |
| 793 | MV_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1); |
| 794 | if (!dmvgbe->p_rxdesc) |
| 795 | goto error1; |
| 796 | |
| 797 | dmvgbe->p_rxbuf = memalign(PKTALIGN, |
| 798 | RINGSZ * PKTSIZE_ALIGN + 1); |
| 799 | if (!dmvgbe->p_rxbuf) |
| 800 | goto error2; |
| 801 | |
| 802 | dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); |
| 803 | if (!dmvgbe->p_aligned_txbuf) |
| 804 | goto error3; |
| 805 | |
| 806 | dmvgbe->p_txdesc = memalign(PKTALIGN, sizeof(struct mvgbe_txdesc) + 1); |
| 807 | if (!dmvgbe->p_txdesc) |
| 808 | goto error4; |
| 809 | |
| 810 | return 0; |
| 811 | |
| 812 | error4: |
| 813 | free(dmvgbe->p_aligned_txbuf); |
| 814 | error3: |
| 815 | free(dmvgbe->p_rxbuf); |
| 816 | error2: |
| 817 | free(dmvgbe->p_rxdesc); |
| 818 | error1: |
| 819 | return -ENOMEM; |
| 820 | } |
| 821 | |
| 822 | #ifndef CONFIG_DM_ETH |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 823 | int mvgbe_initialize(bd_t *bis) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 824 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 825 | struct mvgbe_device *dmvgbe; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 826 | struct eth_device *dev; |
| 827 | int devnum; |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 828 | int ret; |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 829 | u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 830 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 831 | for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 832 | /*skip if port is configured not to use */ |
| 833 | if (used_ports[devnum] == 0) |
| 834 | continue; |
| 835 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 836 | dmvgbe = malloc(sizeof(struct mvgbe_device)); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 837 | if (!dmvgbe) |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 838 | return -ENOMEM; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 839 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 840 | memset(dmvgbe, 0, sizeof(struct mvgbe_device)); |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 841 | ret = mvgbe_alloc_buffers(dmvgbe); |
| 842 | if (ret) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 843 | printf("Err.. %s Failed to allocate memory\n", |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 844 | __func__); |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 845 | free(dmvgbe); |
| 846 | return ret; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 847 | } |
| 848 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 849 | dev = &dmvgbe->dev; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 850 | |
Mike Frysinger | f6add13 | 2011-11-10 14:11:04 +0000 | [diff] [blame] | 851 | /* must be less than sizeof(dev->name) */ |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 852 | sprintf(dev->name, "egiga%d", devnum); |
| 853 | |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 854 | switch (devnum) { |
| 855 | case 0: |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 856 | dmvgbe->regs = (void *)MVGBE0_BASE; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 857 | break; |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 858 | #if defined(MVGBE1_BASE) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 859 | case 1: |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 860 | dmvgbe->regs = (void *)MVGBE1_BASE; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 861 | break; |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 862 | #endif |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 863 | default: /* this should never happen */ |
| 864 | printf("Err..(%s) Invalid device number %d\n", |
Joe Hershberger | 1fd92db | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 865 | __func__, devnum); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 866 | return -1; |
| 867 | } |
| 868 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 869 | dev->init = (void *)mvgbe_init; |
| 870 | dev->halt = (void *)mvgbe_halt; |
| 871 | dev->send = (void *)mvgbe_send; |
| 872 | dev->recv = (void *)mvgbe_recv; |
| 873 | dev->write_hwaddr = (void *)mvgbe_write_hwaddr; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 874 | |
| 875 | eth_register(dev); |
| 876 | |
Sebastian Hesselbarth | cd3ca3f | 2012-12-04 09:32:00 +0100 | [diff] [blame] | 877 | #if defined(CONFIG_PHYLIB) |
| 878 | mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum); |
| 879 | #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 880 | int retval; |
| 881 | struct mii_dev *mdiodev = mdio_alloc(); |
| 882 | if (!mdiodev) |
| 883 | return -ENOMEM; |
| 884 | strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); |
| 885 | mdiodev->read = smi_reg_read; |
| 886 | mdiodev->write = smi_reg_write; |
| 887 | |
| 888 | retval = mdio_register(mdiodev); |
| 889 | if (retval < 0) |
| 890 | return retval; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 891 | /* Set phy address of the port */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 892 | miiphy_write(dev->name, MV_PHY_ADR_REQUEST, |
| 893 | MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 894 | #endif |
| 895 | } |
| 896 | return 0; |
Prafulla Wadaskar | 0b785dd | 2009-07-01 20:34:51 +0200 | [diff] [blame] | 897 | } |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 898 | #endif |
| 899 | |
| 900 | #ifdef CONFIG_DM_ETH |
| 901 | static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe) |
| 902 | { |
| 903 | return dmvgbe->phyaddr > PHY_MAX_ADDR; |
| 904 | } |
| 905 | |
| 906 | static int mvgbe_start(struct udevice *dev) |
| 907 | { |
| 908 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 909 | struct mvgbe_device *dmvgbe = dev_get_priv(dev); |
| 910 | int ret; |
| 911 | |
| 912 | ret = __mvgbe_init(dmvgbe, pdata->enetaddr, dev->name); |
| 913 | if (ret) |
| 914 | return ret; |
| 915 | |
| 916 | if (!mvgbe_port_is_fixed_link(dmvgbe)) { |
| 917 | dmvgbe->phydev = __mvgbe_phy_init(dev, dmvgbe->bus, |
| 918 | dmvgbe->phy_interface, |
| 919 | dmvgbe->phyaddr); |
| 920 | if (!dmvgbe->phydev) |
| 921 | return -ENODEV; |
| 922 | } |
| 923 | |
| 924 | return 0; |
| 925 | } |
| 926 | |
| 927 | static int mvgbe_send(struct udevice *dev, void *packet, int length) |
| 928 | { |
| 929 | struct mvgbe_device *dmvgbe = dev_get_priv(dev); |
| 930 | |
| 931 | return __mvgbe_send(dmvgbe, packet, length); |
| 932 | } |
| 933 | |
| 934 | static int mvgbe_recv(struct udevice *dev, int flags, uchar **packetp) |
| 935 | { |
| 936 | struct mvgbe_device *dmvgbe = dev_get_priv(dev); |
| 937 | |
| 938 | return __mvgbe_recv(dmvgbe, packetp); |
| 939 | } |
| 940 | |
| 941 | static void mvgbe_stop(struct udevice *dev) |
| 942 | { |
| 943 | struct mvgbe_device *dmvgbe = dev_get_priv(dev); |
| 944 | |
| 945 | __mvgbe_halt(dmvgbe); |
| 946 | } |
| 947 | |
| 948 | static int mvgbe_probe(struct udevice *dev) |
| 949 | { |
| 950 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 951 | struct mvgbe_device *dmvgbe = dev_get_priv(dev); |
| 952 | struct mii_dev *bus; |
| 953 | int ret; |
| 954 | |
| 955 | ret = mvgbe_alloc_buffers(dmvgbe); |
| 956 | if (ret) |
| 957 | return ret; |
| 958 | |
| 959 | dmvgbe->regs = (void __iomem *)pdata->iobase; |
| 960 | |
| 961 | bus = mdio_alloc(); |
| 962 | if (!bus) { |
| 963 | printf("Failed to allocate MDIO bus\n"); |
| 964 | return -ENOMEM; |
| 965 | } |
| 966 | |
| 967 | bus->read = smi_reg_read; |
| 968 | bus->write = smi_reg_write; |
| 969 | snprintf(bus->name, sizeof(bus->name), dev->name); |
| 970 | bus->priv = dmvgbe; |
| 971 | dmvgbe->bus = bus; |
| 972 | |
| 973 | ret = mdio_register(bus); |
| 974 | if (ret < 0) |
| 975 | return ret; |
| 976 | |
| 977 | return 0; |
| 978 | } |
| 979 | |
| 980 | static const struct eth_ops mvgbe_ops = { |
| 981 | .start = mvgbe_start, |
| 982 | .send = mvgbe_send, |
| 983 | .recv = mvgbe_recv, |
| 984 | .stop = mvgbe_stop, |
| 985 | .write_hwaddr = mvgbe_write_hwaddr, |
| 986 | }; |
| 987 | |
| 988 | static int mvgbe_ofdata_to_platdata(struct udevice *dev) |
| 989 | { |
| 990 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 991 | struct mvgbe_device *dmvgbe = dev_get_priv(dev); |
| 992 | void *blob = (void *)gd->fdt_blob; |
| 993 | int node = dev_of_offset(dev); |
| 994 | const char *phy_mode; |
| 995 | int fl_node; |
| 996 | int pnode; |
| 997 | unsigned long addr; |
| 998 | |
| 999 | pdata->iobase = devfdt_get_addr(dev); |
| 1000 | pdata->phy_interface = -1; |
| 1001 | |
| 1002 | pnode = fdt_node_offset_by_compatible(blob, node, |
| 1003 | "marvell,kirkwood-eth-port"); |
| 1004 | |
| 1005 | /* Get phy-mode / phy_interface from DT */ |
| 1006 | phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL); |
| 1007 | if (phy_mode) |
| 1008 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
Chris Packham | 92f129f | 2018-12-04 19:54:30 +1300 | [diff] [blame] | 1009 | else |
| 1010 | pdata->phy_interface = PHY_INTERFACE_MODE_GMII; |
Chris Packham | fb73107 | 2018-07-09 21:34:00 +1200 | [diff] [blame] | 1011 | |
| 1012 | dmvgbe->phy_interface = pdata->phy_interface; |
| 1013 | |
| 1014 | /* fetch 'fixed-link' property */ |
| 1015 | fl_node = fdt_subnode_offset(blob, pnode, "fixed-link"); |
| 1016 | if (fl_node != -FDT_ERR_NOTFOUND) { |
| 1017 | /* set phy_addr to invalid value for fixed link */ |
| 1018 | dmvgbe->phyaddr = PHY_MAX_ADDR + 1; |
| 1019 | dmvgbe->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex"); |
| 1020 | dmvgbe->speed = fdtdec_get_int(blob, fl_node, "speed", 0); |
| 1021 | } else { |
| 1022 | /* Now read phyaddr from DT */ |
| 1023 | addr = fdtdec_lookup_phandle(blob, pnode, "phy-handle"); |
| 1024 | if (addr > 0) |
| 1025 | dmvgbe->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); |
| 1026 | } |
| 1027 | |
| 1028 | return 0; |
| 1029 | } |
| 1030 | |
| 1031 | static const struct udevice_id mvgbe_ids[] = { |
| 1032 | { .compatible = "marvell,kirkwood-eth" }, |
| 1033 | { } |
| 1034 | }; |
| 1035 | |
| 1036 | U_BOOT_DRIVER(mvgbe) = { |
| 1037 | .name = "mvgbe", |
| 1038 | .id = UCLASS_ETH, |
| 1039 | .of_match = mvgbe_ids, |
| 1040 | .ofdata_to_platdata = mvgbe_ofdata_to_platdata, |
| 1041 | .probe = mvgbe_probe, |
| 1042 | .ops = &mvgbe_ops, |
| 1043 | .priv_auto_alloc_size = sizeof(struct mvgbe_device), |
| 1044 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), |
| 1045 | }; |
| 1046 | #endif /* CONFIG_DM_ETH */ |