blob: a995e32bb98cfc3dd1f5dc2a9efb4ed3b044516f [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "x86 architecture"
2 depends on X86
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "x86"
6
Masahiro Yamadadd840582014-07-30 14:08:14 +09007choice
Bin Meng65c4ac02015-04-27 23:22:24 +08008 prompt "Mainboard vendor"
Bin Meng99a309f2015-05-07 21:34:09 +08009 default VENDOR_EMULATION
Masahiro Yamadadd840582014-07-30 14:08:14 +090010
Bin Meng65c4ac02015-04-27 23:22:24 +080011config VENDOR_COREBOOT
12 bool "coreboot"
Simon Glass8ef07572014-11-12 22:42:07 -070013
Ben Stoltz3dcdd172015-08-04 12:33:46 -060014config VENDOR_EFI
15 bool "efi"
16
Bin Menga65b25d2015-05-07 21:34:08 +080017config VENDOR_EMULATION
18 bool "emulation"
19
Bin Meng65c4ac02015-04-27 23:22:24 +080020config VENDOR_GOOGLE
21 bool "Google"
Masahiro Yamadadd840582014-07-30 14:08:14 +090022
Bin Meng65c4ac02015-04-27 23:22:24 +080023config VENDOR_INTEL
24 bool "Intel"
Bin Mengef46bea2015-02-02 22:35:29 +080025
Masahiro Yamadadd840582014-07-30 14:08:14 +090026endchoice
27
Bin Meng65c4ac02015-04-27 23:22:24 +080028# board-specific options below
29source "board/coreboot/Kconfig"
Ben Stoltz3e9aa322015-08-04 12:33:47 -060030source "board/efi/Kconfig"
Bin Menga65b25d2015-05-07 21:34:08 +080031source "board/emulation/Kconfig"
Bin Meng65c4ac02015-04-27 23:22:24 +080032source "board/google/Kconfig"
33source "board/intel/Kconfig"
34
Bin Meng029194a2015-04-27 23:22:25 +080035# platform-specific options below
36source "arch/x86/cpu/baytrail/Kconfig"
37source "arch/x86/cpu/coreboot/Kconfig"
38source "arch/x86/cpu/ivybridge/Kconfig"
Bin Menga65b25d2015-05-07 21:34:08 +080039source "arch/x86/cpu/qemu/Kconfig"
Bin Meng029194a2015-04-27 23:22:25 +080040source "arch/x86/cpu/quark/Kconfig"
41source "arch/x86/cpu/queensbay/Kconfig"
42
43# architecture-specific options below
44
Simon Glassb724bd72015-02-11 16:32:59 -070045config SYS_MALLOC_F_LEN
46 default 0x800
47
Simon Glass70a09c62014-11-12 22:42:10 -070048config RAMBASE
49 hex
50 default 0x100000
51
Simon Glass70a09c62014-11-12 22:42:10 -070052config XIP_ROM_SIZE
53 hex
Bin Meng7698d362015-01-06 22:14:16 +080054 depends on X86_RESET_VECTOR
Simon Glassbbd43d62015-01-01 16:17:54 -070055 default ROM_SIZE
Simon Glass70a09c62014-11-12 22:42:10 -070056
57config CPU_ADDR_BITS
58 int
59 default 36
60
Simon Glass65dd74a2014-11-12 22:42:28 -070061config HPET_ADDRESS
62 hex
63 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
64
65config SMM_TSEG
66 bool
67 default n
68
69config SMM_TSEG_SIZE
70 hex
71
Bin Meng8cb20cc2015-01-06 22:14:15 +080072config X86_RESET_VECTOR
73 bool
74 default n
75
Bin Meng343fb992015-06-07 11:33:12 +080076config RESET_SEG_START
77 hex
78 depends on X86_RESET_VECTOR
79 default 0xffff0000
80
81config RESET_SEG_SIZE
82 hex
83 depends on X86_RESET_VECTOR
84 default 0x10000
85
86config RESET_VEC_LOC
87 hex
88 depends on X86_RESET_VECTOR
89 default 0xfffffff0
90
Bin Meng8cb20cc2015-01-06 22:14:15 +080091config SYS_X86_START16
92 hex
93 depends on X86_RESET_VECTOR
94 default 0xfffff800
95
Simon Glass3ba5f742015-11-26 19:51:30 -070096config DM_PCI_COMPAT
97 default y # Until we finish moving over to the new API
98
Bin Meng64542f42014-12-12 21:05:19 +080099config BOARD_ROMSIZE_KB_512
100 bool
101config BOARD_ROMSIZE_KB_1024
102 bool
103config BOARD_ROMSIZE_KB_2048
104 bool
105config BOARD_ROMSIZE_KB_4096
106 bool
107config BOARD_ROMSIZE_KB_8192
108 bool
109config BOARD_ROMSIZE_KB_16384
110 bool
111
112choice
113 prompt "ROM chip size"
Bin Meng7698d362015-01-06 22:14:16 +0800114 depends on X86_RESET_VECTOR
Bin Meng64542f42014-12-12 21:05:19 +0800115 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
116 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
117 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
118 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
119 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
120 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
121 help
122 Select the size of the ROM chip you intend to flash U-Boot on.
123
124 The build system will take care of creating a u-boot.rom file
125 of the matching size.
126
127config UBOOT_ROMSIZE_KB_512
128 bool "512 KB"
129 help
130 Choose this option if you have a 512 KB ROM chip.
131
132config UBOOT_ROMSIZE_KB_1024
133 bool "1024 KB (1 MB)"
134 help
135 Choose this option if you have a 1024 KB (1 MB) ROM chip.
136
137config UBOOT_ROMSIZE_KB_2048
138 bool "2048 KB (2 MB)"
139 help
140 Choose this option if you have a 2048 KB (2 MB) ROM chip.
141
142config UBOOT_ROMSIZE_KB_4096
143 bool "4096 KB (4 MB)"
144 help
145 Choose this option if you have a 4096 KB (4 MB) ROM chip.
146
147config UBOOT_ROMSIZE_KB_8192
148 bool "8192 KB (8 MB)"
149 help
150 Choose this option if you have a 8192 KB (8 MB) ROM chip.
151
152config UBOOT_ROMSIZE_KB_16384
153 bool "16384 KB (16 MB)"
154 help
155 Choose this option if you have a 16384 KB (16 MB) ROM chip.
156
157endchoice
158
159# Map the config names to an integer (KB).
160config UBOOT_ROMSIZE_KB
161 int
162 default 512 if UBOOT_ROMSIZE_KB_512
163 default 1024 if UBOOT_ROMSIZE_KB_1024
164 default 2048 if UBOOT_ROMSIZE_KB_2048
165 default 4096 if UBOOT_ROMSIZE_KB_4096
166 default 8192 if UBOOT_ROMSIZE_KB_8192
167 default 16384 if UBOOT_ROMSIZE_KB_16384
168
169# Map the config names to a hex value (bytes).
Simon Glassfce7b272014-11-12 22:42:08 -0700170config ROM_SIZE
171 hex
Bin Meng64542f42014-12-12 21:05:19 +0800172 default 0x80000 if UBOOT_ROMSIZE_KB_512
173 default 0x100000 if UBOOT_ROMSIZE_KB_1024
174 default 0x200000 if UBOOT_ROMSIZE_KB_2048
175 default 0x400000 if UBOOT_ROMSIZE_KB_4096
176 default 0x800000 if UBOOT_ROMSIZE_KB_8192
177 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
178 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
Simon Glassfce7b272014-11-12 22:42:08 -0700179
180config HAVE_INTEL_ME
181 bool "Platform requires Intel Management Engine"
182 help
183 Newer higher-end devices have an Intel Management Engine (ME)
184 which is a very large binary blob (typically 1.5MB) which is
185 required for the platform to work. This enforces a particular
186 SPI flash format. You will need to supply the me.bin file in
187 your board directory.
188
Simon Glass65dd74a2014-11-12 22:42:28 -0700189config X86_RAMTEST
190 bool "Perform a simple RAM test after SDRAM initialisation"
191 help
192 If there is something wrong with SDRAM then the platform will
193 often crash within U-Boot or the kernel. This option enables a
194 very simple RAM test that quickly checks whether the SDRAM seems
195 to work correctly. It is not exhaustive but can save time by
196 detecting obvious failures.
197
Simon Glass8ce24cd2015-01-27 22:13:41 -0700198config HAVE_FSP
199 bool "Add an Firmware Support Package binary"
Simon Glasse49ccea2015-08-04 12:34:00 -0600200 depends on !EFI
Simon Glass8ce24cd2015-01-27 22:13:41 -0700201 help
202 Select this option to add an Firmware Support Package binary to
203 the resulting U-Boot image. It is a binary blob which U-Boot uses
204 to set up SDRAM and other chipset specific initialization.
205
206 Note: Without this binary U-Boot will not be able to set up its
207 SDRAM so will not boot.
208
209config FSP_FILE
210 string "Firmware Support Package binary filename"
211 depends on HAVE_FSP
212 default "fsp.bin"
213 help
214 The filename of the file to use as Firmware Support Package binary
215 in the board directory.
216
217config FSP_ADDR
218 hex "Firmware Support Package binary location"
219 depends on HAVE_FSP
220 default 0xfffc0000
221 help
222 FSP is not Position Independent Code (PIC) and the whole FSP has to
223 be rebased if it is placed at a location which is different from the
224 perferred base address specified during the FSP build. Use Intel's
225 Binary Configuration Tool (BCT) to do the rebase.
226
227 The default base address of 0xfffc0000 indicates that the binary must
228 be located at offset 0xc0000 from the beginning of a 1MB flash device.
229
230config FSP_TEMP_RAM_ADDR
231 hex
Bin Mengd04e30b2015-06-01 21:07:23 +0800232 depends on HAVE_FSP
Simon Glass8ce24cd2015-01-27 22:13:41 -0700233 default 0x2000000
234 help
Bin Meng48aa6c22015-08-20 06:40:20 -0700235 Stack top address which is used in fsp_init() after DRAM is ready and
Simon Glass8ce24cd2015-01-27 22:13:41 -0700236 CAR is disabled.
237
Bin Meng57b10f52015-08-20 06:40:19 -0700238config FSP_SYS_MALLOC_F_LEN
239 hex
240 depends on HAVE_FSP
241 default 0x100000
242 help
243 Additional size of malloc() pool before relocation.
244
Bin Meng3340f2c2015-12-10 22:03:01 -0800245config FSP_USE_UPD
246 bool
247 depends on HAVE_FSP
248 default y
249 help
250 Most FSPs use UPD data region for some FSP customization. But there
251 are still some FSPs that might not even have UPD. For such FSPs,
252 override this to n in their platform Kconfig files.
253
Bin Menge2d76e92015-10-11 21:37:35 -0700254config ENABLE_MRC_CACHE
255 bool "Enable MRC cache"
256 depends on !EFI && !SYS_COREBOOT
257 help
258 Enable this feature to cause MRC data to be cached in NV storage
259 to be used for speeding up boot time on future reboots and/or
260 power cycles.
261
Simon Glass45b5a372015-04-29 22:25:59 -0600262config SMP
263 bool "Enable Symmetric Multiprocessing"
264 default n
265 help
266 Enable use of more than one CPU in U-Boot and the Operating System
267 when loaded. Each CPU will be started up and information can be
268 obtained using the 'cpu' command. If this option is disabled, then
269 only one CPU will be enabled regardless of the number of CPUs
270 available.
271
Bin Meng4c713222015-06-12 14:52:23 +0800272config MAX_CPUS
273 int "Maximum number of CPUs permitted"
274 depends on SMP
275 default 4
276 help
277 When using multi-CPU chips it is possible for U-Boot to start up
278 more than one CPU. The stack memory used by all of these CPUs is
279 pre-allocated so at present U-Boot wants to know the maximum
280 number of CPUs that may be present. Set this to at least as high
281 as the number of CPUs in your system (it uses about 4KB of RAM for
282 each CPU).
283
Simon Glass45b5a372015-04-29 22:25:59 -0600284config AP_STACK_SIZE
285 hex
Bin Meng063374d2015-06-12 14:52:22 +0800286 depends on SMP
Simon Glass45b5a372015-04-29 22:25:59 -0600287 default 0x1000
288 help
289 Each additional CPU started by U-Boot requires its own stack. This
290 option sets the stack size used by each CPU and directly affects
291 the memory used by this initialisation process. Typically 4KB is
292 enough space.
293
Bin Meng786a08e2015-07-06 16:31:33 +0800294config HAVE_VGA_BIOS
295 bool "Add a VGA BIOS image"
296 help
297 Select this option if you have a VGA BIOS image that you would
298 like to add to your ROM.
299
300config VGA_BIOS_FILE
301 string "VGA BIOS image filename"
302 depends on HAVE_VGA_BIOS
303 default "vga.bin"
304 help
305 The filename of the VGA BIOS image in the board directory.
306
307config VGA_BIOS_ADDR
308 hex "VGA BIOS image location"
309 depends on HAVE_VGA_BIOS
310 default 0xfff90000
311 help
312 The location of VGA BIOS image in the SPI flash. For example, base
313 address of 0xfff90000 indicates that the image will be put at offset
314 0x90000 from the beginning of a 1MB flash device.
315
Bin Mengb5b6b012015-04-24 18:10:05 +0800316menu "System tables"
Bin Meng8744bef2015-08-13 00:29:13 -0700317 depends on !EFI && !SYS_COREBOOT
Bin Mengb5b6b012015-04-24 18:10:05 +0800318
319config GENERATE_PIRQ_TABLE
320 bool "Generate a PIRQ table"
321 default n
322 help
323 Generate a PIRQ routing table for this board. The PIRQ routing table
324 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
325 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
326 It specifies the interrupt router information as well how all the PCI
327 devices' interrupt pins are wired to PIRQs.
328
Simon Glass6388e352015-04-28 20:25:10 -0600329config GENERATE_SFI_TABLE
330 bool "Generate a SFI (Simple Firmware Interface) table"
331 help
332 The Simple Firmware Interface (SFI) provides a lightweight method
333 for platform firmware to pass information to the operating system
334 via static tables in memory. Kernel SFI support is required to
335 boot on SFI-only platforms. If you have ACPI tables then these are
336 used instead.
337
338 U-Boot writes this table in write_sfi_table() just before booting
339 the OS.
340
341 For more information, see http://simplefirmware.org
342
Bin Meng07545d82015-06-23 12:18:52 +0800343config GENERATE_MP_TABLE
344 bool "Generate an MP (Multi-Processor) table"
345 default n
346 help
347 Generate an MP (Multi-Processor) table for this board. The MP table
348 provides a way for the operating system to support for symmetric
349 multiprocessing as well as symmetric I/O interrupt handling with
350 the local APIC and I/O APIC.
351
Saket Sinha867bcb62015-08-22 12:20:55 +0530352config GENERATE_ACPI_TABLE
353 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
354 default n
355 help
356 The Advanced Configuration and Power Interface (ACPI) specification
357 provides an open standard for device configuration and management
358 by the operating system. It defines platform-independent interfaces
359 for configuration and power management monitoring.
360
Miao Yana5dd1e62016-01-20 01:57:07 -0800361config QEMU_ACPI_TABLE
362 bool "Load ACPI table from QEMU fw_cfg interface"
363 depends on GENERATE_ACPI_TABLE && QEMU
364 default y
365 help
366 By default, U-Boot generates its own ACPI tables. This option, if
367 enabled, disables U-Boot's version and loads ACPI tables generated
368 by QEMU.
369
Bin Meng721e9922015-10-12 05:23:41 -0700370config GENERATE_SMBIOS_TABLE
371 bool "Generate an SMBIOS (System Management BIOS) table"
372 default y
373 help
374 The System Management BIOS (SMBIOS) specification addresses how
375 motherboard and system vendors present management information about
376 their products in a standard format by extending the BIOS interface
377 on Intel architecture systems.
378
379 Check http://www.dmtf.org/standards/smbios for details.
380
Bin Mengb5b6b012015-04-24 18:10:05 +0800381endmenu
382
383config MAX_PIRQ_LINKS
384 int
385 default 8
386 help
387 This variable specifies the number of PIRQ interrupt links which are
388 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
389 Some newer chipsets offer more than four links, commonly up to PIRQH.
390
391config IRQ_SLOT_COUNT
392 int
393 default 128
394 help
395 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
396 which in turns forms a table of exact 4KiB. The default value 128
397 should be enough for most boards. If this does not fit your board,
398 change it according to your needs.
399
Simon Glass2d934e52015-01-27 22:13:33 -0700400config PCIE_ECAM_BASE
401 hex
Bin Mengba877ef2015-02-02 21:25:09 +0800402 default 0xe0000000
Simon Glass2d934e52015-01-27 22:13:33 -0700403 help
404 This is the memory-mapped address of PCI configuration space, which
405 is only available through the Enhanced Configuration Access
406 Mechanism (ECAM) with PCI Express. It can be set up almost
407 anywhere. Before it is set up, it is possible to access PCI
408 configuration space through I/O access, but memory access is more
409 convenient. Using this, PCI can be scanned and configured. This
410 should be set to a region that does not conflict with memory
411 assigned to PCI devices - i.e. the memory and prefetch regions, as
412 passed to pci_set_region().
413
Bin Meng1ed66482015-07-22 01:21:15 -0700414config PCIE_ECAM_SIZE
415 hex
416 default 0x10000000
417 help
418 This is the size of memory-mapped address of PCI configuration space,
419 which is only available through the Enhanced Configuration Access
420 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
421 so a default 0x10000000 size covers all of the 256 buses which is the
422 maximum number of PCI buses as defined by the PCI specification.
423
Bin Meng1eb39a52015-10-22 19:13:31 -0700424config I8259_PIC
425 bool
426 default y
427 help
428 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
429 slave) interrupt controllers. Include this to have U-Boot set up
430 the interrupt correctly.
431
432config I8254_TIMER
433 bool
434 default y
435 help
436 Intel 8254 timer contains three counters which have fixed uses.
437 Include this to have U-Boot set up the timer correctly.
438
Simon Glass6b44ae62015-11-11 10:05:43 -0700439config I8042_KEYB
440 default y
441
442config DM_KEYBOARD
443 default y
444
Simon Glasse49ccea2015-08-04 12:34:00 -0600445source "arch/x86/lib/efi/Kconfig"
446
Masahiro Yamadadd840582014-07-30 14:08:14 +0900447endmenu